JPS61220462A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPS61220462A JPS61220462A JP60060985A JP6098585A JPS61220462A JP S61220462 A JPS61220462 A JP S61220462A JP 60060985 A JP60060985 A JP 60060985A JP 6098585 A JP6098585 A JP 6098585A JP S61220462 A JPS61220462 A JP S61220462A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- laminated
- laminated metal
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、積層構造の電極を持つ化合物半導体装置に関
するもので、特に悪影響を与える金属間化合物の生成を
防止する８層１層電極構造の砒化ガリウム半導体装置に
係るものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a compound semiconductor device having a laminated structure of electrodes, and in particular, the present invention relates to a compound semiconductor device having an electrode of a laminated structure. This relates to a gallium semiconductor device.
［発明の技術的背景］
現在砒化ガリウム（ＧａＡｓ）半導体装置等の化合物半
導体装置では複数の金ｆｆＪＩをＷ４層した構造の電極
が多く使用されている。 この従来例を図面にもとづい
て以下説明する。 第４図及び第５図はＧａＡｓ半導体
装置の従来の電極構造の断面図である。 第４図におい
て半絶縁性ＧａＡＳ基板１の表面に形成されたＮ＋型導
電領ＩＪ１２上のオーム性電極（第１積層金属層と呼ぶ
）３は２つの金ｊｉ１２を積層したものである。 即ち
第１層目はＮ＋型導電領域２とオーム接触をする金−ゲ
ルマニウム合金層（ＡＵ Ｇｅ層）３ａとし第２１１目
（この例では最上ＩＩ）３ｂは白金（Ｐｔ）、ニッケル
（Ｎｉ ）或いは金（ＡＵ ）としている。 最上層３
ｂを積層する目的は、Ａｕ ＧｅとＧａＡＳ結晶との熱
処理合金化の過程で生ずるＡｕ Ｇｅのポールアップ現
象（局所的にＡＵ Ｇｅが球状に膨れあがる現象）を防
止する為と他の１つはＧｅの酸化防止の為である。 最
上層３ｂがｐｔ層或いはＮｉｌの場合には、これらの層
厚を厚くするとコンタクト抵抗が増加し、耐熱性が悪く
なるので例えばＰｔ１ｌの場合にはその層厚を約３００
ス、Ｎｉ層の場合には約５００Ｘに抑えてコンタクト抵
抗を低くし且つ耐熱性をもたせている。 次にこのオー
ム性の第１積層金属１３の少な（とも一部分と重なるよ
うにワイヤボンディング性が良好な金属からなる第２積
層金属層４を形成する。 この第２積層金属層４は第１
積層金属１１３にその一部が重なる第１１ｉ目４ａとこ
れに積層される第２層目（この例では最上層）４ｂとか
らなる。 こ。[Technical Background of the Invention] Currently, in compound semiconductor devices such as gallium arsenide (GaAs) semiconductor devices, electrodes having a structure in which a plurality of gold ffJI layers are formed in W4 are often used. This conventional example will be explained below based on the drawings. 4 and 5 are cross-sectional views of conventional electrode structures of GaAs semiconductor devices. In FIG. 4, an ohmic electrode (referred to as a first laminated metal layer) 3 on an N+ type conductive region IJ12 formed on the surface of a semi-insulating GaAS substrate 1 is a lamination of two gold ji12. That is, the first layer is a gold-germanium alloy layer (AU Ge layer) 3a that is in ohmic contact with the N+ type conductive region 2, and the 211th layer (Mogami II in this example) 3b is made of platinum (Pt), nickel (Ni) or Gold (AU). Top layer 3
The purpose of stacking b is to prevent the pole-up phenomenon of Au Ge (a phenomenon in which AU Ge locally swells into a spherical shape) that occurs during the heat treatment alloying process of Au Ge and GaAS crystal. This is to prevent Ge from oxidizing. When the uppermost layer 3b is a PT layer or Nil, increasing the thickness of these layers increases contact resistance and deteriorates heat resistance.
In the case of a Ni layer, the contact resistance is suppressed to about 500X to lower the contact resistance and provide heat resistance. Next, a second laminated metal layer 4 made of a metal with good wire bondability is formed so as to overlap a small portion of the first ohmic metal laminated metal 13.
It consists of an 11i-th layer 4a that partially overlaps the laminated metal 113, and a second layer (in this example, the top layer) 4b that is laminated thereon. child.
の最上層４ｂはボンディングパッドとなる部分で、アル
ミニウム（Ａ１）等のボンディング特性の良い金属層で
ある。 この金属層と下地との密着性を保つため通常酸
化シリコン（Ｓｉ Ｏ□）及びＧａＡＳ等に対して共に
密着性の良い例えばチタン（Ｔｉ ）を第２積層金ｊｌ
ｌ１４の第１１ｉ目４ａとする。 また最上層４ｂがＡ
１層の場合は、このＴｉ層４ａはＡ１層と第１積層金１
ｆｆ３との間で金１ｆｉｌ化合物の生成を防止する役目
もはたしている。 第５図は第１積層金属層３と重なら
ない第２積層金属層４の部分と半導体基板との間にＣＶ
Ｄによって堆積したｓ＋ ０２膜６を介在した従来例で
ある。 なお以下の図面において同一符号は同一部分又
は相当部分を表わす。The uppermost layer 4b serves as a bonding pad, and is a metal layer with good bonding properties, such as aluminum (A1). In order to maintain the adhesion between this metal layer and the base, titanium (Ti), which has good adhesion to both silicon oxide (SiO□) and GaAS, is usually used as a second layer of gold.
Let it be the 11i-th 4a of l14. Also, the top layer 4b is A
In the case of one layer, this Ti layer 4a is composed of the A1 layer and the first laminated gold layer 1.
It also serves to prevent the formation of gold 1fil compounds with ff3. FIG. 5 shows a CV between a portion of the second laminated metal layer 4 that does not overlap with the first laminated metal layer 3 and the semiconductor substrate.
This is a conventional example in which an s+02 film 6 deposited by D is interposed. In the drawings below, the same reference numerals represent the same or equivalent parts.
［背景技術の問題点］
第２積層金属層４の最上層をワイヤボンディング性が良
好で且つ材料価格が安いＡ１とした場合法の問題が生ず
る。[Problems with the Background Art] A problem arises when the uppermost layer of the second laminated metal layer 4 is made of A1, which has good wire bonding properties and is cheap in material cost.
即ちＡＩ層４ｂと第１積層金属層３はＴｉ１１４ａによ
り隔てられるが、この金属層３と重なる第２積層金属層
４の周縁部が金属１１３の周縁部より後退して金属層３
の面上にある場合、この部分（第４及び第５図の点線で
示す部分）５の露出したＡ１周面と金属層３の上面とは
、Ｔｉ層厚だけ離れていても互いに反応し易い接近した
状態になる。 この状態で素子製造の後工程で、例えば
、ＣｖＤ等の熱処理を含む工程を行なうとＡ１周面附近
にＡｕ−Ａｌの金ａｍ化合物が形成され易い。That is, the AI layer 4b and the first laminated metal layer 3 are separated by the Ti 114a, but the peripheral edge of the second laminated metal layer 4 that overlaps with this metal layer 3 recedes from the peripheral edge of the metal 113, and the metal layer 3
, the exposed A1 peripheral surface of this portion (the portion indicated by the dotted line in FIGS. 4 and 5) 5 and the upper surface of the metal layer 3 are likely to react with each other even if they are separated by the Ti layer thickness. become close. If, in this state, a step including heat treatment such as CvD is performed in a post-process of device manufacturing, a gold-am compound of Au--Al is likely to be formed near the circumferential surface of A1.
なおＡ１０８層３ａの上にＰｔ １Ｉ３ｂ或いはＮｉ層
３ｂが積層されている場合でも、これらｐｔ層或いはＮ
ｉｌの層厚は前記のようにコンタクト抵抗増加等のため
薄く制限されているので、この膜を通してＡｕ−Ａｌの
反応が起こる。Note that even if a Pt 1I3b or Ni layer 3b is laminated on the A108 layer 3a, these pt layers or N
Since the layer thickness of il is limited to a thin layer due to the increase in contact resistance as described above, the Au--Al reaction occurs through this film.
前記Ａ１周面以外のＡＩ Ｊ１４ｂ面でもＡＵ −ＡＩ
金ｊＩ！間化合物が形成されることがある。 これは第
１積層金属層の最上層３ｂのＰｔ層或いはＮｉ層の層厚
は数百人に抑えられ、第２積層金属層のＴｉ １Ｉ４ａ
の膜厚も薄いので、ＡＬＩ Ｇｅ層３ａのＡＩＩがこれ
らｉｌｌ！ｉＩを通してＡｌ １Ｉ４ｂ ニ達し反応す
るものと思われる。AU-AI on the AI J14b surface other than the A1 peripheral surface
Gold jI! Intermediate compounds may be formed. This is because the thickness of the Pt layer or Ni layer of the top layer 3b of the first laminated metal layer is suppressed to several hundred layers, and the thickness of the Ti layer of the second laminated metal layer is
Since the film thickness of the ALI Ge layer 3a is also thin, the AII of the ALI Ge layer 3a is thin! It is thought that Al 1I4b reaches and reacts through iI.
以上のような従来設計によって量産を行うと第１積層金
１ｉＩＷＪ３と第２積層金属１１４とが互いに重なる部
分及びその近傍に黒く変色した即ちＡｕ −Ａ１金属間
化合物が生成したロットが発生する。When mass production is performed according to the conventional design as described above, a lot is generated in which the first metal layer 1iIWJ3 and the second metal layer 114 overlap with each other and in the vicinity thereof, which is discolored black, that is, an Au-A1 intermetallic compound is formed.
こうしたロフトは次のような障害を起こす。Such lofts cause the following problems:
即ちＡｕ−Ａｌ生成が１１度の場合は反応部分が高抵抗
となり素子の特性劣化を引き起こす。 例えばＭＥＳ
ＦＥＴの場合、ソース抵抗増加による相互コンダクタ
ンス９識の低下等が生ずる。 また反応部分は体積膨張
するので膜の密着性を損なうと共に表面の平坦度（フラ
ットネス）が失われ、均一なパッシベーション族の形成
が困難になる。That is, when Au--Al is generated at 11 degrees, the reaction portion becomes high in resistance, causing deterioration of the characteristics of the device. For example, MES
In the case of FETs, an increase in source resistance causes a decrease in mutual conductance. In addition, the volumetric expansion of the reaction portion impairs the adhesion of the film and the flatness of the surface, making it difficult to form a uniform passivation group.
Ａｕ−Ａｌ生成が中度又は軽疫の場合は、特性や信頼性
上問題は無くとも自動組立工程における表面認ｌｆｆ１
時、ペレットの良品と不良品の識別が困難になる。 即
ちインクを落しである不良ペレットとＡ１の変色してい
るベレットの光反射量が同程度になってしまうからであ
る。If Au-Al formation is moderate or light, surface detection lff1 in the automatic assembly process may occur even if there are no problems with characteristics or reliability.
At times, it becomes difficult to distinguish between good and defective pellets. That is, the amount of light reflected by the defective pellet that has dropped ink and the discolored pellet of A1 will be approximately the same.
［発明の目的］
本発明の目的は、ＧａＡｓ等の化合物半導体装置のオー
ム性の第１積層金属層と、この金属層にその一部が重な
るワイヤボンディング性の良い第２積層金属層との間に
有害な金属間化合物が生成されることのない電極構造を
具備する化合物半導体装置を提供することである。[Object of the Invention] The object of the present invention is to provide a structure between an ohmic first laminated metal layer of a compound semiconductor device such as GaAs and a second laminated metal layer with good wire bondability, which partially overlaps this metal layer. An object of the present invention is to provide a compound semiconductor device having an electrode structure in which no intermetallic compound harmful to the body is generated.
［発明の概要］
本発明のＧａＡＳ等の化合物半導体装置の電極は、第１
積層金属層とこれに一部が重なる第２積層金ｌ１ｌｌと
から構成される。 この第１積層金属層は複数の金属層
を互いに積層してつくられ、その第１層目は、化合物半
導体基板上に形成されたＮ型又はＰ型の導電領域に接し
、これとオーム接触をするＡｕＧｅ等の金ｌ１Ｉｌｌｉ
である。 また最上層はチタン層である。 第２積層金
属層も複数の金属層を互いに積層したもので、その第１
１１目はチタン層、最上層はボンディングパッドとなる
Ａ１等の金属層である。[Summary of the Invention] The electrode of the compound semiconductor device such as GaAS of the present invention has a first
It is composed of a laminated metal layer and a second laminated gold layer l1ll that partially overlaps the laminated metal layer. This first laminated metal layer is made by laminating a plurality of metal layers on each other, and the first layer is in contact with and makes ohmic contact with an N-type or P-type conductive region formed on a compound semiconductor substrate. Gold such as AuGe
It is. Moreover, the top layer is a titanium layer. The second laminated metal layer is also a plurality of metal layers laminated together, and the first
The 11th layer is a titanium layer, and the top layer is a metal layer such as A1 that becomes a bonding pad.
半導体基板上に設けられる電極の主な機能は、基板内の
電圧電流をオーミックに電極内に取り込みこれをボンデ
ィングにより接続される導線より外部に送出することで
ある。 ＧａＡＳ等の化合物半導体装置においてはオー
ム接触をする金属としてはＡｕ Ｇｅ合金が望ましい実
施態様であり、またボンディングパッドとしてはボンデ
ィング性も良く価格も安いアルミニウム（Ａ１）が望ま
しい実施態様である。 しかしＡＵ ＧｅとＡ１との間
には有害なＡｕ−Ａｌの金属間化合物が生成され易い。The main function of the electrodes provided on the semiconductor substrate is to ohmically capture the voltage and current within the substrate into the electrodes and transmit them to the outside through conductive wires connected by bonding. In a compound semiconductor device such as GaAS, the metal for ohmic contact is preferably an AuGe alloy, and the bonding pad is preferably aluminum (A1), which has good bonding properties and is inexpensive. However, harmful Au-Al intermetallic compounds are likely to be generated between AU Ge and A1.
本発明の効果は、望ましい実施態様を例にとれば、第
１積層金属層の最上層を従来の層厚の上限が制限される
Ｐｔ 、Ｎｉに代えて、ＡＵ−ＡＩの生成防止に必要十
分な層厚にすることのできるＴｉとし、第２積層金属層
の第１Ｗ１目のＴｉ１ｌと相俟って、これら両層をＡｕ
Ｇｅ層とＡ１層との間に介在積層し、Ａｕ−Ａｌの生
成を大幅に軽減したものである。 なお第１積層金属層
のＴｉ層の目的は、上記以外にＡＬＩ Ｑｅ層の熱処理
工程におけるボールアップ現象を抑えることもある。
ＡＵ Ｇｅ層中のゲルマニウム（Ｇｅ ）の含有量を濃
度８重量％以下にすればこのＴｉ１ｌにより確実にボー
ルアップの生成を防止できる。Taking a preferred embodiment as an example, the effect of the present invention is that the uppermost layer of the first laminated metal layer is replaced with Pt or Ni, which has a limited upper limit of the conventional layer thickness, and is sufficient to prevent the generation of AU-AI. Ti, which can be made to have a layer thickness of
This layer is interposed between the Ge layer and the A1 layer to significantly reduce the generation of Au-Al. In addition to the above, the purpose of the Ti layer of the first laminated metal layer is to suppress the ball-up phenomenon in the heat treatment process of the ALI Qe layer.
If the content of germanium (Ge) in the AU Ge layer is set to a concentration of 8% by weight or less, this Ti1l can reliably prevent the formation of ball-up.
また第２積層金属層の最上層のボンディングパッドはそ
の下地との密着性がボンディング時の衝撃に十分耐え得
る強さが必要である。 第２積層金属層のＴｉｌの目的
の１つはこのためのものである。 第１積層金属層と重
なる部分以外の第２積層金属層の下がＧａＡＳ基板であ
ってもまたシリコン酸化（Ｓｉ ０２ ）層、けいりん
酸ガラス（ＰＳＧ）層、窒化シリコン（Ｓｉ ３ Ｎｍ
）層及びシリコンナイトライドオキサイド（Ｓｆ ｘ
Ｏｙ Ｎｚ ）層のいずれの絶縁膜であっても又はこ
れ等を組み合わせた複数層の積層からなる絶縁膜であっ
ても、Ｔｉ層との密着が良好であり本発明の望ましい実
施態様である。Further, the bonding pad on the uppermost layer of the second laminated metal layer needs to have sufficient adhesion with the base to withstand shock during bonding. One of the purposes of Til in the second laminated metal layer is for this purpose. Even if the second laminated metal layer other than the portion overlapping with the first laminated metal layer is a GaAS substrate, a silicon oxide (Si 02 ) layer, a silicate glass (PSG) layer, a silicon nitride (Si 3 Nm) layer, etc.
) layer and silicon nitride oxide (Sf x
Regardless of whether the insulating film is an insulating film of the Oy Nz ) layer or an insulating film consisting of a plurality of laminated layers that are a combination of these, the adhesion with the Ti layer is good and this is a desirable embodiment of the present invention.
［発明の実施例］
オーム接触をするＡｕＧｅ層とボンディングパッドのＡ
１層との間にＡｕ−Ａｌの金属間化合物が生成するのを
防止する為、第２積層金属層４の第１層目のＴｉ層の層
厚を厚くすることが考えられたがこの層厚も制限される
。 これは第２積層金ａｍのＴｉＷとＡｌ１１とを１回
の蒸着とリフトオフにより形成することによる。 つま
り（イ）１回のリフトオフ（レジストを溶かしレジスト
上のメタルも同時にとる工程）で蒸着可能な膜厚はレジ
ストパターン（スペーサ）の膜厚（例えば庇形状のレジ
スト厚）未満である。 （ロ）第２積層金属層は、通
常１〜１．５μｍの微細パターンのショットキーゲート
電極と同時に形成するのでスペーサ即ちレジストの微細
バターニングをする関係上レジストの膜厚は最大的１．
１μＩである。[Embodiments of the Invention] A of AuGe layer and bonding pad making ohmic contact
In order to prevent the formation of an Au-Al intermetallic compound between the first layer and the first layer, it was considered to increase the thickness of the first Ti layer of the second laminated metal layer 4, but this layer Thickness is also limited. This is because TiW and Al11 of the second laminated gold am are formed by one-time evaporation and lift-off. In other words, (a) the film thickness that can be deposited in one lift-off (a step of melting the resist and removing the metal on the resist at the same time) is less than the film thickness of the resist pattern (spacer) (for example, the thickness of the eaves-shaped resist). (b) Since the second laminated metal layer is usually formed at the same time as the Schottky gate electrode with a fine pattern of 1 to 1.5 μm, the maximum thickness of the resist is 1.5 μm due to fine patterning of the spacer, that is, the resist.
It is 1μI.
（ハ）良好なボンディング性を得るには最上層のＡｌ１
１厚は１．０μＩ以上は必要である。 以上の（イ）、
（ロ）、（ハ）及び工程のバラツキに対する余裕度（マ
ージン）を考慮して、微細パターンを得るためにスペー
サ厚（レジスト）１．５μ糟、従ってリフトオフが安定
して行なえるために第２積層金ａ層厚１．３μ１１良好
なボンディング性確保のため最上層のＡ１層厚１．０μ
鋼、従ってＴｉ層厚０．３μ−に制限される。(c) To obtain good bonding properties, the top layer Al1
1 thickness is required to be 1.0 μI or more. Above (a),
Considering (b), (c) and the margin for process variations, the spacer thickness (resist) is 1.5 μm in order to obtain a fine pattern. Laminated gold A layer thickness: 1.3μ11 Top layer A1 layer thickness: 1.0μ to ensure good bonding properties
steel, and thus the Ti layer thickness is limited to 0.3 μm.
Ａｕ Ｇｅ層とＡ１層との間を遮蔽するためには前記の
ように層厚が＆Ｉｌ限される第１積層金属層のＰｔ ｌ
１１Ｎｉ ＩＩに代えて制限の少ないＴｉ層とすれば好
結果が得られるという知見を得た。In order to shield between the Au Ge layer and the A1 layer, the Ptl of the first laminated metal layer whose layer thickness is limited as described above is used.
It has been found that good results can be obtained if a Ti layer with fewer restrictions is used in place of 11Ni II.
第１図及び第２図は、本発明によるＧａＡＳ半導体装置
の電極構造の実施例を示す断面図である。1 and 2 are cross-sectional views showing an example of the electrode structure of a GaAS semiconductor device according to the present invention.
第１図に示す例は、オーム性の第１積層金属層３の層厚
をＡｕＧｅ層３ａを２０００Ｘ 、 Ｔ ｉ層３Ｃを３
０００＆とし、ＡｕＧｅのＧｅ重農濃度５％とする。In the example shown in FIG. 1, the layer thickness of the ohmic first laminated metal layer 3 is 2000× for the AuGe layer 3a and 3× for the Ti layer 3C.
000&, and the Ge concentration of AuGe is 5%.
第２積層金属層４の層厚を１１層４ａを３０００ス、Ａ
１層４ｂを１００ＯＯ＆とする。 第２図に示す例は、
各層厚は第１図の電極と同一であるが第１積層金属層と
重なる部分以外の第２積層金属層と半導体基板との間を
ＣｖＤによって堆積した５１０２膜とした点が異なる。The layer thickness of the second laminated metal layer 4 is 11 layers 4a, 3000 mm, A
The thickness of the first layer 4b is 100OO&. The example shown in Figure 2 is
The thickness of each layer is the same as that of the electrode in FIG. 1, except that a 5102 film deposited by CvD is used between the second laminated metal layer and the semiconductor substrate except for the portion overlapping with the first laminated metal layer.
第１図に示す実施例をＭＥＳ ＦＥＴに適用した場合
の製造工程を、第３図（ａ ）ないしくｄ ）にもとづ
いて次に説明する。 （１）半絶縁性ＧａＡｓ基板１
に選択イオン注入法と活性化のためのアンニール技術を
用いてＮ１型領［２及びＮ型領域２′を形成する（第３
図（ａ））。 （２）次にＮ＋型領領域２上開口部を
もった断面が庇形状のレジストパターンをホトリソグラ
フィー技術により形成する。 庇形状とするには例えば
現像する前にモノクロルベンゼンに５分浸漬することに
より容易に達成できる。 （３）次にＡＩＪ Ｑｅと
Ｔｉとを真空蒸着により堆積し、アセトンでレジストを
溶かし去ることでレジスト上の不用なＡＩｌ ＧＣ及び
Ｔｉを取り除き熱処理を行ない第１積層金属層３の第１
層目のオーム接触をするＡｌｌ Ｇｅ層３ａ及び最上Ｗ
（この例では第２層目）のＴｉ層３Ｃを形成する（第３
図（ｂ））。The manufacturing process when the embodiment shown in FIG. 1 is applied to a MES FET will be explained below based on FIGS. 3(a) to 3(d). (1) Semi-insulating GaAs substrate 1
Then, selective ion implantation and annealing technology for activation are used to form N1 type region [2 and N type region 2' (third
Figure (a)). (2) Next, a resist pattern having an opening above the N+ type region 2 and having an eave-shaped cross section is formed by photolithography. The eaves shape can be easily achieved, for example, by immersing the film in monochlorobenzene for 5 minutes before development. (3) Next, AIJ Qe and Ti are deposited by vacuum evaporation, and by dissolving the resist with acetone, unnecessary AIl GC and Ti on the resist are removed, and heat treatment is performed to remove the first layer of the first laminated metal layer 3.
The All Ge layer 3a and the top layer W make ohmic contact with each other.
(second layer in this example) Ti layer 3C is formed (third layer).
Figure (b)).
（４）次にゲートと第２積層金属層４（ボンディングパ
ッド）となる部分が開口した断面が庇形状のレジストパ
ターンを形成しく３）と同様な方法でＴｉ及びＡ１を蒸
着及び処理をして、第２積層金属層４の第１層目の１１
層４ａ及び最上層のＡｌｌ１４ｂ（ボンディングパッド
）とショットキーゲート電極７を形成する（第３図（Ｃ
））。(4) Next, form a resist pattern with an eave-shaped cross section in which the gate and second laminated metal layer 4 (bonding pad) are open, and Ti and A1 are vapor-deposited and treated in the same manner as in 3). , the first layer 11 of the second laminated metal layer 4
The layer 4a and the uppermost layer All14b (bonding pad) and the Schottky gate electrode 7 are formed (see FIG. 3(C)
)).
（５）次に保護膜としてＣｖＤにより５１０２を堆積し
て、ボンディング部分の５ｉＯｚを選択エツチングして
保護膜８を形成する。(5) Next, 5102 is deposited as a protective film by CvD, and 5iOz in the bonding portion is selectively etched to form the protective film 8.
上述の実施例においては第１積層金属閣及び第２積層金
属層はそれぞれ２つの金属層を積層したものであるが例
えば第１積層金属層の第１Ｗ目がＡｕ Ｇｅ層、第２層
目が薄いＮｉ層、最上層がＴｉ層となるように２Ｍ！以
上を積層しても差支えない。 また本発明はオーム接触
をする金属としてＡｕ Ｇｅ以外の八〇を含有する合金
層に対しても適用できる。 また本発明はＧａＡｓ基板
の一部にＧａ ｘ Ａｌ ｗ Ａａ ｚ等が形成されて
いる基板にも勿論適用できる。In the above-described embodiment, the first laminated metal layer and the second laminated metal layer each have two metal layers laminated. For example, the first layer of the first metal layer is an Au Ge layer, and the second layer is an Au Ge layer. 2M so that the thin Ni layer and the top layer are the Ti layer! There is no problem even if the above layers are stacked. Further, the present invention can also be applied to an alloy layer containing 80 other than AuGe as a metal making ohmic contact. Furthermore, the present invention can of course be applied to a GaAs substrate in which Ga x Al w A a z or the like is formed on a part of the substrate.
［発明の効果］
本発明ではボンディングパッドとなるＡｌｌ！の周面は
第１積層金属層の最上層の７ｉ層によりＡｌｌ ０８等
の金属層から遮蔽される。 しかもこのＴｉ１ｌの層厚
は従来のｐｔ、Ｎｉのようにコンタクト抵抗や耐熱性に
影響を及ぼさないので厚くすることができる（約３００
０Ｘ ）。 従って、Ａ１層周面におけるＡｌ−Ａｕ生
成は大幅に軽減される。 また第２積層金属層の第１層
目のＴｉ層も加わるので層厚を稼ぐことができ、Ａｕ−
Ａｌ生成防止をより確実に行なうことができる。 本発
明にお１いてＡｌｌ Ｇｅ層中のＧｅの重量濃度を８％
以下とすることでＡｕ Ｇｅのポールアップ現象を完全
に抑えることができる。 また、重なる部分以外の第２
１’ｉ！ｉｌｌ金属層の下が、ＧａＡＳ基板であっても
Ｓｔ ０２ 、ＰＳＧＳＳｉ ３ Ｎｔ及び３１ ｘＯ
ｙ Ｎｚのいずれの絶縁膜であってもＴ１との密着が良
好なためボンディング時の衝撃に強く、この部分をボン
ディングパッドとすることが可能である。[Effects of the Invention] In the present invention, All! serves as a bonding pad. The peripheral surface of is shielded from the metal layer such as All 08 by the top 7i layer of the first laminated metal layer. Moreover, the layer thickness of this Ti1l can be made thicker (approximately 300 m
0X). Therefore, Al--Au formation on the circumferential surface of the A1 layer is significantly reduced. Also, since the first Ti layer of the second laminated metal layer is added, the layer thickness can be increased, and the Au-
Al generation can be more reliably prevented. In the present invention, the weight concentration of Ge in the All Ge layer is 8%.
The Au Ge pole-up phenomenon can be completely suppressed by the following conditions. In addition, the second part other than the overlapping part
1'i! Even if the bottom of the ill metal layer is a GaAS substrate, St 02 , PSGSSi 3 Nt and 31 xO
Regardless of whether the insulating film is y or Nz, it has good adhesion to T1, so it is strong against impact during bonding, and this portion can be used as a bonding pad.
第１図及び第２図は本発明の化合物半導体装置の電極構
造の２つの実施例を示す断面図、第３図（ａ）ないしく
ｄ）は第１図に示す実施例をＭＥＳ ＦＥＴに適用す
る場合の製造工程を示す断面図、第４図及び第５図は従
来のＱ、ａＡｓ半導体装置の電極構造の断面図である。
１・・・ＧａＡＳ半導体基板、 ２・・・Ｎ＋型導電領
域、 ３・・・第１積層金属層、 ３ａ・・・第１１Ｉ
１１目のオーム接触する金ＩＩ （Ａｕ Ｇｅ ）、
３ｂ−・・従来の最上層、 ３Ｃ・・・本発明による最
上層のＴｉ層、 ４・・・第２積層金属層、 ４ａ・・
・第１層目のＴｉＪｌ、 ４ｂ・・・最上層のボン
ディングパッドとなる金属１ｆ（ＡＩ＞、 ６・・・絶
縁膜。
第１図
５〜へ、
第、２図
第３図
第４図
第５．、ｓ1 and 2 are cross-sectional views showing two embodiments of the electrode structure of the compound semiconductor device of the present invention, and FIGS. 3(a) to 3d) show the embodiment shown in FIG. 1 applied to an MES FET. 4 and 5 are cross-sectional views showing the electrode structure of a conventional Q, aAs semiconductor device. DESCRIPTION OF SYMBOLS 1... GaAS semiconductor substrate, 2... N+ type conductive region, 3... First laminated metal layer, 3a... 11th I
11th ohm contact gold II (Au Ge),
3b-- Conventional top layer, 3C... Top Ti layer according to the present invention, 4... Second laminated metal layer, 4a...
・First layer TiJl, 4b... Metal 1f (AI>, 6... Insulating film, which becomes the bonding pad of the top layer. Figure 1 to 5~, Figure 2, Figure 3, Figure 4) 5.,s
Claims (1)
一導電型領域と、前記一導電型領域表面に接する第１層
目のオーム接触をする金属層及び最上層のチタン層を含
む複数の金属層を互いに積層してなる第１の積層金属層
と、この第１積層金属層と一部で重なり且つ第１層目の
チタン層及び最上層のボンディングパッドとなる金属層
を含む複数の金属層を互いに積層してなる第２の積層金
属層と を具備することを特徴とする化合物半導体装置。 ２ オーム接触をする金属層が濃度８重量％以下のゲル
マニウムを含有する金からなる特許請求の範囲第１項記
載の化合物半導体装置。 ３ ボンディングパッドとなる金属層の主成分がアルミ
ニウムからなる特許請求の範囲第１項記載の化合物半導
体装置。 ４ 第２積層金属層と化合物半導体基板との間に、シリ
コン酸化層、けいりん酸ガラス層、窒化シリコン層及び
シリコンナイトライドオキサイド（Ｓｉ＿ｘＯ＿ｙＮ＿
ｚ）層のうちいずれか１層又は複数層の積層からなる絶
縁膜を有する特許請求の範囲第１項記載の化合物半導体
装置。[Scope of Claims] 1. A compound semiconductor substrate, a region of one conductivity type formed on the surface of the substrate, a metal layer as a first layer making ohmic contact with the surface of the region of one conductivity type, and a titanium layer as the top layer. A first laminated metal layer formed by laminating a plurality of metal layers including a metal layer, and a metal layer that partially overlaps with the first laminated metal layer and serves as a first titanium layer and a top layer bonding pad. and a second laminated metal layer formed by laminating a plurality of metal layers including: 2. The compound semiconductor device according to claim 1, wherein the metal layer making ohmic contact is made of gold containing germanium at a concentration of 8% by weight or less. 3. The compound semiconductor device according to claim 1, wherein the main component of the metal layer serving as the bonding pad is aluminum. 4 Between the second laminated metal layer and the compound semiconductor substrate, a silicon oxide layer, a silicate glass layer, a silicon nitride layer, and a silicon nitride oxide (Si_xO_yN_
z) The compound semiconductor device according to claim 1, comprising an insulating film made of one layer or a stack of a plurality of layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060985A JPS61220462A (en) | 1985-03-27 | 1985-03-27 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60060985A JPS61220462A (en) | 1985-03-27 | 1985-03-27 | Compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61220462A true JPS61220462A (en) | 1986-09-30 |
Family
ID=13158234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60060985A Pending JPS61220462A (en) | 1985-03-27 | 1985-03-27 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220462A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008235728A (en) * | 2007-03-23 | 2008-10-02 | Eudyna Devices Inc | Semiconductor device |
-
1985
- 1985-03-27 JP JP60060985A patent/JPS61220462A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008235728A (en) * | 2007-03-23 | 2008-10-02 | Eudyna Devices Inc | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8748995B2 (en) | Nitride semiconductor device with metal layer formed on active region and coupled with electrode interconnect | |
| US6011281A (en) | Semiconductor device having an ohmic contact and a Schottky contact, with a barrier layer interposed between the ohmic contact and the Schottky contact | |
| US10777667B2 (en) | Semiconductor device | |
| US4695869A (en) | GAAS semiconductor device | |
| US11081573B2 (en) | Semiconductor element | |
| CN114975614A (en) | High electron mobility transistor and manufacturing method thereof | |
| JPS61220462A (en) | Compound semiconductor device | |
| CN111584364A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| JPS62150869A (en) | Compound semiconductor device | |
| JPH065688B2 (en) | Semiconductor device | |
| JP2555871B2 (en) | Gallium arsenide semiconductor device | |
| JPS6128228B2 (en) | ||
| JP3018677B2 (en) | Method for manufacturing semiconductor device | |
| JPS61102071A (en) | Semiconductor device | |
| JP3823826B2 (en) | Manufacturing method of semiconductor device | |
| JPS63160274A (en) | Gallium arsenide semiconductor device | |
| JPS60120560A (en) | Semiconductor device | |
| JPS6323665B2 (en) | ||
| JPH06252357A (en) | Semiconductor element | |
| JPS62104176A (en) | Field effect transistor | |
| JPS6252962A (en) | Semiconductor device | |
| JPH0131310B2 (en) | ||
| JPH01319974A (en) | Semiconductor device | |
| JPH03253084A (en) | Gunndiode | |
| JPH03290931A (en) | Semiconductor device and its manufacture |