JPH065688B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH065688B2
JPH065688B2 JP59162552A JP16255284A JPH065688B2 JP H065688 B2 JPH065688 B2 JP H065688B2 JP 59162552 A JP59162552 A JP 59162552A JP 16255284 A JP16255284 A JP 16255284A JP H065688 B2 JPH065688 B2 JP H065688B2
Authority
JP
Japan
Prior art keywords
layer
electrode
substrate
gaas
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59162552A
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Japanese (ja)
Other versions
JPS6142147A (en
Inventor
康男 宮脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
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Filing date
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Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP59162552A priority Critical patent/JPH065688B2/en
Publication of JPS6142147A publication Critical patent/JPS6142147A/en
Publication of JPH065688B2 publication Critical patent/JPH065688B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、半導体基体としてガリウムヒ素（以下、Ｇａ
Ａｓという。）を用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to gallium arsenide (hereinafter, Ga) as a semiconductor substrate.
Called As. ) Is used for the semiconductor device.

(ロ)従来の技術 ＧａＡｓ基体を用いたＧａＡｓショットキ障壁ゲート電
界効果トランジスタ（以下、ＧａＡｓ−ＭＥＳＦＥＴと
いう。）は、低雑音、高利得など優れた特性をもつマイ
クロ波帯増幅素子として実用化されている。(B) Conventional technology A GaAs Schottky barrier gate field effect transistor (hereinafter referred to as GaAs-MESFET) using a GaAs substrate has been put into practical use as a microwave band amplification element having excellent characteristics such as low noise and high gain. There is.

ＧａＡｓ−ＭＥＳＦＥＴは第４図および第５図に示すよ
うに、Ｃｒドープまたはアンドープの半絶縁体となった
基板(11)上にイオン注入および活性化アニールによりｎ
型（ドナー濃度約１０17cm-3）の活性層(12)を設けたＧ
ａＡｓ半導体基体(1)を備え、活性層(12)上にソースお
よびドレイン電極とゲート電極をリストオフ法により形
成している。すなわち、ソース電極(13)とドレイン電極
(14)を活性層(12)にオーミック接触して設けると共に、
ソース電極13とドレイン電極(14)との間にゲート電極(1
5)(16)を活性層(12)にショットキ接触して設けている。As shown in FIGS. 4 and 5, the GaAs-MESFET is formed by ion implantation and activation annealing on a substrate (11) which is a Cr-doped or undoped semi-insulator.
Type G (donor concentration: about 10 17 cm -3 ) provided with an active layer (12)
An aAs semiconductor substrate (1) is provided, and source and drain electrodes and a gate electrode are formed on the active layer (12) by the wrist-off method. That is, the source electrode (13) and the drain electrode
(14) is provided in ohmic contact with the active layer (12),
Between the source electrode 13 and the drain electrode (14), the gate electrode (1
5) (16) is provided in Schottky contact with the active layer (12).

ところで、ＧａＡｓ基体(1)とオーミック接触をとる方
法としては、基体(1)表面にオーミック接触形成金属を
被着した後、適当な合金化熱処理工程により前記金属と
基体との間に、合金化反応を進行させ、オーミック接触
をとる方法が一般的である。現在用いられているオーミ
ック接触形成金属のうち、最もよく使用されているのは
Ａｕ（金）を主成分とする合金、例えばＡｕＧｅ（金・
ゲルマニウム）合金である。また、特開昭５９−２８３
７６号公報に示すように、オーミック電極の接触抵抗を
減らすためにＡｕＧｅＧａ合金を用いた半導体装置があ
る。By the way, as a method for making ohmic contact with the GaAs substrate (1), after depositing an ohmic contact forming metal on the surface of the substrate (1), an alloying heat treatment step is performed to form an alloy between the metal and the substrate. Generally, a method of advancing the reaction to make ohmic contact is established. Of the currently used ohmic contact forming metals, the one most often used is an alloy containing Au (gold) as a main component, such as AuGe (gold.
Germanium) alloy. In addition, JP-A-59-283
As shown in Japanese Patent Publication No. 76-76, there is a semiconductor device using an AuGeGa alloy in order to reduce the contact resistance of the ohmic electrode.

第６図は従来のソース電極(13)およびドレイン電極(14)
を模式的断面図をもって示すものである。ＧａＡｓ基体
(1)の表面に形成された電極には、外部引出しリード等
の金属体と電気的に接続するためにＡｕ線よりなるリー
ド線(17)がボンディングされる。したがって、その電極
表面にはボンディング性向上のためにＡｕ層(20)が設け
られている。また、ＡｕＧｅ層(21)と電極表面のＡｕ層
(20)との間にＡｕ層(20)の密着性を良好にするためにＴ
ｉ（チタン）層(22)Ｎｉ（ニッケル）層(23)を介在させ
ている。また第７図の様にＡｕＧｅ層(21)、Ｎｉ層(23)
で合金化し、その上にボンディングパツドとしての第２
電極としてＴｉ層(22)、Ａｕ層(20)を形成する場合もあ
る。FIG. 6 shows a conventional source electrode (13) and drain electrode (14)
2 is a schematic sectional view. GaAs substrate
A lead wire (17) made of an Au wire is bonded to the electrode formed on the surface of (1) in order to electrically connect with a metal body such as an external lead. Therefore, the Au layer (20) is provided on the surface of the electrode for improving the bonding property. Also, the AuGe layer (21) and the Au layer on the electrode surface
In order to improve the adhesion of the Au layer (20) with (20), T
The i (titanium) layer (22) and the Ni (nickel) layer (23) are interposed. Also, as shown in FIG. 7, AuGe layer (21), Ni layer (23)
Is alloyed with and then the second bonding pad
A Ti layer (22) and an Au layer (20) may be formed as electrodes.

(ハ)発明が解決しようとする問題点 しかしながら、第６図で示した電極構造では、基体(1)
とＡｕＧｅ層(21)との合金層の破壊強度が小さいためボ
ンディングの際、電極部分の基体(1)のクラックによる
電極ハガレや熱処理後の表面Ａｕ層(20)の変質に伴なう
ボンディング付着性の劣化があった。また第７図の構造
でも第１電極のＮｉ層(23)と第２電極のＴｉ層(22)の接
着強度が小さいため、ボンディングの際第２電極がはが
れる問題があった。(C) Problems to be solved by the invention However, in the electrode structure shown in FIG. 6, the substrate (1)
Since the alloy layer of AuGe layer (21) and AuGe layer (21) has a small fracture strength, bonding is caused by peeling of the electrode due to cracks in the substrate (1) at the electrode portion and deterioration of the surface Au layer (20) after heat treatment during bonding. There was deterioration of sex. Also in the structure of FIG. 7, the adhesion strength between the Ni layer (23) of the first electrode and the Ti layer (22) of the second electrode is small, so that there is a problem that the second electrode peels off during bonding.

(ニ)問題点を解決するための手段 本発明は上述した問題点を解消するためになされたもの
にして、ガリウムヒ素半導体基体と、この半導体基体の
所定領域に接触させた電極とを具備する半導体装置にお
いて、前記電極上に、チタンに金を積層した第２電極層
を配設すると共に、この第２電極層を半導体基体まで延
在して半導体基体と接続させ、半導体基体上に位置する
第２電極層上にリード線をボンディングしたことを特徴
とする。(D) Means for Solving the Problems The present invention has been made to solve the above problems, and comprises a gallium arsenide semiconductor substrate and an electrode in contact with a predetermined region of the semiconductor substrate. In the semiconductor device, a second electrode layer in which titanium and gold are laminated is provided on the electrode, and the second electrode layer extends to the semiconductor base and is connected to the semiconductor base, and is located on the semiconductor base. A lead wire is bonded on the second electrode layer.

(ホ)作用 本発明によれば、ＧａＡｓ基体上に密着性の良好なチタ
ンが接続し、その位置でリード線をボンディングするの
で、電極がボンディング作業の際にはがれるおそれがは
ない。(E) Function According to the present invention, since titanium having good adhesion is connected to the GaAs substrate and the lead wire is bonded at that position, there is no risk of the electrode peeling during the bonding work.

(ヘ)実施例 以下本発明の一実施例を第１図ないし第３図に従い説明
する。第１図は本発明によるＧａＡｓ−ＭＥＳＦＥＴの
上面図、第２図は第１図のII−II線断面図、第３図は本
発明の電極構造を説明するための模式的断面図である。(F) Embodiment An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a top view of a GaAs-MESFET according to the present invention, FIG. 2 is a sectional view taken along line II-II of FIG. 1, and FIG. 3 is a schematic sectional view for explaining an electrode structure of the present invention.

本実施例のＧａＡｓ−ＭＥＳＦＥＴは、第１図および第
２図に示すように、ソース電極(13)とドレイン電極(14)
との間に、第１ゲート電極(15)および第２ゲート電極(1
6)からなる２本のゲート電極を設けたいわゆるデュアル
ゲート構造となっている。第１図において、各電極のボ
ンディング領域は鎖線で示している。As shown in FIGS. 1 and 2, the GaAs-MESFET of this embodiment has a source electrode (13) and a drain electrode (14).
Between the first gate electrode (15) and the second gate electrode (1
It has a so-called dual gate structure provided with two gate electrodes consisting of 6). In FIG. 1, the bonding area of each electrode is shown by a chain line.

ＧａＡｓ−ＭＥＳＦＥＴは、第２図に示すように、Ｃｒ
ドープまたはアンドープによって半絶縁体となった基板
(11)上に、イオン注入および活性化アニールによって形
成したｎ型（ドナー濃度約１０17cm-3）活性層(12)上に
各電極を配している。As shown in FIG. 2, the GaAs-MESFET has a Cr
Substrates that have become semi-insulating by doping or undoping
Each electrode is disposed on the n-type (donor concentration of about 10 17 cm −3 ) active layer (12) formed by ion implantation and activation annealing.

なお基板(11)、ｎ型活性層(12)を含めてＧａＡｓ基体
(1)という。GaAs substrate including the substrate (11) and n-type active layer (12)
(1).

ｎ型活性層(12)表面の中央には１μｍ〜1.5μｍの幅の
２本のゲート電極がショットキ接触して配置される。２
本のゲート電極は、それぞれ、第１ゲート電極(15)およ
び第２ゲート電極(16)を構成する。また、２本のゲート
電極をはさんで、ソース電極(13)とドレイン電極(14)が
オーミック接触して配置される。ここで、ＧａＡｓ基体
(1)とオーミック接触するソース電極(13)およびドレイ
ン電極(14)は第３図に示すように最下層に厚さ１１００
ÅのＡｕ−Ｇｅ層(21)、中間層に厚さ４００ÅのＮｉ層
(23)厚さ１０００ÅのＴｉ層(23)と最上層の厚さ３００
０ÅのＡｕ層(20)を蒸着によって積層して構成されてい
る。At the center of the surface of the n-type active layer 12, two gate electrodes having a width of 1 μm to 1.5 μm are arranged in Schottky contact. Two
The gate electrodes of the book form a first gate electrode (15) and a second gate electrode (16), respectively. Further, the source electrode (13) and the drain electrode (14) are arranged in ohmic contact with each other across the two gate electrodes. Where GaAs substrate
The source electrode (13) and the drain electrode (14) which are in ohmic contact with (1) have a thickness of 1100 at the lowermost layer as shown in FIG.
Å Au-Ge layer (21), 400 Å Ni layer as intermediate layer
(23) Ti layer (23) with a thickness of 1000Å and thickness 300 of the top layer
It is constituted by stacking 0Å Au layers (20) by vapor deposition.

そして、本発明はこのように構成したソース電極(13)お
よびドレイン電極(14)上に、厚さ１０００ÅのＴｉ層(3
0)と厚さ３０００ÅのＡｕ層(31)を積層した第２電極層
(3)を配設し、そして、第２電極層(3)をＧａＡｓ基体
(1)まで延在させ、ＧａＡｓ基体(1)と密着性の高いＴｉ
(30)を接触させる。The present invention provides a Ti layer (3) having a thickness of 1000 Å on the source electrode (13) and the drain electrode (14) thus configured.
0) and a 3000 Å-thick Au layer (31) laminated on the second electrode layer
(3) is arranged, and the second electrode layer (3) is a GaAs substrate.
Ti that extends to (1) and has high adhesion to the GaAs substrate (1)
Contact (30).

また、第１および第２ゲート電極(15)(16)は最下層に厚
さ１５００ÅのＴｉ層と中間層に厚さ５００ÅのＰｔ層
と最上層に厚さ３０００ÅのＡｕ層を蒸着によって積層
して構成される。本実施例では、第１および第２ゲート
電極(15)(16)上にも前述したように第２電極層(3)が配
設されている。The first and second gate electrodes (15, 16) are formed by depositing a Ti layer having a thickness of 1500 Å as a lowermost layer, a Pt layer having a thickness of 500 Å as an intermediate layer, and an Au layer having a thickness of 3000 Å as an uppermost layer. Consists of In this embodiment, the second electrode layer (3) is also provided on the first and second gate electrodes (15) and (16) as described above.

そして、ゲート形成前に合金化熱処理を行うことによっ
て、ソース電極(13)およびドレイン電極(14)はＧａＡｓ
基体(1)にオーミック接触すると共に、第１および第２
ゲート電極(15)(16)はＧａＡｓ基体(1)にショットキ接
触する。また、第２電極層(3)もＧａＡｓ基体(1)にショ
ットキ接触するが、第２電極層(3)がショットキ接触す
るＧａＡｓ基体(1)の箇所は半絶縁体で構成しているの
で、ＧａＡｓ−ＭＥＳＦＥＴの動作に対しては影響を及
ぼさないようになっている。さらには、第２電極層
（３）が活性層（１２）に接触したとしても、Ｔｉ（３
０）がアノードとなるショットキーダイオードが逆方向
に接続され、内部に空乏層を形成するだけであるので、
電流が流れるソース電極〜ゲート電極〜ドレイン電極の
動作領域には何の影響も与えない。Then, by performing an alloying heat treatment before forming the gate, the source electrode (13) and the drain electrode (14) are made of GaAs.
Ohmic contact with the substrate (1), and the first and second
The gate electrodes 15 and 16 are in Schottky contact with the GaAs substrate 1. Also, the second electrode layer (3) is also in Schottky contact with the GaAs substrate (1), but the location of the GaAs substrate (1) in which the second electrode layer (3) is in Schottky contact is made of a semi-insulating material. It does not affect the operation of the GaAs-MESFET. Furthermore, even if the second electrode layer (3) contacts the active layer (12), Ti (3
Since the Schottky diode whose anode is 0) is connected in the opposite direction and only forms the depletion layer inside,
It has no influence on the operating regions of the source electrode, the gate electrode, and the drain electrode through which the current flows.

尚、電極形成領域以外の活性層(12)表面および半絶縁体
基体(11)上には絶縁膜が設けられていると共に、第２電
極層(3)のボンディング領域以外のＧａＡｓ−ＭＥＳＦ
ＥＴ表面はパッシベーション膜が設けられている。An insulating film is provided on the surface of the active layer (12) other than the electrode formation region and on the semi-insulating substrate (11), and the GaAs-MESF other than the bonding region of the second electrode layer (3) is provided.
The ET surface is provided with a passivation film.

而して、リード線(17)の各電極に対するボンディング
は、ＧａＡｓ基板(1)上に位置する第２電極層(3)上に行
われ、リード線(17)が第２電極層(3)上に接続され、電
極の取り出しが行なわれる。すなわち、接着強度の大き
い、第２電極層(3)上でボンディングするので、第２電
極層(3)がはがれるおそれはない。また、たとえ、第２
電極層(3)とＧａＡｓ基体(1)との間に、ボンディングの
際剥離が生じたとしても、各電極と第２電極層(3)は密
着しているので、断線なども生じない。Thus, the bonding of the lead wire (17) to each electrode is performed on the second electrode layer (3) located on the GaAs substrate (1), and the lead wire (17) is bonded to the second electrode layer (3). It is connected to the top and the electrodes are taken out. That is, since the bonding is performed on the second electrode layer (3) having a high adhesive strength, there is no possibility that the second electrode layer (3) will come off. Also, even if the second
Even if peeling occurs during bonding between the electrode layer (3) and the GaAs substrate (1), since the respective electrodes and the second electrode layer (3) are in close contact with each other, no disconnection occurs.

尚、本実施例では、ソース電極(13)およびドレイン電極
(14)をＡｕ−Ｇｅ層(21)、Ｎｉ層(23)、Ｔｉ層(22)Ａｕ
層(20)で構成しているが、Ａｕ−Ｇｅ層(21)などのオー
ミツク接触形成金属を単層で構成し、その上に第２電極
層(3)を配設して構成することもできる。また第１およ
び第２ゲート電極(15)(16)もＴｉ層などのショットキ接
触形成金属を単層で構成し、その上に第２電極層(3)を
配設して構成することもできる。In this example, the source electrode (13) and the drain electrode
(14) is Au-Ge layer (21), Ni layer (23), Ti layer (22) Au
Although it is composed of the layer (20), it is also possible that the ohmic contact forming metal such as the Au-Ge layer (21) is composed of a single layer, and the second electrode layer (3) is disposed on it. it can. The first and second gate electrodes (15) and (16) can also be configured by forming a single layer of Schottky contact forming metal such as a Ti layer and disposing the second electrode layer (3) on the Schottky contact forming metal. .

(ト)発明の効果 以上説明したように、本発明によれば、ボンディング作
業の際に、電極が剥離することもなくなり、信頼性の高
い半導体装置を提供することができる。(G) Effect of the Invention As described above, according to the present invention, it is possible to provide a highly reliable semiconductor device in which the electrodes do not peel off during the bonding work.

【図面の簡単な説明】[Brief description of drawings]

第１図ないし第３図は本発明の一実施例を示し、第１図
は本発明によるＧａＡｓ−ＭＥＳＦＥＴの上面図、第２
図は第１図のII−II線断面図、第３図は電極構造を示す
模式断面図である。第４図ないし第７図は従来例を示
し、第４図はＧａＡｓ−ＭＥＳＦＥＴの上面図、第５図
は第４図のV−V線断面図、第６図および第７図は電極構
造を示す模式断面図である。 (1)…ＧａＡｓ基体、(11)…基体、(12)…活性層、(13)
…ソース電極、(14)…ドレイン電極、(15)(16)…ゲート
電極、(3)…第２電極層。1 to 3 show an embodiment of the present invention. FIG. 1 is a top view of a GaAs-MESFET according to the present invention, and FIG.
1 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a schematic sectional view showing an electrode structure. 4 to 7 show a conventional example, FIG. 4 is a top view of a GaAs-MESFET, FIG. 5 is a sectional view taken along line VV of FIG. 4, and FIGS. 6 and 7 show electrode structures. It is a schematic cross section shown. (1) ... GaAs substrate, (11) ... substrate, (12) ... active layer, (13)
Source electrode, (14) ... Drain electrode, (15) (16) ... Gate electrode, (3) ... Second electrode layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】ガリウムヒ素半導体基体と、この半導体基
体の所定領域に接触させた電極とを具備する半導体装置
において、前記電極上に、チタンに金を積層した第２電
極層を配設すると共に、この第２電極層を半導体基体ま
で延在して半導体基体と接続させ、半導体基体上に位置
する第２電極層上にリード線をボンディングしたことを
特徴とする半導体装置。1. A semiconductor device comprising a gallium arsenide semiconductor substrate and an electrode in contact with a predetermined region of the semiconductor substrate, wherein a second electrode layer in which titanium and gold are laminated is provided on the electrode. A semiconductor device, wherein the second electrode layer extends to the semiconductor substrate to be connected to the semiconductor substrate, and a lead wire is bonded to the second electrode layer located on the semiconductor substrate.
JP59162552A 1984-08-01 1984-08-01 Semiconductor device Expired - Lifetime JPH065688B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59162552A JPH065688B2 (en) 1984-08-01 1984-08-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59162552A JPH065688B2 (en) 1984-08-01 1984-08-01 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6142147A JPS6142147A (en) 1986-02-28
JPH065688B2 true JPH065688B2 (en) 1994-01-19

Family

ID=15756758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59162552A Expired - Lifetime JPH065688B2 (en) 1984-08-01 1984-08-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH065688B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63106902U (en) * 1986-12-29 1988-07-11
DE3719354A1 (en) * 1987-06-10 1988-12-22 Heilmeier & Weinlein SCREW-IN VALVE HOUSING

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56142678A (en) * 1980-04-07 1981-11-07 Nec Corp Field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56142678A (en) * 1980-04-07 1981-11-07 Nec Corp Field effect transistor

Also Published As

Publication number Publication date
JPS6142147A (en) 1986-02-28

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