JPS61216166A - Address signal processor - Google Patents
Address signal processorInfo
- Publication number
- JPS61216166A JPS61216166A JP5682985A JP5682985A JPS61216166A JP S61216166 A JPS61216166 A JP S61216166A JP 5682985 A JP5682985 A JP 5682985A JP 5682985 A JP5682985 A JP 5682985A JP S61216166 A JPS61216166 A JP S61216166A
- Authority
- JP
- Japan
- Prior art keywords
- address signal
- signal
- peak level
- level
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Optical Recording Or Reproduction (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ビデオディスクやビデオファイル等において
、ディスクにあらかじめ記録されている番地信号の番地
信号処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an address signal processing device for address signals pre-recorded on a video disc, video file, or the like.
従来の技術
従来、ディスクから番地信号を読み出す際には、第２図
に示すように、ピックアップ手段２によってとり出され
た番地信号のサグや振幅の大きさによる直流変動をおさ
えるためにクランプ回路４で番地信号をクランプし、電
圧比較器９で基準レベル源１０の出力信号である直流電
圧と上記クランプされた番地信号を電圧比較して波形整
形を行ない、番地信号を読みとることがよく行なわれて
いた。2. Description of the Related Art Conventionally, when reading an address signal from a disk, as shown in FIG. It is common practice to clamp the address signal with a voltage comparator 9, compare the voltage of the clamped address signal with the DC voltage that is the output signal of the reference level source 10, perform waveform shaping, and read the address signal. Ta.
発明が解決しようとする問題−く、
しかしながら上記のような構成では、ディスクによる反
射率や溝深さのバラツキ等により番地信号の振幅に変動
があると、読み取り可能な基準しベル源に変動があり読
み取れないという問題点を有していた。Problem to be Solved by the Invention: However, with the above configuration, if there is a fluctuation in the amplitude of the address signal due to variations in the reflectance of the disk or the groove depth, the fluctuation in the readable reference signal will occur. The problem was that it was difficult to read.
本発明は」二部問題点に鑑みてなされたもので、番地信
号の読取の不可能な場合が生じない番地信号処理装置を
提供することを目的としている。The present invention has been made in view of the two problems, and it is an object of the present invention to provide an address signal processing device that does not cause cases where address signals cannot be read.
問題点を解決するための手段
上記問題点を解決するために本発明の番地信号処理装置
は、番地信号の底の部分を第１の基準レベルにクランプ
し１番地信号の」二部のピークレベルを検出し第２の基
準レベルとの誤差信号を制御信号として可変増幅器の増
幅度をかえ、可変増幅器を通すクランプされた番地信号
と、上記第１の基準レベルと第２の基準レベルの中間レ
ベルとを電圧比較し波形整形された番地信号を得るよう
構成したものである。Means for Solving the Problems In order to solve the above problems, the address signal processing device of the present invention clamps the bottom part of the address signal to a first reference level and adjusts the peak level of the second part of the first address signal. is detected and the amplification degree of the variable amplifier is changed using the error signal with the second reference level as a control signal, and the clamped address signal passed through the variable amplifier and the intermediate level between the first reference level and the second reference level are detected. This configuration is configured to compare the voltages of the two signals and obtain a waveform-shaped address signal.
作用
本発明は」二部した構成により、番地信号の直流変動が
なく振幅が一定に保たれるため、番地信号の読みとれる
基準電圧レベルに変動がなく、読みとれ々いことがなく
なることになる。Effects of the present invention Due to the two-part structure, there is no DC fluctuation in the address signal and the amplitude is kept constant, so there is no fluctuation in the reference voltage level at which the address signal can be read, and there is no possibility that the address signal will not be read.
実施例
第１図は本発明の番地信号処理装置の一実施例を示すブ
ロック図である。第１図において１はあらかじめ番地信
号の記録された記録媒体で、ピックアップ手段２により
上記番地信号がとシ出され増幅される。上記増幅された
番地信号は可変増幅器３に入力され差動増幅型子の出力
信号である番地信号の振幅大きさに応じた制御電圧によ
って増幅度が変化し振幅が一定な番地信号を出力する。Embodiment FIG. 1 is a block diagram showing an embodiment of the address signal processing device of the present invention. In FIG. 1, reference numeral 1 denotes a recording medium on which an address signal is recorded in advance, and a pickup means 2 picks up and amplifies the address signal. The amplified address signal is input to the variable amplifier 3, and the degree of amplification is changed by a control voltage according to the amplitude of the address signal, which is the output signal of the differential amplification type element, and an address signal having a constant amplitude is output.
この番地信号はクランプ回路４に入力され一定のレベル
（クランプレベル）にクランプされる。This address signal is input to the clamp circuit 4 and clamped to a constant level (clamp level).
上記クランプ回路４は例えば第１図の点線で囲まれてい
るようなものである。可変増幅器３の出力番地信号はフ
ィードバッククランプ回路４ｂの出力信号である番地信
号の直流変動やサグの大きさに応じた制御信号によって
クランプレベルにクランプされる。上記クランプされた
番地信号は増幅器４ａに入力さｒ番地信号のサグが検出
できるまで増幅される。フィードバッククランプ回路４
ｂには増幅器４ａの出力番地信号が入力されると共に、
クランプレベル源４Ｃの出力信号であるクランプレベル
電圧が入力され、番地信号の直流変動やサグの大きさに
応じた比較誤差制御電圧を出力し、可変増幅器３の出力
番地信号に加算されクランプレベルにクランプするよう
に制御ループを形成する。The clamp circuit 4 is, for example, the one surrounded by the dotted line in FIG. The output address signal of the variable amplifier 3 is clamped to a clamp level by a control signal corresponding to the magnitude of DC fluctuation or sag in the address signal, which is the output signal of the feedback clamp circuit 4b. The clamped address signal is input to the amplifier 4a and is amplified until a sag in the r address signal can be detected. Feedback clamp circuit 4
The output address signal of the amplifier 4a is input to b, and
The clamp level voltage, which is the output signal of the clamp level source 4C, is input, and a comparison error control voltage corresponding to the magnitude of the DC fluctuation and sag of the address signal is output, which is added to the output address signal of the variable amplifier 3 to obtain the clamp level. Form a control loop to clamp.
クランプ回路４の出力番地信号はピークレベル検出器５
に入力され、番地信号の上部のピークレベル電圧を出力
する。差動増幅器７の負端子には上記ピークレベル電圧
が入力されると共に正端子には基準ピークレベル源１ｏ
の出力信号であるピークレベル電圧が入力され、番地信
号の振幅の大きさに応じた比較誤差制御電圧を出力し、
可変増幅器３に入力され振幅が一定になるように制御ル
ープを形成する。The output address signal of the clamp circuit 4 is sent to the peak level detector 5.
and outputs the upper peak level voltage of the address signal. The above peak level voltage is input to the negative terminal of the differential amplifier 7, and the reference peak level source 1o is input to the positive terminal.
The peak level voltage which is the output signal of is input, and a comparison error control voltage is output according to the amplitude of the address signal
A control loop is formed so that the signal is input to the variable amplifier 3 and the amplitude is constant.
上記２つの制御ループによりサグのとれて振幅の一定な
、一定の電位にクランプされた番地信号が得られる。The two control loops described above provide an address signal clamped to a constant potential with no sag and constant amplitude.
上記クランプレベル電圧とピークレベル電圧は 。The above clamp level voltage and peak level voltage are.
同時に加算割算回路８に入力され、クランブレペロ′・
ノ
ルミ圧とピークレベル電圧の中間のレベル電圧を出力す
る。At the same time, it is input to the addition/division circuit 8, and the crumble pero'・
Outputs a level voltage between the norm voltage and the peak level voltage.
電圧比較器９の負端子には増幅器４ａの出力番地信号が
入力され、正端子には上記中間のレベル電圧が入力され
、波形整形された番地信号を出力する。The output address signal of the amplifier 4a is input to the negative terminal of the voltage comparator 9, and the above-mentioned intermediate level voltage is input to the positive terminal, and a waveform-shaped address signal is output.
以上のよう本実施例によれば、番地信号の振幅の大きさ
に応じて増幅度が変わる可変増幅器３と番地信号の直流
変動やサグの大きさに応じてクランプ量が変わるクラン
プ回路４を設けることにより、番地信号の読みとりの誤
動作を防ぐことができる。As described above, according to this embodiment, the variable amplifier 3 whose amplification degree changes depending on the magnitude of the amplitude of the address signal, and the clamp circuit 4 whose clamping amount changes according to the DC fluctuation of the address signal or the magnitude of sag are provided. This makes it possible to prevent malfunctions in reading address signals.
発明の効果
以上のように本発明は可変増幅器とクランプ回路を設け
ることにより、番地信号の変動に対する読みとりの誤動
作を防ぐことができる。Effects of the Invention As described above, by providing a variable amplifier and a clamp circuit, the present invention can prevent reading errors due to changes in address signals.
第１図は本発明の一実施例における番地信号処理装置の
ブロック図、第２図は従来の番地信号処理装置のブロッ
ク図である。
３ 可変増幅器、４・・・クランプ回路、５・・・・
ピークレベル検出器、６・・・・・・基準ピークレベル
源、７・・・差動増幅器、８・・−７Ｊｎ算・割算回路
、９・・・・電圧比較器。FIG. 1 is a block diagram of an address signal processing device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional address signal processing device. 3 variable amplifier, 4...clamp circuit, 5...
Peak level detector, 6...Reference peak level source, 7...Differential amplifier, 8...-7Jn calculation/division circuit, 9...Voltage comparator.
Claims (1)
表わす信号（番地信号）を光学的に読みとるピックアッ
プ手段と、上記ピックアップ手段によって読みとられた
番地信号を入力信号とし印加された制御信号に応じて増
幅度が変化する可変増幅器と、前記可変増幅器の出力番
地信号を入力信号とし第１の基準レベルにクランプする
クランプ回路と、クランプされた番地信号の振幅のピー
クレベルを検出するピークレベル検出器と、前記ピーク
レベル検出器の出力信号と第２の基準レベルとを比較し
その比較信号を制御信号として前記可変増幅器に出力す
る差動増幅器と、前記第１の基準レベルと第２の基準レ
ベルの中間のレベルを出力する加算・割算回路と、前記
クランプされた番地信号と前記中間レベルとを電圧比較
し波形整形整形された番地信号を出力する電圧比較器と
を備えたことを特徴とする番地信号処理装置。a pickup means for optically reading a signal (address signal) representing the position of a guide groove recorded in advance on a recording medium; and a pickup means that uses the address signal read by the pickup means as an input signal and responds to an applied control signal. a variable amplifier whose amplification degree changes by changing the amplification level; a clamp circuit that uses the output address signal of the variable amplifier as an input signal and clamps it to a first reference level; and a peak level detector that detects the peak level of the amplitude of the clamped address signal. and a differential amplifier that compares the output signal of the peak level detector with a second reference level and outputs the comparison signal as a control signal to the variable amplifier, and the first reference level and the second reference level. and a voltage comparator that compares voltages between the clamped address signal and the intermediate level and outputs a waveform-shaped address signal. address signal processing device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60056829A JPH0664843B2 (en) | 1985-03-20 | 1985-03-20 | Signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60056829A JPH0664843B2 (en) | 1985-03-20 | 1985-03-20 | Signal processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61216166A true JPS61216166A (en) | 1986-09-25 |
| JPH0664843B2 JPH0664843B2 (en) | 1994-08-22 |
Family
ID=13038263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60056829A Expired - Fee Related JPH0664843B2 (en) | 1985-03-20 | 1985-03-20 | Signal processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0664843B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01165037A (en) * | 1987-09-08 | 1989-06-29 | Hitachi Ltd | Signal reproducing system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58189810A (en) * | 1982-03-31 | 1983-11-05 | Akai Electric Co Ltd | Digital signal extracting circuit in pcm reproducer |
-
1985
- 1985-03-20 JP JP60056829A patent/JPH0664843B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58189810A (en) * | 1982-03-31 | 1983-11-05 | Akai Electric Co Ltd | Digital signal extracting circuit in pcm reproducer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01165037A (en) * | 1987-09-08 | 1989-06-29 | Hitachi Ltd | Signal reproducing system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0664843B2 (en) | 1994-08-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |