JPS61189667A - Emitter short-circuit structure of semiconductor device - Google Patents
Emitter short-circuit structure of semiconductor deviceInfo
- Publication number
- JPS61189667A JPS61189667A JP2985685A JP2985685A JPS61189667A JP S61189667 A JPS61189667 A JP S61189667A JP 2985685 A JP2985685 A JP 2985685A JP 2985685 A JP2985685 A JP 2985685A JP S61189667 A JPS61189667 A JP S61189667A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- short
- emitter
- turn
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 239000000969 carrier Substances 0.000 abstract description 7
- 230000002441 reversible effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体装置、特にＰまたはＮゲート３端子自己
消弧形サイリスタのエミッタ短絡構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device, particularly to an improvement in the emitter short-circuit structure of a P or N gate three-terminal self-extinguishing thyristor.
（０） 従来の技術
靜ｔｔＳ導サイリスタ（以下ＳＩサイリスタという）や
ゲートターンオフサイリスタなどに有するエミッタ短絡
構造としては、スイッチング時間の短絡および高温での
漏れ電流の低減を図るために、特にアノード電極側のＰ
形エミッタ層に、この膚とは逆のＮ形の層で、ウェハ基
板と同形の拡散を行ったものが一般的である。(0) Conventional technology The emitter short-circuit structure of S-conducting thyristors (hereinafter referred to as SI thyristors), gate turn-off thyristors, etc. is designed to shorten the switching time and reduce leakage current at high temperatures, especially on the anode electrode side. P of
Generally, the N-type emitter layer is an N-type layer opposite to the skin, and is diffused in the same shape as the wafer substrate.
そして、このアノード電極表面上でのＮ形の拡散層の占
める割合をＰ形エミッタ層短絡率（以下ＰＥ短絡率とい
う）と称し、ＰＩＩ短絡率が素子性能に及ぼす影響は次
のようなものである。The proportion of the N-type diffusion layer on the surface of the anode electrode is called the P-type emitter layer short-circuit rate (hereinafter referred to as PE short-circuit rate), and the influence that the PII short-circuit rate has on device performance is as follows. be.
すなわち長所としては、
（１） 素子をターンオフさせたときに生ずる基板内
の浮遊キャリアを素速く短絡孔から引き出させることが
できるので、ターンオフに要する時間は減少し、スイッ
チングの高速化となる。That is, the advantages are as follows: (1) Floating carriers in the substrate that are generated when the device is turned off can be quickly drawn out from the shorting hole, so the time required for turn-off is reduced and switching speed is increased.
（２）ターンオフの際、Ｐ形エミッタ層からの余計なキ
ャリア注入が減少し、また高温でオフ時の漏れ電流も少
なくなるので電力損失が減少する。(2) During turn-off, unnecessary carrier injection from the P-type emitter layer is reduced, and leakage current during off-time at high temperatures is also reduced, resulting in reduced power loss.
また短所としては、
Ｐ形エミッタ層からのキャリア注入が前述したごとく減
少するので、ターンオンの際、電流が流れにくい。また
、オン状態で順電圧降下が増して発熱し、電力損失が増
加する。Another drawback is that carrier injection from the P-type emitter layer is reduced as described above, so current is difficult to flow during turn-on. Further, in the on state, the forward voltage drop increases, heat is generated, and power loss increases.
以上のように、エミッタ短絡構造を有する素子には一長
一短があり、設計に際しては前述パラメーターのトレー
ドオフ関係を基準にして行われる。As described above, elements having an emitter short-circuit structure have advantages and disadvantages, and the design is performed based on the trade-off relationship among the parameters described above.
また、Ｐ形エミッタ層の幅はＮ形エミッタ層を有するエ
ピタキシャル成長せしめたＮ形層の狭い側の幅より広く
取られている。すなわち、サイリスタの場合、後述する
ＰＢ Ｎａ ＰＢ Ｎｇ構造となっており、ＮＢ層がＰ
ａ層に向って深いためＰａ層よりのキャリア注入が少な
いと点弧しなくなる。故に、一般的に知られているＶ短
絡孔での２３１層短絡は、ＰＢ層の囲って行われている
。従って、後述する本発明はこれらの点を踏えて発明さ
れたものである。Also, the width of the P-type emitter layer is greater than the width of the narrow side of the epitaxially grown N-type layer with the N-type emitter layer. That is, in the case of a thyristor, it has a PB Na PB Ng structure, which will be described later, and the NB layer is P
Since it is deep toward the a layer, if there is less carrier injection from the Pa layer, ignition will not occur. Therefore, the 231 layer short circuit using the generally known V short circuit hole is performed by surrounding the PB layer. Therefore, the present invention, which will be described later, was invented taking these points into consideration.
さて、従来のＰゲート３端子自己消弧形のＳＩサイリス
タのエミッタ短絡構造の一例を第３図〜第５図に基づい
て説明する。Now, an example of the emitter short-circuit structure of a conventional P-gate three-terminal self-extinguishing SI thyristor will be described with reference to FIGS. 3 to 5.
第３図（ａ） 、 （ｂ）は従来のものの一例を示し、
（ａ）図はその外観を示す平面図、（ｂ）図は（ａ）図
の部分図であり、第４図（ａ） 、 （ｂ）は第３図（
ａ）に示す矢視Ａ −Ａ′。Figures 3(a) and 3(b) show an example of the conventional one,
Figure (a) is a plan view showing the external appearance, Figure (b) is a partial view of Figure (a), and Figures 4 (a) and (b) are Figure 3 (
Arrow view A-A' shown in a).
Ｂ −Ｂ’のそれぞれを示す断面図、第５図ｔａｌ 、
（ｂ）は第３図（ａ）に示すものの作用を説明するた
めの説明図である。A sectional view showing each of B-B', Fig. 5 tal,
(b) is an explanatory diagram for explaining the effect of what is shown in FIG. 3(a).
第３図（ａ） 、 （ｂ）および第４図（ａ） 、 （
ｂ）において、１はＰ形エミッタ層（以下ＰＢ層という
）、２！；ｔＮ形の短絡層（以下？短絡層という）、３
はＮ形の高抵抗領域基板（以下Ｎ８層という）、４はＰ
形のゲート拡散層（以下２層という）、３ａは２層４に
囲まれたＮ８層３の部分を示すチャンネル部、５はエピ
タキシャル成長で形成せしめられたＮ形の層（以下Ｎ層
という）、６はＮ形のエミッタ層（以下Ｎ８層という）
、７はアルミニウム蒸着せしめられたカソード電極、８
はアルミニウム蒸着せしめられたゲート電極、９はアル
ミニウム合金のアノード電極、ｌＯはＰＢ層１．Ｎ＋短
絡層２などから形成された第３図（ａ）に示すペレット
である。Figure 3 (a), (b) and Figure 4 (a), (
In b), 1 is a P-type emitter layer (hereinafter referred to as PB layer), 2! ;tN type short circuit layer (hereinafter referred to as ? short circuit layer), 3
4 is an N-type high resistance region substrate (hereinafter referred to as N8 layer), and 4 is a P
a shaped gate diffusion layer (hereinafter referred to as 2 layers); 3a indicates a channel portion of the N8 layer 3 surrounded by 2 layers 4; 5 denotes an N type layer formed by epitaxial growth (hereinafter referred to as N layer); 6 is an N-type emitter layer (hereinafter referred to as N8 layer)
, 7 is a cathode electrode deposited with aluminum, 8
9 is an aluminum alloy anode electrode, IO is a PB layer 1. The pellet shown in FIG. 3(a) is formed from the N+ shorting layer 2 and the like.
すなわち第４図（ａ） 、 （ｂ）に示す８Ｉサイリス
タは、Ｎ８層３と８層５の境界部に（ａ）図に示すごと
く格子状に２層４が埋め込まれており、８層５の上部に
Ｎ８層６、更にその上面にカソード電極７が形成され、
Ｎ８層３の下部にはＰＢ層１およびＰＢ層１の側面周辺
部にｆ短絡層２が形成され、更にその下面にアノード電
極９．モリブデン支持電極（図示せず）が形成され、更
にまた、８層５の周辺部は取り除かれ、２層４の表面が
一部露出せしめられ、この露出部分にゲート電極８が形
成されて第３図（ａ）に示すペレットｌＯを得るものか
ら構成されている。In other words, in the 8I thyristor shown in FIGS. 4(a) and 4(b), two layers 4 are embedded in the boundary between the N8 layer 3 and the 8 layer 5 in a grid pattern as shown in FIG. An N8 layer 6 is formed on top of the N8 layer 6, and a cathode electrode 7 is formed on the top surface of the N8 layer 6.
Below the N8 layer 3, a PB layer 1 and an f-shorting layer 2 are formed around the side surfaces of the PB layer 1, and an anode electrode 9. A molybdenum supporting electrode (not shown) is formed, and furthermore, the peripheral part of the 8th layer 5 is removed to expose a part of the surface of the 2nd layer 4, a gate electrode 8 is formed on this exposed part, and a 3rd layer 5 is formed. It consists of what produces the pellets IO shown in Figure (a).
その作用を第５図（ａ） 、 （ｂ）について詳述する
。The effect will be explained in detail with reference to FIGS. 5(a) and 5(b).
第５図（ａ）はＳＩサイリスタがオン状態にあるとき、
（ｂ）図はターンオフしたときを示す。FIG. 5(a) shows when the SI thyristor is in the on state,
(b) The figure shows the state when turned off.
（ａ）図において、アノード電極９の端子Ａ側を正極、
カソード電極７の端子に側を負極とする順バイアスとし
て電圧を印加すると、主電流がアノード電極９からカソ
ード電極７へ流れるノーマリオン型素子の動作を示す。(a) In the figure, the terminal A side of the anode electrode 9 is the positive electrode,
When a voltage is applied to the terminal of the cathode electrode 7 as a forward bias with the negative electrode side, the main current flows from the anode electrode 9 to the cathode electrode 7, which shows the operation of a normally-on type element.
すなわち、キャリアとしての正孔りは、ＰＩ！１層１か
らＮ２層６に向って矢印■のごとく流れ、電子ｅＩｉＮ
Ｂ層６からＰＢ層１に向って矢印■のごとく、またＮ８
層３からＮ短絡層２に向って矢印■のごとく流れる。In other words, holes as carriers are PI! Flowing from the 1st layer 1 to the N2 layer 6 as shown by the arrow ■, electrons eIiN
From B layer 6 to PB layer 1, as shown by the arrow ■, again N8
It flows from the layer 3 toward the N-shorted layer 2 as shown by the arrow ■.
次にゲート電極８に負バイアスをかけると、ＳＩサイリ
スタは（ｂ）図に示すごとくターンオフとなる。Next, when a negative bias is applied to the gate electrode 8, the SI thyristor is turned off as shown in FIG.
すなわち、Ｎ８層３に有する正孔りはＰ＋層４に向って
矢印■のごとく流れ、電子ｅはＮ８層６からチャンネル
部３ａに向って矢印■のごとく、またＮ８層３からｒ短
絡層２に向って矢印■のごとく流れる。That is, the holes in the N8 layer 3 flow toward the P+ layer 4 as shown by the arrow (■), and the electrons e flow from the N8 layer 6 toward the channel portion 3a as shown by the arrow (■), and from the N8 layer 3 to the r-shorting layer 2. It flows like an arrow ■ toward .
（ハ）発明が解決しようとする問題点
かくして、上述したようなＳＩサイリスタの短絡構造で
は、ターンオフのときｐｇ層１の上部に有するキャリア
、すなわち電子ｅを引き抜くことが遅れがちとなり、Ｐ
ｇ層ｌの幅が広くなるとＮ短絡層２と２の間隔が長くな
って電子ｅはＮ＋短絡層２に到達しずらくなり、一層遅
れがちとなってターンオフ時間がかかる。(c) Problems to be Solved by the Invention Thus, in the short-circuit structure of the SI thyristor as described above, the extraction of carriers, that is, electrons e, present in the upper part of the pg layer 1 tends to be delayed during turn-off, and the
As the width of the g layer l increases, the distance between the N shorting layers 2 becomes longer, making it more difficult for the electrons e to reach the N+ shorting layer 2, and the electron e tends to be delayed further, resulting in a longer turn-off time.
よって、本発明の目的とするところは、上述したような
問題点を解決し、ターンオフ時間の短縮されたものを実
現することにある。Therefore, an object of the present invention is to solve the above-mentioned problems and realize a device with a shortened turn-off time.
に）問題点を解決するための手段
そこで、上記の目的を達成するための本発明の構成は、
エミッタ短絡層を有するＰ形のエミッタ層の内部に、エ
ミッタ短絡層と並列にエミッタ短線層より幅の狭いエミ
ッタ短絡補助層を形成したものである。以下その作用を
、Ｐゲート３端子自己消弧形のＳＩサイリスタを例にと
り第１図、第２図を参照して詳述する。Therefore, the structure of the present invention to achieve the above object is as follows:
An emitter shorting auxiliary layer having a width narrower than the emitter short line layer is formed in parallel with the emitter shorting layer inside a P-type emitter layer having an emitter shorting layer. The operation will be described below in detail with reference to FIGS. 1 and 2, taking a P-gate three-terminal self-extinguishing type SI thyristor as an example.
（ホ）実施例
第１図（ａ） 、 （ｂ）は本発明にかかるＳＩサイリ
スタの一実施例を示し、（ａ） 、 （ｂ）図は第４図
（ａ） 、 （ｂ）に類した断面図、第２図（ａ） 、
（ｂ）は第５図（ａ） 、 （ｂ）に類した説明図で
あり、図中、第４図と第５図の符合と同じものは同一構
成部分を示す。(e) Embodiment FIGS. 1(a) and (b) show an embodiment of the SI thyristor according to the present invention, and FIGS. 1(a) and 1(b) are similar to FIGS. 4(a) and (b). Cross-sectional view, Fig. 2(a),
5(b) is an explanatory diagram similar to FIGS. 5(a) and 5(b), in which the same reference numerals as in FIG. 4 and FIG. 5 indicate the same components.
第１図（ａ） 、 （ｂ）において、１１はＮ＋短絡層
２を有するＰＫ層１′の内部に、Ｎ＋短絡層２と並列に
ｔ短絡層２の幅Ｗより狭い幅外のエミ、り短絡補助層（
以下Ｎ短絡補助層という）であり、これは所定の間隔で
もって３ケ所に形成されている。In FIGS. 1(a) and 1(b), reference numeral 11 indicates an emitter layer 11 inside the PK layer 1' having the N+ shorting layer 2, in parallel with the N+ shorting layer 2, and having an outer width narrower than the width W of the t-shorting layer 2. Short circuit auxiliary layer (
(hereinafter referred to as N shorting auxiliary layer), which is formed at three locations at predetermined intervals.
すなわち、ＳＩサイリスタは、定格が順阻止電圧５００
Ｖ 、平均オン電流がＩＯＡ 、大きさが１０ｍ口。In other words, the SI thyristor has a forward blocking voltage rating of 500
V, average on-current is IOA, and size is 10m.
第３図（ａ）に示す１０ケ所の長方形の単体の大きさが
ｐｇ層１′の幅〈が４００μｍ、Ｙ短絡補助層１１の幅
外が２０μｍ、ＰＢ短絡率が３２チのものが使、用され
、−各部の構成はＶ短絡補助層１１および２１１層１′
を除いて従来のものと同じである。The size of the 10 rectangular units shown in FIG. 3(a) is such that the width of the pg layer 1' is 400 μm, the outside width of the Y shorting auxiliary layer 11 is 20 μm, and the PB shorting rate is 32 inches. - The structure of each part is V shorting auxiliary layer 11 and 211 layer 1'
It is the same as the conventional one except for.
Ｎ＋短絡補助層１１を拡散してＰＭ層１′に形成する際
の最低必要なＮ＋短絡補助層１１の幅細は、Ｎ＋短絡補
助層１１の深さをｄとした場合の１．６ｄと、アノード
電極９側に形成されるｒ短絡補助層１１のパターンの最
低幅を加えた寸法となる。なお、パターン最低幅はアノ
ード電極９側の基板表面形状およびパ頌
ターン形成種変に左右されるところがあるが、ここでは
深さｄを１０μｍ、パターンの最低幅を４μｍで形成さ
れ、Ｎ短絡補助層１１の輻幅は２０μｍとなり第３図（
ａ）に示す長方形の短形側が３００μｍであることから
（１／１５）倍となる。また、ＰＲ層１′の全体の幅は
、従来の技術の項で説明したごと＜、Ｎ層５より広く取
られている。The minimum required width of the N+ shorting auxiliary layer 11 when forming the N+ shorting auxiliary layer 11 by diffusion into the PM layer 1' is 1.6 d, where d is the depth of the N+ shorting auxiliary layer 11. The dimension is the sum of the minimum width of the pattern of the r-shorting auxiliary layer 11 formed on the anode electrode 9 side. Note that the minimum width of the pattern depends on the surface shape of the substrate on the anode electrode 9 side and the type of pattern formation, but here, the depth d is 10 μm, the minimum width of the pattern is 4 μm, and the N short circuit auxiliary The convergence width of layer 11 is 20 μm, as shown in Figure 3 (
Since the short side of the rectangle shown in a) is 300 μm, it is (1/15) times as large. Further, the overall width of the PR layer 1' is wider than the N layer 5, as explained in the section of the prior art.
次に、これらのものからなるＳＩサイリスタの作用を第
２図（ａ） 、 （ｂ）に基づいて詳述する。Next, the operation of the SI thyristor made of these components will be explained in detail based on FIGS. 2(a) and 2(b).
第２図（ａ）は素子がオン状態にある場合を示し、主電
流はｈ層１′からＮ１層６に向って流れている。FIG. 2(a) shows a case where the device is in the on state, and the main current flows from the h layer 1' to the N1 layer 6.
このとき、従来のものと相異するところは、電子ｅがＮ
８層３かｂＮ短絡補助層１１へ矢印■のごとく流れ込ん
でいる。一方、Ｎ短絡補助層１１を増すとＰＲ短絡率が
増加してオン篭圧降下が増す傾向となるが、従来のもの
のＰＩ短絡率３０％が３２俤となってもオン゛電圧降下
としての影響は出ない。At this time, the difference from the conventional method is that the electron e is N
The 8th layer 3 flows into the bN shorting auxiliary layer 11 as shown by the arrow (■). On the other hand, increasing the N shorting auxiliary layer 11 tends to increase the PR short circuit rate and increase the on-line voltage drop, but even if the conventional PI short-circuit rate of 30% becomes 32 lines, there is no effect on the on-line voltage drop. It doesn't appear.
以上のごとく、オン状態においては従来のものとの相異
は殆んどないが、ターンオフ時には下記のごとく相異が
みられる。その様子を（ｂ）図で説明する。As described above, there is almost no difference from the conventional one in the on state, but the following differences are observed in the turn off state. The situation will be explained using figure (b).
すなわち（ｂ）図において、端子Ｇ、に間に逆バイアス
が印加されると、２層４より正孔りがゲート電極８に引
き出され、チャンネル部３ａに空乏層が発生し、チャン
ネル部３ａ付近を通り抜けるキャリアが殆んどなくなっ
て８Ｉサイリスタはオフ状態に向かう。That is, in the figure (b), when a reverse bias is applied between the terminals G, holes are extracted from the second layer 4 to the gate electrode 8, a depletion layer is generated in the channel part 3a, and a depletion layer is generated in the vicinity of the channel part 3a. Almost no carrier passes through the 8I thyristor, and the 8I thyristor turns off.
一方、Ｎ８層３に浮遊しだすキャリア、特ｉこ電子Ｃは
、矢印■および■に示すごとく、？短絡層２およびイ短
絡補助層１１よりはきだされる。このことによって、テ
ィル時間などターンオフの良否を決定する電子ｅのはき
だしは、従来のＮ＋短絡層２ ゛のほかに本発明のｒ
短絡補助層１１を設けたことによってターンオフ時間の
短縮を可能ならしめる。On the other hand, the carriers, especially the electrons C, floating in the N8 layer 3 are as shown by the arrows ■ and ■. It is discharged from the shorting layer 2 and the shorting auxiliary layer 11. As a result, in addition to the conventional N+ shorting layer 2, the release of electrons e, which determines the quality of turn-off such as the till time, is made possible by using the present invention's r
By providing the short-circuit auxiliary layer 11, the turn-off time can be shortened.
すなわち、ＰＲ層１の３ケ所にＮ＋短絡補助層１１を設
けたことによって、電子流の移動距離が短かくなり、速
く電子ｅがはきだされるようになった。That is, by providing the N+ short-circuit auxiliary layer 11 at three locations on the PR layer 1, the distance traveled by the electron flow was shortened, and the electrons e were ejected quickly.
なお、本実施例においてはＮ”／ｉを用いて説明を行っ
たが、Ｎ層を用いても同様の効果を得ることは周知のこ
とである。また、実施例としては半導体基板としてＮ形
高抵抗のものを使用したＰゲート３端子自己消弧形サイ
リスタのエミッタ短絡構造についてのみ説明したが、Ｎ
ゲート３端子自己消弧形サイリスタについても同様の効
果があるこというまでもない。Although this embodiment has been explained using N''/i, it is well known that the same effect can be obtained by using an N layer.Also, in this embodiment, an N-type semiconductor substrate is used. We have only explained the emitter short-circuit structure of a P-gate 3-terminal self-extinguishing type thyristor using a high-resistance one, but N
Needless to say, a similar effect can be obtained with a gate three-terminal self-extinguishing thyristor.
（へ）発明の効果
以上述べてきたように、本発明によれば、従来ターンオ
フ時間に１．３μＳかかっていたものが、０．９μｓに
短縮され、本発明のＮ＋短絡補助層１１をＰＲ層１内に
設けても、順電圧降下、″ｔＪＬ圧増幅率などの特性に
おいて従来のものと殆んど変わらずまた他の特性に悪影
響を及ぼさないことが確認された。(F) Effects of the Invention As described above, according to the present invention, the turn-off time that conventionally took 1.3 μS is shortened to 0.9 μs, and the N+ shorting auxiliary layer 11 of the present invention is connected to the PR layer. It has been confirmed that even if it is provided within 1, the characteristics such as forward voltage drop and tJL pressure amplification factor are almost the same as those of the conventional type, and other characteristics are not adversely affected.
よって、本発明にかかる半導体装置のエミッタ短絡構造
は、実用的に極めて有用なものである。Therefore, the emitter short circuit structure of the semiconductor device according to the present invention is extremely useful in practice.
第１図（ａ） 、 （ｂ）は本発明にかかるものの一実
施例を示し、 （ａ） 、 （ｂ）図は第４図（ａ）
、 （ｂ）に類した断面図、第２図（ａ） 、 （ｂ）
は第５図（ａ） 、 （ｂ）に類した説明図、第３図（
ａ） 、 （ｂ）は従来のものの一例を示し、（ａ）図
はその外観を示す平面図、（ｂ）図は（ａ）図の部分図
、第４図（ａ） 、 （ｂ）は第３図（ａｌに示す矢視
Ａ−Ａ’、Ｂ−Ｂ’のそれぞれを示す断面図、第５図（
ａ） 、 （ｂ）は第３図（ａ）に示すものの作用を説
明するための説明図である。
１・・・・・ＰＲ層、２・・・・・Ｎ＋短絡層、１１・
・・・・Ｎ＋短絡補助層。FIGS. 1(a) and (b) show an embodiment of the present invention, and FIGS. 1(a) and (b) show FIG. 4(a).
, sectional view similar to (b), Figure 2 (a), (b)
is an explanatory diagram similar to Figures 5(a) and (b), and Figure 3(
Figures a) and (b) show an example of a conventional one, (a) is a plan view showing its appearance, (b) is a partial view of (a), and Figures 4 (a) and (b) are Figure 3 (a sectional view taken along arrows A-A' and B-B' shown in al), Figure 5 (
3a) and 3(b) are explanatory diagrams for explaining the operation of what is shown in FIG. 3(a). 1...PR layer, 2...N+ shorting layer, 11...
...N+ short circuit auxiliary layer.
Claims (1)
ッタ短絡構造において、エミッタ短絡層を有するＰ形の
エミッタ層の内部に、エミッタ短絡層と並列に前記エミ
ッタ短絡層より幅の狭いエミッタ短絡補助層を設けるこ
とを特徴とする半導体装置のエミッタ短絡構造。In the emitter short-circuit structure of a P- or N-gate three-terminal self-extinguishing thyristor, an emitter short-circuit auxiliary layer having a width narrower than the emitter short-circuit layer is provided inside the P-type emitter layer having an emitter short-circuit layer in parallel with the emitter short-circuit layer. An emitter short-circuit structure for a semiconductor device, characterized in that it is provided with an emitter short-circuit structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2985685A JPS61189667A (en) | 1985-02-18 | 1985-02-18 | Emitter short-circuit structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2985685A JPS61189667A (en) | 1985-02-18 | 1985-02-18 | Emitter short-circuit structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61189667A true JPS61189667A (en) | 1986-08-23 |
Family
ID=12287606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2985685A Pending JPS61189667A (en) | 1985-02-18 | 1985-02-18 | Emitter short-circuit structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61189667A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63257274A (en) * | 1987-04-14 | 1988-10-25 | Toyota Central Res & Dev Lab Inc | Electrostatic induction semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5527641A (en) * | 1978-08-18 | 1980-02-27 | Meidensha Electric Mfg Co Ltd | Semiconductor control element |
| JPS56112753A (en) * | 1980-02-13 | 1981-09-05 | Hitachi Ltd | Gate turn-off thyristor |
| JPS5940303A (en) * | 1982-08-31 | 1984-03-06 | Sony Corp | Magnetic head device for magnetization of magnetic material |
| JPS59189672A (en) * | 1983-04-13 | 1984-10-27 | Hitachi Ltd | Gate turn off thyristor |
-
1985
- 1985-02-18 JP JP2985685A patent/JPS61189667A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5527641A (en) * | 1978-08-18 | 1980-02-27 | Meidensha Electric Mfg Co Ltd | Semiconductor control element |
| JPS56112753A (en) * | 1980-02-13 | 1981-09-05 | Hitachi Ltd | Gate turn-off thyristor |
| JPS5940303A (en) * | 1982-08-31 | 1984-03-06 | Sony Corp | Magnetic head device for magnetization of magnetic material |
| JPS59189672A (en) * | 1983-04-13 | 1984-10-27 | Hitachi Ltd | Gate turn off thyristor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63257274A (en) * | 1987-04-14 | 1988-10-25 | Toyota Central Res & Dev Lab Inc | Electrostatic induction semiconductor device |
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