JPS6013311B2 - Semiconductor controlled rectifier - Google Patents
Semiconductor controlled rectifierInfo
- Publication number
- JPS6013311B2 JPS6013311B2 JP12752779A JP12752779A JPS6013311B2 JP S6013311 B2 JPS6013311 B2 JP S6013311B2 JP 12752779 A JP12752779 A JP 12752779A JP 12752779 A JP12752779 A JP 12752779A JP S6013311 B2 JPS6013311 B2 JP S6013311B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- base layer
- layer
- type base
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明は半導体制御整流装置、特にサイリス夕に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor controlled rectifiers, and more particularly to thyristors.
従釆、一般に周知のサィリスタの構造を第１図に示して
説明すると、同図において、１は比較的濃度の低いｎ−
導燈形のベース層、２は前記ベース層１の一方の面に設
けられたｐ＋導電形のアノード層、３は前記ベース層の
他方の面に設けられたｐ導電形のベース層、４はこのｐ
導電形ベース層３上に選択的に設けられたｎ十導電形の
カソード層である。The structure of a generally known thyristor will be explained with reference to FIG. 1. In the figure, 1 is a relatively low concentration n
2 is a p+ conductivity type anode layer provided on one surface of the base layer 1; 3 is a p conductivity type base layer provided on the other surface of the base layer; 4 is a conductive light-type base layer; This p
This is a cathode layer of n+ conductivity type selectively provided on the conductivity type base layer 3.
そして、５はアノード層２にオーム性接触をなすアノー
ド電極、６はカソード層４にオーム性接触をなすカソー
ド電極、７はｐ導電形のベース層３にオーム性接触をな
すゲート電極である。このような構造を有するサィリス
タの動作の概要を説明する。Reference numeral 5 designates an anode electrode that makes ohmic contact with the anode layer 2, 6 a cathode electrode that makes ohmic contact with the cathode layer 4, and 7 a gate electrode that makes ohmic contact with the base layer 3 of the p conductivity type. An overview of the operation of a thyristor having such a structure will be explained.
主電流を通電するときにはカソード電極６に負バイアス
、アノード電極５に正バイアスを印加する。このときア
ノード層２とｎ導電形ベース層１の接合Ｊ，およびカソ
ード層４とｐ導電形ベース層３の間の接合Ｊ３は順方向
にバイアスされるが、ｎ導電形ベース層１とｐ導電形ベ
ース層３の間の接合Ｊ２は逆方向バイアスになる。ゲー
ト電極７から正孔が注入され、カソード電極６からカソ
ード層４を経て電子がｐ導電形ベース層３に注入される
。注入された電子は接合Ｊ２を通ってｎ導軍形ベース層
１に集められる。このときアノード層２からｎ導電形ベ
ース層１に正孔が注入され、ベース層１を通ってｐ導電
形ベース層３に集められる。この正孔によって再びカソ
ード層４から接合Ｊ３を通って電子がｐ導電形ベース層
３に注入される。この過程を繰り返すことにより接合Ｊ
２の両側ベース層に正孔および電子が蓄積されることに
よって接合Ｊ２が逆バイアスから順バイアスに転換して
導適状態となる。この導適状態に移る過程をターンオン
と称し、その速さはゲート電極Ｔから注入された正孔が
カソード層４に入る速度、カソード層４からｐ導電形ベ
ース層３に注入された電子がｎ導電形ベース層１に伝達
する速さ、アノード層２からｎ導電形ベース層１に注入
された正孔がｐ導電形ベース層３に到達する速さなどに
よってさまる。また、逆バイアス電圧をカソード電極６
とアノード電極５の間に印加して鰭流を遮断した際に導
適状態から阻止状態に移る過程をターンオフと称し「
これは接合Ｊ２近傍に残留している正孔、電子が消失し
完全に順阻止状態を回復する速さでさまる。しかしなが
ら、上記した構造の従来のサィリス夕では、大電力の制
御能力はすぐれているが、その制御速度が小さく、高速
でかつ高耐圧のスイッチング装置が得うれなかった。When the main current is applied, a negative bias is applied to the cathode electrode 6 and a positive bias is applied to the anode electrode 5. At this time, the junction J between the anode layer 2 and the n-conductivity type base layer 1 and the junction J3 between the cathode layer 4 and the p-conductivity type base layer 3 are biased in the forward direction; The junction J2 between the shaped base layers 3 is reverse biased. Holes are injected from the gate electrode 7 , and electrons are injected from the cathode electrode 6 through the cathode layer 4 into the p-conductivity type base layer 3 . The injected electrons are collected in the n-type base layer 1 through the junction J2. At this time, holes are injected from the anode layer 2 into the n-conductivity type base layer 1, pass through the base layer 1, and are collected in the p-conductivity type base layer 3. These holes cause electrons to be injected from the cathode layer 4 into the p-conductivity type base layer 3 through the junction J3 again. By repeating this process, the joint J
By accumulating holes and electrons in the base layers on both sides of J2, the junction J2 changes from reverse bias to forward bias and becomes conductive. The process of transitioning to this conductive state is called turn-on, and its speed is determined by the speed at which holes injected from the gate electrode T enter the cathode layer 4, and the speed at which electrons injected from the cathode layer 4 into the p-conductivity type base layer 3 It depends on the speed of transmission to the conductivity type base layer 1, the speed at which holes injected from the anode layer 2 to the n conductivity type base layer 1 reach the p conductivity type base layer 3, etc. In addition, the reverse bias voltage is applied to the cathode electrode 6.
The process of changing from the conductive state to the blocking state when the fin flow is interrupted by applying between the anode electrode 5 and the anode electrode 5 is called turn-off.
This is limited to the speed at which the holes and electrons remaining in the vicinity of the junction J2 disappear and the forward blocking state is completely restored. However, although the conventional sirolith switch having the above-described structure has an excellent ability to control large electric power, its control speed is low, and a switching device with high speed and high withstand voltage cannot be obtained.
本発明はこのような点に鑑みでなされたもので「その目
的は制御速度を大きくするとともに高速動作に対するｄ
ｉ／ｄｔおよびｄｖ／ｄｔの耐量を大きくすることによ
り、高速でかつ高耐圧化を可能にした半導体制御整流装
置を提供することにある。The present invention was made in view of these points, and its purpose is to increase the control speed and increase the d for high-speed operation.
The object of the present invention is to provide a semiconductor-controlled rectifier that can operate at high speed and withstand high voltage by increasing the i/dt and dv/dt withstand capacities.
この目的を達成するために、本発明は、ｎ導蚤形のベー
ス層と、このベース層の両面に設けられたｐ導電形のア
ノード層およびベース層と〜 このｐ導電形のベース層
上に設けられたｎ導電形のカソード層とからなる半導体
制御整流装置において、前記ｎ導電形のベース層に前記
ｐ導蟹形べ−ス層と隣接して所定のパターンで形成され
た該ｐ導電形ベース層より高い不純物濃度を有するｐ導
電形のゲート領域を設け、かつ前記ｎ導電形ベース層と
前記アノード層との間に該ベース層より高い不純物濃度
を有する高濃度ベース領域を設け「前記ゲート領域の相
互間隔を２ａト前記ｐ導電形ベース層の厚みおよび不純
物濃度をそれぞれＷ８およびＮａ、前記ｎ導電形ベース
層の不純物濃度をＮｄとしたとき、Ｎｄ・ａ２＜Ｎａ・
ＷＢ２ になるようにしたことを特徴としている。以下
、図面を用いて本発明の実施例を説明する。第２図は本
発明の一実施例を示すサィリスタの要部断面図であり、
第１図と同一又は相当部分は同一番号を用いてある。To achieve this object, the present invention comprises an n-conductivity type base layer, a p-conductivity type anode layer and a base layer provided on both sides of this base layer, and ~ on this p-conductivity type base layer. In a semiconductor controlled rectifier comprising an n-conductivity type cathode layer provided, the p-conductivity type base layer is formed in a predetermined pattern adjacent to the p-conductivity crab-shaped base layer. A p conductivity type gate region having a higher impurity concentration than the base layer is provided, and a high concentration base region having a higher impurity concentration than the base layer is provided between the n conductivity type base layer and the anode layer. When the mutual spacing between the regions is 2a, the thickness and impurity concentration of the p-conductivity type base layer are W8 and Na, and the impurity concentration of the n-conductivity type base layer is Nd, Nd・a2<Na・
It is characterized by being made to be WB2. Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a sectional view of a main part of a thyristor showing an embodiment of the present invention,
The same numbers are used for the same or corresponding parts as in FIG. 1.
ここで第１図のサィリスタ構造と異なる点は、ｎ導電形
ベース層１上にｐ導電形ベース層３ａと隣接して縦横に
細かいパターンで櫛の歯状またはメッシュ状に形成され
たｐ十導電形のゲート領域８を設け、かつｎ導電形ベー
ス層竃とｐ＋導電形アノード層２との間にこのベース層
翼よりも高濃度の不純物を含むｎ十導電形のベース層領
域９を設けたことである。この場合、ｐ導電形ベース層
３ａは第１図におけるｐ導電形べ−ス層３よりも十分薄
く形成されており、その厚みは耐圧を同一に保つときは
従来構造のＩＪＩの壁度に形成できる。そして「 ｐ導
電形ベース層３８の厚みＷＢは、ゲート領域８の相互間
隔２ａとｐ導電形ベース層３ａの不純物濃度Ｎａしｎ導
電形ベース層富の不純物濃度Ｎｄとの間において「Ｎｄ
。Here, the difference from the thyristor structure in FIG. 1 is that a p-conductor is formed on the n-conductor base layer 1 adjacent to the p-conductor base layer 3a in a comb-like or mesh shape in a fine pattern vertically and horizontally. A gate region 8 of the shape of a conductivity type is provided, and an n+ conductivity type base layer region 9 containing impurities at a higher concentration than the base layer wing is provided between the n conductivity type base layer layer and the p+ conductivity type anode layer 2. That's true. In this case, the p-conductivity type base layer 3a is formed sufficiently thinner than the p-conductivity type base layer 3 in FIG. can. The thickness WB of the p-conductivity type base layer 38 is defined as "Nd" between the mutual spacing 2a of the gate regions 8 and the impurity concentration Na of the p-conductivity type base layer 3a and the impurity concentration Nd of the n-conductivity type base layer 3a.
.
ａ２＜Ｎａ。Ｗ８２の関係を満足するように決められる
。a2<Na. It is determined to satisfy the relationship W82.
なお〜 ｐ導電形ベース層３ａの厚みはゲート領域８の
相互間隔、ｐ導電形ベース層３ａの低抗率および装置の
印加電圧などにより異なってくるが「従来構造の１〜１
′５の塁度まで形成できる。上記実施例の構造のサイリ
スタによると、ターンオン時にゲート電極？から注入さ
れた正孔は、Ｄ導電形べ−ス層３ａを経てカソード層亀
内に注入されようとするがｔゲ−ト領域８が高不純物濃
度で構成されかつ縦横に細かいパターンで櫛の歯状また
はメッシュ状に形成されているので、ゲ−ト領域８は低
抵抗となり、このゲート領域８を通じて素子全面にすば
やく伝達する。The thickness of the p-conductivity type base layer 3a varies depending on the mutual spacing of the gate regions 8, the low resistivity of the p-conductivity type base layer 3a, the applied voltage of the device, etc.
It can be formed up to a base depth of '5. According to the thyristor having the structure of the above embodiment, when it is turned on, the gate electrode? Holes injected from the T-gate region 8 try to be injected into the cathode layer through the D conductivity type base layer 3a. Since the gate region 8 is formed in a tooth-like or mesh-like shape, the resistance is low, and the resistance is quickly transmitted through the gate region 8 to the entire surface of the device.
このためカソード層４からの電子の注入が速く起こり「
かつ注入された電子は従来構造より薄いｐ導電形ベース
層３ａ中を遠く通過してｎ導電形ベース層１に到達する
ことになる。この結果トアノード層２からの正孔の注入
を遠くさせ、ターンオンに要する時間を従来の１′２〜
１′１０まで低下させることができる。すなわち、第１
図に示すサィリスタ構造において「 サイリスタのター
ンオン時間はｐ導電形ベース層３の厚みＷＢ，およびｎ
導電形ベース層１の厚みＷＢ２ に依存し、このｎおよ
びｐ導電形べ−ス層内の少数キャリア走行時間をとする
と、夕−ンオン時間（ｔｏｎ）は近似的にｔｏｎニゾし
・ｔ２となる。Therefore, electron injection from the cathode layer 4 occurs quickly.
In addition, the injected electrons reach the n-conductivity type base layer 1 after passing far through the p-conductivity type base layer 3a, which is thinner than the conventional structure. As a result, the injection of holes from the toanode layer 2 is made farther away, and the turn-on time is increased from 1'2 to
It can be reduced to 1'10. That is, the first
In the thyristor structure shown in the figure, the turn-on time of the thyristor is determined by the thickness WB of the p-conductivity type base layer 3 and the n
Depending on the thickness WB2 of the conductivity type base layer 1, and assuming the minority carrier transit time in the n and p conductivity type base layers, the evening on time (ton) is approximately equal to tonnizo-t2. Become.
ただし「Ｄｎ、Ｄｐは前記各ベース層内での少数キャリ
アの拡散定数である。したがって、前記ベース層が厚く
なるとターンオン時間は長くなり、また、ｐ導電形ベー
ス層３の厚みがＷＢ，が小さくなると、サイリスタの順
阻止電圧はそのベース層のパンチスルー‐電圧ＶｐＴに
よって制御される問題が起こる。これに対して、本発明
は、ｐ導電形ベース層３ａ内に空乏層の延びを抑制する
ことによりその厚みＷ８，を４・さくし、かつｎ＋導電
形のベース層領域９によりｎ導電形ベース領域１の厚み
ＷＢ２を４・さくしようとするものであり、第２図の実
施例構造では、ｐ導電形ベース層３ａ内の空乏層の延び
が第１図の構造のものに比べて近似的に１ノムになる。
ただし岬ｘｐ（号）であり、ここ側まゲ−ト領域８の間
隔、Ｌはその深さである。However, Dn and Dp are minority carrier diffusion constants in each of the base layers. Therefore, the thicker the base layer, the longer the turn-on time, and the smaller the thickness of the p-conductivity type base layer 3, WB, is. Then, a problem arises in that the forward blocking voltage of the thyristor is controlled by the punch-through voltage VpT of its base layer.In contrast, the present invention has a method of suppressing the extension of the depletion layer in the p-conductivity type base layer 3a. Therefore, the thickness W8, of the base layer region 9 of the n+ conductivity type is reduced by 4.0 cm, and the thickness WB2 of the n conductivity type base region 1 is reduced by 4.0 cm. The extension of the depletion layer in the conductive base layer 3a is approximately 1 nom compared to the structure shown in FIG.
However, it is the cape xp (number), the distance between the gate areas 8 on this side, and L is the depth thereof.
それ故、ｐ導電形ベース層３ａの厚み（＝ＷＢ，を１／
叫こすることができ、したがって、ターンオン時間は１
ノ叫こすることができる。たとえば裏：。‐７の時には
ターンオン時間は約１／甥茎度に短くなる。また、ｐ導
鶴形ベース層３ａの厚みＷＢ，が一定であると考えると
、第２図の構造では第１図のものに比べて山倍の電圧を
印加することできるので「順阻止電圧を仏倍にできる。
一方、電流の遮断時にカソード電極６とアノード電極５
間には逆バイアス電圧が印加されるが、このとき接合Ｊ
，およびＪ３には逆バイアスが印加されるのに対し、接
合Ｊ２は反転したままで順バイアスが印加されるので、
従来の構造では、前記接合Ｊ２近傍の過剰キャリャは再
結合による自然消滅をまたねばならず、ターンオフに要
する時間が長くかかっていた。Therefore, the thickness of the p-conductivity type base layer 3a (=WB, is 1/
can be screamed and therefore the turn-on time is 1
You can scream. For example, the back:. At -7, the turn-on time is reduced to about 1/degree. Furthermore, assuming that the thickness WB of the p-conductor crane-shaped base layer 3a is constant, the structure shown in Fig. 2 can apply a voltage twice as high as that of Fig. 1. It can be doubled.
On the other hand, when the current is cut off, the cathode electrode 6 and the anode electrode 5
A reverse bias voltage is applied between the junction J
, and J3 are reverse biased, whereas junction J2 remains inverted and forward biased, so
In the conventional structure, the excess carriers near the junction J2 had to disappear naturally by recombination, and it took a long time for turn-off.
本発明では、ｎ導電形ベース層１とアノード層２との間
に設けられたｎ十導電形ベース層９によりァノード層２
から前記ベース層２への正孔の注入を制御しており「で
きる限り正孔の注入量を少なくして夕−ンオンする構造
をｎ＋導電形ベース層９の厚みおよび不純物濃度を適当
に選ぶことによって可能とすることができる。このため
、ターンオフ時に消滅するキャリャが少なくてすむこと
になり「 ターンオフ速度を早くすることができる。次
にｄｉノｄｔおよびｄｖ／ｄｔの耐量を第３図および第
４図を参照して説明する。In the present invention, the anode layer 2 is formed by the n+ conductivity type base layer 9 provided between the n conductivity type base layer 1 and the anode layer 2.
The injection of holes into the base layer 2 is controlled by "appropriately selecting the thickness and impurity concentration of the n+ conductivity type base layer 9 so as to reduce the amount of holes injected as much as possible and turn on the structure in the evening." Therefore, fewer carriers disappear during turn-off, and the turn-off speed can be increased. This will be explained with reference to FIG.
ここで、第３図は第１図に示す従来のサィリスタに、第
４図は第２図に示す本発明のサィリス外こそれぞれ対応
する。従来のサィリスタ構造において、サィリスタがオ
フ状態からオン状態に移る場合には第３図に示すＡ部分
すなわちカソード（ェミッタともいう）層４の周辺部で
ゲ−電極７に近いところに電流が集中して流れ、時間の
経過とともに、電流の流れ面積がカソード層全面に速度
ｖｓで広がる。一方、本発明の構造では第４図に示すＢ
部分すなわちｐ＋導霧形ゲート領域８の周辺部に電流が
集中し、その面積が速度ｖｓで広がる。そのため、本発
明では実効的なェミッタ周辺長が長くなり「ｄｖ／ｄｔ
耐量が改善される。また、上記ｖｓはｎ導電形ベース層
１の厚みＷＢ２に逆比例するので、本発明ではこのｖｓ
が大きくなり、これもｄｉ／ｄｔ耐量の改善に寄与する
ことになる。また、ｎ導電形カソード（ェミツタ）層４
、ｐ導電形ベース層３およびｎ導電形ベース層１からな
るｎ−ｐ−ｎトランジスタの電流増幅率Ｑはサィリスタ
を流れる電流の密度に依存し、一般に電流密度の増加と
ともにＱが大きくなる。Here, FIG. 3 corresponds to the conventional thyristor shown in FIG. 1, and FIG. 4 corresponds to the thyristor exterior of the present invention shown in FIG. 2. In the conventional thyristor structure, when the thyristor changes from the off state to the on state, current concentrates in the area A shown in FIG. As time passes, the current flow area spreads over the entire surface of the cathode layer at a speed vs. On the other hand, in the structure of the present invention, B shown in FIG.
The current is concentrated in the peripheral portion of the p+ atomized gate region 8, and its area expands at a speed vs. Therefore, in the present invention, the effective emitter peripheral length becomes longer and "dv/dt
Tolerance is improved. Further, since the above vs is inversely proportional to the thickness WB2 of the n-conductivity type base layer 1, in the present invention, this vs
becomes larger, which also contributes to improvement of di/dt tolerance. In addition, an n-conductivity type cathode (emitter) layer 4
, a p-conductivity type base layer 3 and an n-conductivity type base layer 1, the current amplification factor Q of the npn transistor depends on the density of the current flowing through the thyristor, and generally the Q increases as the current density increases.
このＱの電流密度依存性を小さくすれば、ｄｖ／ｄｔ耐
量が改善される。ｐ導電形ベース層３ａの厚みＷＢ，が
薄くなると、ｎ−ｐ−ｎトランジスタのベース輸送効率
はキャリャの拡散によって支配されるようになり、相対
的に電界によるドリフトの影響が少なくなる。したがっ
て、本発明の構造ではＱの電流依存性が小さくなり〜ｄ
ｖ／ｄｔ耐量が改善されることになる。以上説明したよ
うに、本発明による半導体制御整流装置によれば、ｎ導
霞形ベース層にｐ導電形ベース層を隣接して所定のパタ
ーンで形成されたｐ導電形のゲート領域を設けて該ｐ導
電形ベース層内の空乏層の延びを抑制することによりそ
のベース層の厚みを小さくし、かつ前記ベース層とｐ導
電形アノード層との間に設けた該ベース層より高い不純
物濃度を有する高濃度ベース領域により前記ｎ導電形ベ
ース層の厚みを小さくした構造としたので、前記ゲート
領域によってｐ導電形べ−ス層の厚みを十分薄くしてし
かも日頃方向耐圧を大きくすることができ、高速でかつ
高耐圧の半導体制御整流装置を提供することができると
いう効果がある。By reducing the current density dependence of Q, the dv/dt withstand capability is improved. When the thickness WB of the p-conductivity type base layer 3a becomes thinner, the base transport efficiency of the npn transistor comes to be dominated by carrier diffusion, and the influence of drift due to the electric field becomes relatively smaller. Therefore, in the structure of the present invention, the current dependence of Q becomes small ~d
The v/dt tolerance will be improved. As explained above, according to the semiconductor controlled rectifier according to the present invention, a p-conductivity type gate region formed in a predetermined pattern is provided adjacent to a p-conductivity type base layer on an n-conductivity hazy base layer. The thickness of the base layer is reduced by suppressing the extension of the depletion layer within the p-conductivity type base layer, and the base layer has a higher impurity concentration than the base layer provided between the base layer and the p-conductivity type anode layer. Since the structure is such that the thickness of the n-conductivity type base layer is reduced by the high concentration base region, the thickness of the p-conductivity type base layer can be sufficiently thinned by the gate region, and the breakdown voltage in the normal direction can be increased. This has the advantage that it is possible to provide a high-speed, high-voltage semiconductor-controlled rectifier.
第１図は従来のサィリスタを示す要部断面図、第２図は
本発明の一実施例を示すサィリスタ要部断面図、第３図
および第４図はそれぞれ従釆と本発明とのｄｉ／ｄＬｄ
ｖ／ｄｔの耐量の説明に供する説明図である。
１…・・・ｎ‐導電形ベース層「 ２・・…・ｐ＋導電
形アノード層、３，３ａ・・・・・・ｐ導電形ベース層
、４……ｎ＋導電形カソード層、５……アノード電極、
６・・・・・・カソード電極、７・・・・・・ゲート電
極、８・・・・・・ｐ＋導電形のゲート領域、９・・…
，げ導電形のべ−ス領域。
第１図
第２図
第３図
第４図FIG. 1 is a sectional view of the main part of a conventional thyristor, FIG. 2 is a sectional view of the main part of a thyristor showing an embodiment of the present invention, and FIGS. dLd
FIG. 2 is an explanatory diagram for explaining v/dt tolerance. 1...n-conductivity type base layer 2...p+ conductivity type anode layer, 3, 3a...p conductivity type base layer, 4...n+ conductivity type cathode layer, 5... anode electrode,
6...Cathode electrode, 7...Gate electrode, 8...P+ conductivity type gate region, 9...
, base area of conductive type. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
られたｐ導電形のアノード層およびベース層と、このｐ
導電形のベース層上に設けられたｎ導電形のカソード層
とからなる半導体制御整流装置において、前記ｎ導電形
のベース層に前記ｐ導電形のベース層と隣接して所定の
パターンで形成された該ｐ導電形ベース層より高い不純
物濃度を有するｐ導電形ゲート領域を設け、かつ前記ｎ
導電形ベース層と前記アノード層との間に該ベース層よ
り高い不純物濃度を有する高濃度ベース領域を設け、前
記ゲート領域の相互間隔を２ａ、前記ｐ導電形ベース層
の厚みおよび不純物濃度をそれぞれＷ＿ＢおよびＮａ、
前記導電形ベース層の不純物濃度をＮｄとしたとき、Ｎ
ｄ・ａ＾２＜Ｎａ・Ｗ＿Ｂ＾２ になるようにしたことを特徴とする半導体制御整流装置
。[Claims] 1 A base layer of n conductivity type, an anode layer and a base layer of p conductivity type provided on both sides of this base layer, and this p conductivity type base layer.
In a semiconductor controlled rectifier comprising a cathode layer of n conductivity type provided on a base layer of conductivity type, the base layer of n conductivity type is formed in a predetermined pattern adjacent to the base layer of p conductivity type. a p-conductivity type gate region having a higher impurity concentration than the p-conductivity type base layer;
A high concentration base region having an impurity concentration higher than that of the base layer is provided between the conductivity type base layer and the anode layer, the mutual spacing of the gate regions is 2a, and the thickness and impurity concentration of the p conductivity type base layer are respectively W_B and Na,
When the impurity concentration of the conductivity type base layer is Nd, N
A semiconductor-controlled rectifier device characterized in that d・a^2<Na・W_B^2.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12752779A JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
| CA000361937A CA1159158A (en) | 1979-10-01 | 1980-10-01 | Semiconductor controlled rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12752779A JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5650565A JPS5650565A (en) | 1981-05-07 |
| JPS6013311B2 true JPS6013311B2 (en) | 1985-04-06 |
Family
ID=14962213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12752779A Expired JPS6013311B2 (en) | 1979-10-01 | 1979-10-01 | Semiconductor controlled rectifier |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6013311B2 (en) |
| CA (1) | CA1159158A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IE53895B1 (en) * | 1981-11-23 | 1989-04-12 | Gen Electric | Semiconductor device having rapid removal of majority carriers from an active base region thereof at device turn-off and method of fabricating this device |
| JPS60142559A (en) * | 1983-12-29 | 1985-07-27 | Fujitsu Ltd | Programmable read only memory |
| GB8901342D0 (en) * | 1989-01-21 | 1989-03-15 | Lucas Ind Plc | Semiconductor device |
| US7638816B2 (en) * | 2007-08-28 | 2009-12-29 | Littelfuse, Inc. | Epitaxial surge protection device |
-
1979
- 1979-10-01 JP JP12752779A patent/JPS6013311B2/en not_active Expired
-
1980
- 1980-10-01 CA CA000361937A patent/CA1159158A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1159158A (en) | 1983-12-20 |
| JPS5650565A (en) | 1981-05-07 |
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