JPS6118861B2 - - Google Patents
Info
- Publication number
- JPS6118861B2 JPS6118861B2 JP52054285A JP5428577A JPS6118861B2 JP S6118861 B2 JPS6118861 B2 JP S6118861B2 JP 52054285 A JP52054285 A JP 52054285A JP 5428577 A JP5428577 A JP 5428577A JP S6118861 B2 JPS6118861 B2 JP S6118861B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon nitride
- film
- nitride film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- -1 nitrogen or ammonia Chemical compound 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
Landscapes
- Local Oxidation Of Silicon (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
(1) 発明の利用分野
本発明は、窒化シリコン膜を利用して選択酸化
を行う半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (1) Field of Application of the Invention The present invention relates to a method of manufacturing a semiconductor device that performs selective oxidation using a silicon nitride film.
(2) 従来技術
第１図に断面構造で示すように、従来技術にお
いては、MOSトランジスタを製作する場合、シ
リコン基板１上に素子分離用酸化膜２およびゲー
ト酸化膜３を形成後、多結晶シリコン４を堆積し
（第１図ａ）、ホトエツチングによりゲート電極を
形成する。その後、不純物拡散またはイオン打込
みによりソースおよびドレイン領域６を形成し
（第１図ｂ）、りんガラスの如き層間絶縁膜７を堆
積した後、ホトエツチングによりコンタクト孔８
を設け（第１図ｃ）、Al電極９を形成している
（第１図ｄ）。このような方法においては、コンタ
クト孔８を設ける場合、ホトエツチング工程のマ
スク合わせ余裕１０が必要となるために素子の面
積が大きくなつてしまう。(2) Prior Art As shown in the cross-sectional structure in Fig. 1, in the conventional technology, when manufacturing a MOS transistor, after forming an element isolation oxide film 2 and a gate oxide film 3 on a silicon substrate 1, polycrystalline Silicon 4 is deposited (FIG. 1a) and a gate electrode is formed by photoetching. Thereafter, source and drain regions 6 are formed by impurity diffusion or ion implantation (FIG. 1b), and after depositing an interlayer insulating film 7 such as phosphorous glass, contact holes 8 are formed by photoetching.
(FIG. 1c), and an Al electrode 9 is formed (FIG. 1d). In such a method, when forming the contact hole 8, a mask alignment margin 10 is required in the photo-etching process, resulting in an increase in the area of the device.
第２図に従来技術による２層多結晶シリコン構
造の１トランジスタ型メモリの製造工程を断面図
で示す。シリコン基板１上に素子分離用酸化膜
２、蓄積容量形成のための酸化膜３１および多結
晶シリコン電極５１、絶縁膜１１を設けた後（第
２図ａ）酸化を行い、ゲート酸化膜３、および多
結晶シリコン電極５１の側面の酸化膜３２を形成
している（第２図ｂ）。その後、ゲート電極５を
形成し、拡散層６１を設け（第２図ｃ）、りんガ
ラスの如き層間絶縁膜７を堆積した後、コンタク
ト孔８を設け、Al電極９を形成している（第２
図ｄ）。このような方法においては、多結晶シリ
コン電極５１はCVD（Chemical Vapor
Deposition）法などによつて形成したSiO2膜など
をマスクとしてエツチするために加工性が低下す
る。また、多結晶シリコン電極５１の側面の酸化
膜３２はゲート酸化膜３と同じ酸化工程で形成す
るために厚くすることができず、多結晶シリコン
電極５１とゲート電極５の間の耐圧を高くするこ
とができない。 FIG. 2 is a sectional view showing the manufacturing process of a one-transistor type memory having a two-layer polycrystalline silicon structure according to the prior art. After providing an oxide film 2 for element isolation, an oxide film 31 for forming a storage capacitor, a polycrystalline silicon electrode 51, and an insulating film 11 on a silicon substrate 1 (FIG. 2a), oxidation is performed to form a gate oxide film 3, Then, an oxide film 32 is formed on the side surface of the polycrystalline silicon electrode 51 (FIG. 2b). Thereafter, a gate electrode 5 is formed, a diffusion layer 61 is provided (FIG. 2c), an interlayer insulating film 7 such as phosphorous glass is deposited, a contact hole 8 is formed, and an Al electrode 9 is formed (Fig. 2c). 2
Figure d). In such a method, the polycrystalline silicon electrode 51 is heated by chemical vapor deposition (CVD).
Etching is performed using a SiO 2 film formed by a method such as Deposition method as a mask, resulting in poor processability. Furthermore, since the oxide film 32 on the side surface of the polycrystalline silicon electrode 51 is formed in the same oxidation process as the gate oxide film 3, it cannot be made thicker, which increases the breakdown voltage between the polycrystalline silicon electrode 51 and the gate electrode 5. I can't.
(3) 発明の目的
本発明はシリコン基板を窒素やアンモニアの如
き窒素を含む雰囲気中で、１気圧以上の圧力で加
熱することにより形成した窒化シリコン膜を利用
して、該基板上に絶縁膜を介して形成した導電性
電極を厚い酸化膜で覆うことにより前記欠点を取
り除くことのできる半導体装置の製造方法を提供
することを目的とする。(3) Purpose of the Invention The present invention utilizes a silicon nitride film formed by heating a silicon substrate at a pressure of 1 atmosphere or more in an atmosphere containing nitrogen such as nitrogen or ammonia, and forms an insulating film on the substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can eliminate the aforementioned drawbacks by covering conductive electrodes formed via a thick oxide film.
(4) 発明の総括説明
シリコン基板を窒素中で１気圧以上の圧力で加
熱すると次式で表わされる反応により、基板表面
に窒化シリコン膜が形成される。(4) General description of the invention When a silicon substrate is heated in nitrogen at a pressure of 1 atmosphere or more, a silicon nitride film is formed on the surface of the substrate by the reaction expressed by the following formula.
3Si＋2N2→Si3N4
第３図にシリコン基板を１気圧の窒素ガス中で
加熱した場合の窒化速度の温度依存性の一例を示
す。窒素ガスの圧力を高くすると窒化速度は著し
く増加する。このようにして形成された窒化シリ
コン膜の屈折率は1.8〜2.3（この中でも圧力を高
くするとこの値は大きくなる。）となつており、
気相反応などによつて形成した窒化シリコン膜と
同様に耐酸化性がある。第４図に、上記の方法に
従つて形成した窒化シリコン膜の900℃のwet酸
化に対する耐酸化性について検討した結果の一例
を示す。図から、シリコン基板を窒素中で加熱す
ることによつて形成した窒化シリコン膜は耐酸化
に対するマスクとして充分使用にたえうることが
わかる。なお、NH3ガス中で形成した窒化シリコ
ン膜に対しても同様な効果が得られる。 3Si+2N 2 →Si 3 N 4 Figure 3 shows an example of the temperature dependence of the nitriding rate when a silicon substrate is heated in nitrogen gas at 1 atmosphere. Increasing the nitrogen gas pressure significantly increases the nitriding rate. The refractive index of the silicon nitride film formed in this way is 1.8 to 2.3 (this value increases as the pressure is increased).
It has oxidation resistance similar to a silicon nitride film formed by a gas phase reaction or the like. FIG. 4 shows an example of the results of a study on the oxidation resistance of a silicon nitride film formed according to the above method to wet oxidation at 900°C. The figure shows that a silicon nitride film formed by heating a silicon substrate in nitrogen can be used satisfactorily as a mask for oxidation resistance. Note that a similar effect can be obtained for a silicon nitride film formed in NH 3 gas.
(5) 実施例
以下、本発明を実施例を参照して詳細に説明す
る。第５図は本発明の一例で、自己整合で形成さ
れたコンタクト孔を有するMOSトランジスタの
製造工程を断面図で示したものである。まず、比
抵抗15Ω・cm、結晶軸方向＜100＞のＰ形シリコ
ン基板１をH2Oを含む雰囲気中で1000℃、８時
間、局所酸化することにより1.3μｍの素子分離
用酸化膜２を設ける。次に、1000℃、100分の
dvy酸化により700Åのゲート酸化膜３を設け、
更に、CVD（Chemicnl Vapor Deposition）法
により、膜厚4000Å、層抵抗30Ω／口の多結晶シ
リコン４を堆積する（第５図ａ）。その後、ホト
エツチングによりゲート電極５を形成し、ソース
およびドレインとなる基板表面の700Åの酸化膜
を除去する。続いて、800℃、１時間wet酸化を
行つた後、酸化膜をエツチすることによりソース
およびドレインとなる基板表面１５の酸化膜を除
去し、かつ、ゲート電極５を1000Åの酸化膜１２
で被覆する（第５図ｂ）。第５図ｂに至る工程は
例えば特願昭50−70830号明細書に詳しく示され
ている。次に、20気圧の窒素ガス中、1100℃で２
時間加熱することにより露出したシリコン基板表
面１５に窒化シリコン膜１３を形成する（第５図
ｃ）。続いて、窒化シリコン膜１３を耐酸化マス
クとして、850℃、４時間酸化することによりゲ
ート電極上に5000Åの酸化膜１６を形成し、更に
コンタクト孔８を設けた後りん添加により表面を
りんガラス７１に変える。この場合、素子分離酸
化膜の表面もりんガラス７２に変化する（第５図
ｄ）。次に、窒化シリコン膜１３を除去し、Al電
極９を形成する（第５図ｅ）。第５図ｅでわかる
ように、本発明によればコンタクト孔８１は自己
整合で形成されるために素子の面積が非常に小さ
くなる。(5) Examples Hereinafter, the present invention will be explained in detail with reference to examples. FIG. 5 is an example of the present invention, which is a sectional view showing the manufacturing process of a MOS transistor having contact holes formed by self-alignment. First, a P-type silicon substrate 1 with a specific resistance of 15 Ω·cm and a crystal axis direction <100> is locally oxidized at 1000°C for 8 hours in an atmosphere containing H 2 O to form a 1.3 μm element isolation oxide film 2. establish. Next, 1000℃, 100 minutes
A gate oxide film 3 of 700 Å is provided by dvy oxidation.
Further, polycrystalline silicon 4 having a film thickness of 4000 Å and a layer resistance of 30 Ω/hole is deposited by CVD (chemical vapor deposition) (FIG. 5a). Thereafter, a gate electrode 5 is formed by photoetching, and a 700 Å thick oxide film on the substrate surface that will become a source and a drain is removed. Subsequently, after performing wet oxidation at 800°C for 1 hour, the oxide film on the substrate surface 15 that will become the source and drain is removed by etching the oxide film, and the gate electrode 5 is covered with an oxide film 12 with a thickness of 1000 Å.
(Figure 5b). The steps leading to FIG. 5b are shown in detail in, for example, Japanese Patent Application No. 70830/1983. Next, at 1100℃ in nitrogen gas at 20 atmospheres,
By heating for a period of time, a silicon nitride film 13 is formed on the exposed silicon substrate surface 15 (FIG. 5c). Next, using the silicon nitride film 13 as an oxidation-resistant mask, oxidation is performed at 850°C for 4 hours to form an oxide film 16 of 5000 Å on the gate electrode, and after forming a contact hole 8, the surface is made of phosphorus glass by adding phosphorus. Change it to 71. In this case, the surface of the element isolation oxide film also changes to phosphor glass 72 (FIG. 5d). Next, the silicon nitride film 13 is removed and an Al electrode 9 is formed (FIG. 5e). As can be seen in FIG. 5e, according to the present invention, the contact hole 81 is formed in a self-aligned manner, so that the area of the device becomes very small.
第６図は本発明の他の一例で２層多結晶シリコ
ン構造の１トランジスタ型メモリの製造工程を断
面図で示している。第６図ａ，ｂまでの工程は第
５図ａ〜ｃまでの工程と同様である。ただし、第
６図においては、酸化膜で被覆する多結晶シリコ
ン５１はMOSトランジスタのゲート電極ではな
く蓄積容量形成のための電極である。第６図ｂに
おいて、窒化シリコン膜１３を形成した後、850
℃、４時間酸化することにより、多結晶シリコン
電極５１上に5000Åの酸化膜１４を形成する（第
６図ｃ）。次に、窒化シリコン膜１３を除去した
後、CVD法により膜厚4000Å、層抵抗30Ω／口
の多結晶シリコン・ゲート電極５を形成し、更
に、1000℃のりん拡散により深さ1.0μｍ、層抵
抗15Ω／口の拡散層６１を設ける（第６図ｄ）。
続いて、8000Åのりんガラス膜（P2O5濃度5mole
％）７を堆積し、コンタクト孔８を設けた後、
1.2μｍのAlを形成する。 FIG. 6 is a cross-sectional view showing the manufacturing process of a one-transistor type memory having a two-layer polycrystalline silicon structure, which is another example of the present invention. The steps up to FIGS. 6a and 6b are the same as the steps up to FIGS. 5a to 5c. However, in FIG. 6, the polycrystalline silicon 51 covered with an oxide film is not a gate electrode of a MOS transistor but an electrode for forming a storage capacitor. In FIG. 6b, after forming the silicon nitride film 13, 850
℃ for 4 hours to form an oxide film 14 of 5000 Å on the polycrystalline silicon electrode 51 (FIG. 6c). Next, after removing the silicon nitride film 13, a polycrystalline silicon gate electrode 5 with a film thickness of 4000 Å and a layer resistance of 30 Ω/hole is formed by CVD, and then a layer with a depth of 1.0 μm is formed by phosphorus diffusion at 1000°C. A diffusion layer 61 with a resistance of 15 Ω/hole is provided (FIG. 6d).
Next, a 8000 Å phosphorus glass film (P 2 O 5 concentration 5 mole
After depositing %) 7 and providing contact holes 8,
Form 1.2 μm Al.
以上のようにして、本発明によれば多結晶シリ
コン電極５１を従来のように他の絶縁膜をマスク
としてエツチングすることがないため加工精度が
著しく向上し、かつ、多結晶シリコン電極５１と
ゲート電極５の間に厚い酸化膜を形成することが
できるために電極間の耐圧を高くすることができ
る。 As described above, according to the present invention, the processing accuracy is significantly improved because the polycrystalline silicon electrode 51 is not etched using another insulating film as a mask as in the conventional method, and the polycrystalline silicon electrode 51 and gate Since a thick oxide film can be formed between the electrodes 5, the breakdown voltage between the electrodes can be increased.
(6) まとめ
以上説明したごとく本発明によればシリコン基
板を直接窒化してできた窒化シリコン膜を耐酸化
のマスクとして酸化することにより導電性電極を
その酸化膜で厚く被覆できるので、自己整合によ
るコンタクト孔の形成、多層ゲート電極をもつ半
導体装置の製造が可能となる。(6) Summary As explained above, according to the present invention, by oxidizing the silicon nitride film produced by directly nitriding the silicon substrate as an oxidation-resistant mask, the conductive electrode can be thickly covered with the oxide film, thereby achieving self-alignment. This makes it possible to form contact holes and manufacture semiconductor devices with multilayer gate electrodes.
第１図は従来のMOSトランジスタの製造工程
を示す断面図、第２図は従来の２層多結晶シリコ
ンゲート構造の１トランジスタ型MOSメモリの
製造工程を示す断面図、第３図は窒化シリコン膜
の形成速度を示す図、第４図は窒化シリコン膜の
酸化特性を示す図、第５図は本発明によるMOS
トランジスタの製造工程を示す図、第６図は本発
明による２層多結晶シリコンゲート構造の１トラ
ンジスタ型MOSメモリの製造工程を示す図であ
る。
Figure 1 is a cross-sectional view showing the manufacturing process of a conventional MOS transistor, Figure 2 is a cross-sectional view showing the manufacturing process of a conventional 1-transistor MOS memory with a two-layer polycrystalline silicon gate structure, and Figure 3 is a silicon nitride film. FIG. 4 is a diagram showing the oxidation characteristics of silicon nitride film, and FIG. 5 is a diagram showing the formation rate of MOS according to the present invention.
FIG. 6 is a diagram showing the manufacturing process of a transistor, and FIG. 6 is a diagram showing the manufacturing process of a one-transistor type MOS memory having a two-layer polycrystalline silicon gate structure according to the present invention.
Claims (1)
を順次形成した後、所望箇所の該絶縁膜および導
電物質を除去し、前記導電物質露出面を絶縁膜で
被覆した後、窒素を含む雰囲気中で、加熱するこ
とによつて、前記絶縁膜を除去した部分の基板表
面に窒化シリコン膜を形成し、しかる後に酸化を
行う工程を含むことを特徴とする半導体装置の製
造方法。1. After sequentially forming an insulating film and a conductive material on the main surface of a semiconductor substrate, removing the insulating film and conductive material at desired locations, and coating the exposed surface of the conductive material with an insulating film, the method is performed in an atmosphere containing nitrogen. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a silicon nitride film on the surface of the substrate from which the insulating film has been removed by heating, and then oxidizing the silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5428577A JPS53139977A (en) | 1977-05-13 | 1977-05-13 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5428577A JPS53139977A (en) | 1977-05-13 | 1977-05-13 | Production of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53139977A JPS53139977A (en) | 1978-12-06 |
| JPS6118861B2 true JPS6118861B2 (en) | 1986-05-14 |
Family
ID=12966281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5428577A Granted JPS53139977A (en) | 1977-05-13 | 1977-05-13 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53139977A (en) |
-
1977
- 1977-05-13 JP JP5428577A patent/JPS53139977A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53139977A (en) | 1978-12-06 |
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