JPH0341775A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH0341775A JPH0341775A JP1177547A JP17754789A JPH0341775A JP H0341775 A JPH0341775 A JP H0341775A JP 1177547 A JP1177547 A JP 1177547A JP 17754789 A JP17754789 A JP 17754789A JP H0341775 A JPH0341775 A JP H0341775A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- silicon nitride
- nitride film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 7
- 230000005641 tunneling Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 229910003818 SiH2Cl2 Inorganic materials 0.000 abstract 2
- 102100037807 GATOR complex protein MIOS Human genes 0.000 abstract 1
- 101000950705 Homo sapiens GATOR complex protein MIOS Proteins 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＩＯ８（金属−絶縁膜−酸化シリコン膜−
半導体）型の電界効果トランジスタからなる半導体記憶
装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to MIO8 (metal-insulating film-silicon oxide film-
The present invention relates to a method of manufacturing a semiconductor memory device including a semiconductor type field effect transistor.
従来の技術
ＭＩＯ８型半導体記憶装置は、ゲートと基板との間に１
０〜２０Ｖ程度の高電圧を印加して、薄い酸化シリコン
膜と窒化シリコン膜の界面、またはその近傍の窒化シリ
コン膜中のトラップ準位に、半導体基板側から電荷の注
入、蓄積を行ない、トランジスタのしきい値電圧を変化
させて、情報を記憶させるものである。それゆえに、薄
い酸化シリコン膜の形成および、窒化シリコン膜の形成
においては、その膜厚および膜質、更に境界面の状態が
重要である。Conventional technology MIO8 type semiconductor memory device has one
By applying a high voltage of about 0 to 20 V, charge is injected and accumulated from the semiconductor substrate side into the trap level in the silicon nitride film at or near the interface between the thin silicon oxide film and the silicon nitride film, thereby forming a transistor. Information is stored by changing the threshold voltage of the memory. Therefore, in forming a thin silicon oxide film and a silicon nitride film, the thickness and quality of the film, as well as the state of the interface are important.
従来、ＭＩＯ８型半導体記憶装置の代表的なものとして
、第３図に示すようなＭＮＯＳ （金属−窒化シリコン
膜−酸化シリコン膜−半導体〉構造の半導体記憶装置が
よく知られている。同図において、１はＰ型シリコン基
板、２および３は、ソースおよびドレイン領域、８は薄
い酸化シリコン膜、５は窒化シリコン膜、７はゲート電
極である。第３図のような構造のＭＮＯ８型半導体記憶
装置では、ソース領域２、およびドレイン領域３の間に
はさまれたチャンネル領域に接して対向する部分全体に
、薄い酸化シリコン膜８が広がっており、通常、酸素ま
たは酸素中にアルゴンあるいは窒素等の不活性ガスを混
合した希釈酸化法などにより、シリコン基板を熱酸化し
て形成し、その厚さは電荷のトンネル領域を起こしやす
くするために、２０Ａ程度と薄くしている。また、薄い
酸化シリコン膜８上の窒化シリコン膜５の膜厚は、１０
〜２０Ｖの電圧で書き込み、消去を行なうことができる
ように、２００〜３００Ａ程度と、比較的薄くなってい
る。通常、窒化シリコン膜５は、減圧ＣＶＤ法により形
成される。Conventionally, a semiconductor memory device with an MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) structure as shown in FIG. 3 is well known as a typical MIO8 type semiconductor memory device. , 1 is a P-type silicon substrate, 2 and 3 are source and drain regions, 8 is a thin silicon oxide film, 5 is a silicon nitride film, and 7 is a gate electrode.The MNO8 type semiconductor memory has a structure as shown in FIG. In the device, a thin silicon oxide film 8 is spread over the entire portion facing and in contact with the channel region sandwiched between the source region 2 and the drain region 3, and is usually made of oxygen or argon or nitrogen in oxygen. It is formed by thermally oxidizing a silicon substrate using a dilute oxidation method mixed with an inert gas, and the thickness is kept as thin as about 20A to facilitate charge tunneling. The thickness of the silicon nitride film 5 on the silicon film 8 is 10
It is relatively thin, about 200 to 300 A, so that writing and erasing can be performed with a voltage of ~20 V. Usually, the silicon nitride film 5 is formed by a low pressure CVD method.
発明が解決しようとする課題
従って、従来の構造のＭＮＯ８型半導体記憶装置におい
て、薄い酸化シリコン膜を形成する場合、熱酸化炉に入
れる前の洗浄等の前処理の方法等において、熱酸化後の
膜厚に大きく影響を与え、良質でしかも均一な酸化シリ
コン膜の形成が困難であるという問題点を有しており、
しかも再現性にとぼしいという問題点もあり、量産時に
おける一つの障害となっている。Problems to be Solved by the Invention Therefore, when forming a thin silicon oxide film in an MNO8 type semiconductor memory device with a conventional structure, in a pretreatment method such as cleaning before entering a thermal oxidation furnace, The problem is that it greatly affects the film thickness and makes it difficult to form a high quality and uniform silicon oxide film.
Moreover, there is also the problem of poor reproducibility, which is an obstacle in mass production.
本発明の目的は、こうした問題点に対し、ＭＩＯ８型の
半導体記憶装置における。消去特性の向上をはかること
のできる新規な構造を提供することにある。An object of the present invention is to provide an MIO8 type semiconductor memory device to solve these problems. The object of the present invention is to provide a novel structure capable of improving erasing characteristics.
課題を解決するための手段
上記目的を達成すべく、本発明は、−導電型半導体基板
中に設けられたソース領域、ドレイン領域にはさまれた
チャンネル領域上に、トンネリング媒体となりうる薄い
酸化シリコン膜を形成する工程において、減圧ＣＶＤ法
により薄い酸化シリコン膜を形成し、その後、連続して
同一の炉を使用して窒化シリコン膜を形成するものであ
る。Means for Solving the Problems In order to achieve the above objects, the present invention provides: - a thin silicon oxide layer that can be used as a tunneling medium on a channel region sandwiched between a source region and a drain region provided in a conductive type semiconductor substrate; In the step of forming a film, a thin silicon oxide film is formed by a low pressure CVD method, and then a silicon nitride film is continuously formed using the same furnace.
作用
本発明の製造方法によれば、トンネル領域である酸化シ
リコン膜およびトンネルした電荷をトラップする領域で
ある窒化シリコン膜が同一炉で連続して形成することが
でき、更に、酸化シリコン膜を形成する工程において、
熱酸化法によらず、減圧ＣＶＤ法を採用することにより
、均一で再現性の良い良質の薄い酸化シリコン膜を形成
することかでき、特に消去特性の安定化をはかることが
できる。Effect: According to the manufacturing method of the present invention, a silicon oxide film as a tunnel region and a silicon nitride film as a region for trapping tunneled charges can be formed successively in the same furnace, and furthermore, a silicon oxide film can be formed. In the process of
By employing the low pressure CVD method instead of the thermal oxidation method, it is possible to form a thin silicon oxide film of good quality that is uniform and has good reproducibility, and in particular, it is possible to stabilize the erasing characteristics.
実施例
本発明の半導体記憶装置の実施例を第１図に示した断面
構造図を用いて説明する。Embodiment An embodiment of the semiconductor memory device of the present invention will be described with reference to the cross-sectional structural diagram shown in FIG.
これは、Ｐ型シリコン基板１の中にＮ十拡散領域である
ソース、ドレイン２．３が形成され、Ｎ十拡散領域にま
たがって薄い酸化シリコン膜４が設けられ、薄い酸化シ
リコンｒｍ、４上に窒化シリコン膜５、更に窒化シリコ
ンｌ１５Ｉ５上に減圧ＣＶＤ法により酸化シリコン膜６
、が順次積層され、ゲート電極７が形成された構造であ
る。In this structure, a source and drain 2.3, which are N0 diffusion regions, are formed in a P-type silicon substrate 1, a thin silicon oxide film 4 is provided across the N0 diffusion regions, and a thin silicon oxide film 4 is provided on the thin silicon oxide rm, 4. A silicon nitride film 5 is formed on the silicon nitride film 5, and a silicon oxide film 6 is further formed on the silicon nitride film 5 by low pressure CVD.
, are sequentially stacked to form a gate electrode 7.
次に、第１図に示す構造を実現する製造方法の一実施例
を第２図（Ａ）〜（Ｆ）の工程順断面図により説明する
。Next, an embodiment of a manufacturing method for realizing the structure shown in FIG. 1 will be described with reference to step-by-step sectional views of FIGS. 2(A) to 2(F).
まず、第２図（Ａ）に示すように、Ｐ型シリコン基板１
の全面に、酸化シリコン膜９を５００Ａ形成し、更に窒
化シリコン膜１０を１２００Ａ程度形威した後、素子分
離のため所定の部分を公知のフォトエツチング技術でエ
ツチングを行う。First, as shown in FIG. 2(A), a P-type silicon substrate 1
After forming a silicon oxide film 9 of 500 Å on the entire surface and further forming a silicon nitride film 10 of about 1200 Å, predetermined portions are etched using a known photoetching technique for element isolation.
次いで、第２図（Ｂ）に示すように、通常の熱酸化法に
よりフィールド酸化膜１１を１μｍ程度形成させる。Next, as shown in FIG. 2(B), a field oxide film 11 having a thickness of about 1 μm is formed by a normal thermal oxidation method.
次に、第２図（Ｃ）に示すように、窒化シリコン膜１０
と、その下の酸化シリコン膜９を順次エツチングした後
、２０Ａ程度の薄い酸化シリコン膜４を、ジクロルシラ
ン（Ｓ ｉ Ｈ２Ｃ１２）と−酸化窒素（Ｎ２０’）の
化学反応に基づく、気相成長法により形成させる。更に
、連続して同一の炉において、第１図（Ｄ）に示すよう
に、薄い酸化シリコン膜４上に、ジクロルシラン（Ｓｉ
Ｈ２ＣＩ２）とアンモニア（Ｎ Ｈｓ ）の化学反応に
基づく、気相成長法により窒化シリコン膜５を形成させ
る。Next, as shown in FIG. 2(C), a silicon nitride film 10
After sequentially etching the underlying silicon oxide film 9, a thin silicon oxide film 4 of about 20A is grown using a vapor phase growth method based on a chemical reaction between dichlorosilane (S i H2C12) and -nitrogen oxide (N20'). Let it form. Furthermore, in the same furnace, dichlorosilane (Si
A silicon nitride film 5 is formed by a vapor phase growth method based on a chemical reaction between H2CI2) and ammonia (NHs).
本実施例では、成長温度７５０℃、ガス流量比ＮＨ３／
Ｓ １Ｈ２Ｃｌ２＝ＩＯ，Ｈ２０／５ｉＨ２ＣＩ２＝３
の条件化で、窒化シリコン膜５を３０ＯＡ、酸化シリコ
ン膜４を２０Ａ形威した。更に、連続して同一の炉にお
いて、窒化シリコン膜５上に、５０Ａ程度の酸化シリコ
ン膜６を同様のＣＶＤ法により形成する。次いで、全面
にリンをトニブしたポリシリコン膜１２を４０００八程
度形成させ、次いでゲートとなりうる部分のみを残して
、ポリシリコン膜１２、酸化シリコン膜６、窒化シリコ
ン膜５、酸化シリコン！ＩＮ ４をフォトレジストを用
いた公知のフォトエツチング技術によりパタニングを行
う。次いで、Ｎ十拡散領域２．３をフォトレジストをマ
スクとしてヒ素イオンを打ち込み（４０ＫｅＶ、’ ３
ｘ １０１５ｃ＋ｍ−２）形成する。In this example, the growth temperature was 750°C, and the gas flow rate ratio NH3/
S 1H2Cl2=IO, H20/5iH2CI2=3
Under these conditions, the silicon nitride film 5 was made to have a thickness of 30 OA, and the silicon oxide film 4 was made to have a thickness of 20 Å. Further, in the same furnace, a silicon oxide film 6 of about 50 Å is successively formed on the silicon nitride film 5 by the same CVD method. Next, a polysilicon film 12 doped with phosphorus is formed on the entire surface to an extent of about 4,000 yen, and then the polysilicon film 12, the silicon oxide film 6, the silicon nitride film 5, and the silicon oxide film are formed, leaving only the portion that can become the gate. Patterning is performed on IN 4 by a known photoetching technique using a photoresist. Next, arsenic ions are implanted into the N+ diffusion region 2.3 using a photoresist as a mask (40KeV, '3
x 1015c+m-2).
次いで、第２図（Ｅ）に示すように、気相成長法により
、酸化シリコンＭ’Ｊ １３を全面に被着した後、ソー
ス、ドレインの押し込みと、酸化シリコン膜の５窒化の
ために、９００℃で３０分、０２雰囲気中で熱処理を行
う。最後に、フォトエツチング技術によりコンタクト孔
を開孔し、アルミニウム電極１４を形威し、第２図（Ｆ
）に示すＭＮＯ８型半導体記憶装置を製作することがで
きる。Next, as shown in FIG. 2(E), silicon oxide M'J 13 is deposited on the entire surface by vapor phase growth, and then the source and drain are pushed in and the silicon oxide film is 5-nitrided. Heat treatment is performed at 900° C. for 30 minutes in a 02 atmosphere. Finally, a contact hole is opened using photoetching technology, and an aluminum electrode 14 is formed.
) can be manufactured.
発明の詳細
な説明したところから明らかなように、本発明の製造方
法によれば、ＭＩＯ８型半導体記憶装置の、薄い酸化シ
リコン膜の形成工程と、窒化シリコン膜の形成工程が、
連続してしかち同一炉で処理ができるため、ＭｒＯ３型
半導体記憶装置の信頼性の向上に大きく寄与できる。As is clear from the detailed description of the invention, according to the manufacturing method of the present invention, the step of forming a thin silicon oxide film and the step of forming a silicon nitride film of an MIO8 type semiconductor memory device are as follows:
Since the process can be performed continuously and in the same furnace, it can greatly contribute to improving the reliability of MrO3 semiconductor memory devices.
第１図は本発明によるＭＮＯ８型半導体記憶装置の構造
を示す断面図、第２図は、本発明によるＭ Ｎ ＯＳ型
半導体記憶装置の製造方法の一例を示す工程順断面図、
第３図は従来のＭＮＯ８型半導体記憶装置の構造を示す
断面図である。
１・・・・・・Ｐ型シリコン基板、２，３・・・・・・
ソース及びドレイン領域、４・・・・・・ＣＶＤ法によ
る薄い酸化シリコン膜、５・・・・・・窒化シリコン膜
、６・・・・・・ＣＶＤ法による酸化シリコン膜、７・
・・・・・ゲート電極、８・・・・・・熱酸化法による
薄い酸化シリコン膜、９・・・・・酸化シリコン膜、１
０・・・・・・窒化シリコン膜、１１・・・・・・フィ
ールド酸化膜、１２・・・・・・ポリシリコン膜、１３
・・・・・・酸化シリコン膜、１４・・・・・・アルミ
ニウム電極。FIG. 1 is a cross-sectional view showing the structure of an MNO8 type semiconductor memory device according to the present invention, and FIG. 2 is a step-by-step cross-sectional view showing an example of a method for manufacturing an MNO8 type semiconductor memory device according to the present invention.
FIG. 3 is a cross-sectional view showing the structure of a conventional MNO8 type semiconductor memory device. 1... P-type silicon substrate, 2, 3...
Source and drain regions, 4... Thin silicon oxide film by CVD method, 5... Silicon nitride film, 6... Silicon oxide film by CVD method, 7.
... Gate electrode, 8 ... Thin silicon oxide film by thermal oxidation method, 9 ... Silicon oxide film, 1
0...Silicon nitride film, 11...Field oxide film, 12...Polysilicon film, 13
. . . Silicon oxide film, 14 . . . Aluminum electrode.
Claims (1)
ソース領域およびドレイン領域が形成され、同ソース領
域およびドレイン領域にはさまれたチャンネル領域上に
、トンネリング媒体となりうる薄い酸化シリコン膜を減
圧ＣＶＤ法により形成し、連続して前記薄い酸化シリコ
ン膜上に窒化シリコン膜および前記窒化シリコン膜上に
酸化シリコン膜を順次減圧ＣＶＤ法により形成すること
を特徴とする半導体記憶装置の製造方法。A source region and a drain region of a conductivity type opposite to that of the semiconductor substrate are formed in a semiconductor substrate of one conductivity type, and a thin silicon oxide film that can serve as a tunneling medium is formed on a channel region sandwiched between the source region and drain region. A method for manufacturing a semiconductor memory device, characterized in that a silicon nitride film is successively formed on the thin silicon oxide film and a silicon oxide film is sequentially formed on the silicon nitride film by a low pressure CVD method. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177547A JPH0341775A (en) | 1989-07-10 | 1989-07-10 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1177547A JPH0341775A (en) | 1989-07-10 | 1989-07-10 | Manufacture of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0341775A true JPH0341775A (en) | 1991-02-22 |
Family
ID=16032858
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1177547A Pending JPH0341775A (en) | 1989-07-10 | 1989-07-10 | Manufacture of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0341775A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999049517A1 (en) * | 1998-03-24 | 1999-09-30 | Siemens Aktiengesellschaft | Memory cell arrangement and method of production thereof |
| JP2006032797A (en) * | 2004-07-20 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor storage device and its manufacturing method |
-
1989
- 1989-07-10 JP JP1177547A patent/JPH0341775A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999049517A1 (en) * | 1998-03-24 | 1999-09-30 | Siemens Aktiengesellschaft | Memory cell arrangement and method of production thereof |
| JP2006032797A (en) * | 2004-07-20 | 2006-02-02 | Matsushita Electric Ind Co Ltd | Nonvolatile semiconductor storage device and its manufacturing method |
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