JPS62205664A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS62205664A JPS62205664A JP4888686A JP4888686A JPS62205664A JP S62205664 A JPS62205664 A JP S62205664A JP 4888686 A JP4888686 A JP 4888686A JP 4888686 A JP4888686 A JP 4888686A JP S62205664 A JPS62205664 A JP S62205664A
- Authority
- JP
- Japan
- Prior art keywords
- source
- photoresist
- insulating film
- drain
- polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010409 thin film Substances 0.000 title claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 25
- 239000007789 gas Substances 0.000 claims description 7
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 2
- 229910021478 group 5 element Inorganic materials 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 abstract description 2
- 229910008479 TiSi2 Inorganic materials 0.000 abstract description 2
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000010453 quartz Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910020968 MoSi2 Inorganic materials 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000032544 Cicatrix Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は液晶テレビ用の人面梢簿膜トランジスｊタスイ
ッチアレイまたは駆動回路あるいは密者型長尺−次元セ
ンサーの駆動回路での他三次元ＬＳＩ用の機能素子など
に使用される薄膜トランジスタ（ＴＰＴ）の！！７造方
決方法する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to human face film transistor switch arrays or drive circuits for LCD televisions, or other three-dimensional LSIs in drive circuits for close-contact long-dimensional sensors. Thin film transistors (TPT) used in functional devices, etc. ! 7 How to make it.
従来の技術
従来本発明と最も類似しているＴ Ｆ １の製造方法は
、アモルファスシリコンａ−３ｉを用いたＴ Ｉ’丁で
ある。第２図にその工程図を示づ。第２図（八）におい
て、ガラス基板１上にＮｉＣｒゲート電極２を形成し、
その後ゲート絶縁膜となるシリ：」ン酸化膜３、活性層
となるアモルファスシリコン層４、保護膜となるシリコ
ン酸化膜５を真空を破らず連続的にグロー放電法で形成
し、次にこのシリコン酸化膜５上にＡＺレジスト６を塗
布して背面露光を行なうと、ゲート電極２がマスクとな
るため第２図（＾）に示したような自己整合されたパタ
ーンが形成される。次いで、第２図（Ｂ）のように、ソ
ース・ドレインとなる部分のシリコン酸化ｖ５を選択的
にエツチングする。その後、第２図（Ｃ）のように基板
４Ｕ １２０℃でｎ” ａ−８ｉ：１Ｉｔｔ２ｆ ７を
グロー放電法で堆積し、その上部にＮｉＣｒ電極８を蒸
肴する。しかる後、第２図（０）のように、ソース・ド
レイン領域以外のＡＺレジスト６をリフトオフしてフォ
トレジスト上のｎ” ａ−８ｉ：Ｈｌｉｌ ７、ＮｉＣ
ｒ電極８を除去する。BACKGROUND OF THE INVENTION The method for manufacturing TF1 that is most similar to the present invention is TI' using amorphous silicon a-3i. Figure 2 shows the process diagram. In FIG. 2 (8), a NiCr gate electrode 2 is formed on a glass substrate 1,
Thereafter, a silicon oxide film 3 that will become a gate insulating film, an amorphous silicon layer 4 that will become an active layer, and a silicon oxide film 5 that will become a protective film are formed continuously by a glow discharge method without breaking the vacuum. When an AZ resist 6 is applied on the oxide film 5 and back exposure is performed, a self-aligned pattern as shown in FIG. 2(^) is formed because the gate electrode 2 serves as a mask. Next, as shown in FIG. 2(B), the silicon oxide v5 at the portions that will become the source and drain is selectively etched. Thereafter, as shown in FIG. 2(C), n''a-8i:1Itt2f 7 is deposited on the substrate 4U at 120° C. by a glow discharge method, and a NiCr electrode 8 is vaporized on top of it. 0), the AZ resist 6 other than the source/drain region is lifted off and the n" a-8i:Hlil 7, NiC
Remove the r electrode 8.
発明が解決しようとする問題点
従来の技術で述べた例では、ソース・ドレインとなる領
域のｎ” ａ−３ｉ：ＨＱ５はフォトレジストの存在の
ため昇温温度に限界があり、低抵抗化に限界があり、ま
たコンタクト抵抗の増大などの問題があった。特に活性
層がａ−８ｉでなく、多結晶Ｓｉのような場合、従来技
術のようにｎ” ａ−３ｉ：ｆｌを用いることはｎ”
ａ−３ｉ：ｔｌと多結晶Ｓｉの間の界面の問題もあり、
困難であった。Problems to be Solved by the Invention In the example described in the conventional technology, there is a limit to the heating temperature of the n''a-3i:HQ5 in the source/drain region due to the presence of photoresist, and it is difficult to lower the resistance. There are limitations and problems such as an increase in contact resistance.Especially when the active layer is not a-8i but polycrystalline Si, it is not possible to use n'' a-3i:fl as in the prior art. n”
a-3i: There is also the problem of the interface between tl and polycrystalline Si,
It was difficult.
本発明は、ａ−８ｉおよび多結晶ＳｉＴ Ｆ Ｔのいず
れにしても適用できる自己整合型ＴＰＴを製造覆る新規
な方法を提供づることを目的とする。The present invention aims to provide a new method for manufacturing self-aligned TPTs, which is applicable to both a-8i and polycrystalline SiTFTs.
問題点を解決覆るための手段
上記問題点を解決づるために本発明は、透明絶縁基板の
一重部にゲート電極、ゲート絶縁膜、活性Ｓｉ層、絶縁
保護膜、フォトレジストを形成し、前記基板の他主面か
らの露光により前記ゲート電極をマスクとして前記フォ
トレジストおよび絶縁膜を選択的に除去し、前記フォト
レジストを除去した後前記絶縁保護膜をマスクとしてソ
ース・ドレインとなるべき前記活性Ｓｉの領域にｍ族あ
るいはＶ族元素と水素原子を用いて不純物のドーピング
を行なうものである。Means for Solving and Overcoming the Problems In order to solve the above-mentioned problems, the present invention forms a gate electrode, a gate insulating film, an active Si layer, an insulating protection film, and a photoresist on a single portion of a transparent insulating substrate. The photoresist and the insulating film are selectively removed by exposure from the other main surface using the gate electrode as a mask, and after removing the photoresist, the active Si to be the source/drain is removed using the insulating protection film as a mask. The region is doped with impurities using an M group or V group element and hydrogen atoms.
さらに本発明は、活性Ｓｉ層のソース・ドレイン領域に
前記元素を不純物として導入するに際し、ｍ族またはＶ
族元素を含むガスを用いたプラズマ放電中あるいはその
放電空間近傍に基板を置いて、不純物をドーピングする
ものである。Furthermore, in the present invention, when introducing the above-mentioned elements as impurities into the source/drain regions of the active Si layer,
In this method, a substrate is placed in a plasma discharge using a gas containing group elements or near the discharge space, and doped with impurities.
作用
上記構成により、ソース・ドレインとなるべき領域に所
望元素を自己整合的にドーピングでき、従来問題となっ
ていたゲートとドレイン間の重なり寄生容量の極めて少
ない素子を形成することが可能となり、しかも、水素原
子も同時に導入するため、従来イオンビーム例えばＢ１
をイオン注入後熱処理してもあまり活性化せず、また＃
Ａ傷も多く残留した欠陥は補償され、水素の離脱による
膜特性劣化も緩和きれる。Operation With the above configuration, it is possible to dope the desired element in a self-aligned manner in the regions to become the source and drain, and it is possible to form an element with extremely low overlap parasitic capacitance between the gate and the drain, which has been a problem in the past. , since hydrogen atoms are also introduced at the same time, conventional ion beams such as B1
Even if heat treated after ion implantation, it does not activate much, and #
Many A-scars and remaining defects are compensated for, and the deterioration of film properties due to the elimination of hydrogen can be alleviated.
実施例
以下、本発明の一実施例を図面に基づいて説明する。第
１図（＾）において、１１は石英、ソーダガラスなどの
透明基板であり、該基板１１にゲート電極１２をたとえ
ばＣｒ、 ＨｏＳｉ２． ＴｉＳｉ２などあるいはこれ
らの複合層により約１０００人形成づる。続いてＳｉＯ
２，Ｓｉ３Ｎ４の如きゲート絶縁膜１３を例えば１００
０人形成し、その上に多結晶Ｓｉ膜１４．５ｉＱ２の如
き絶縁膜１５を形成づる。多結晶Ｓｉ膜１４はノンドー
プもしくは最終的にＨあるいはＨと１０００ｐｐＨ以下
の８を含んだ膜である。しかる後、Ｊなる寸法の多＠膜
島領域をフォトエッチして形成する。その後再度フォト
レジスト１６を塗布し、光１７により背面露光して、少
なくともソース・ドレイン領域の前記フォトレジスト１
６および絶縁膜１５を除去し、ソース・ドレイン領域に
開孔部１８．１９を形成する。EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings. In FIG. 1(^), reference numeral 11 is a transparent substrate made of quartz, soda glass, etc., and a gate electrode 12 is formed on the substrate 11 using, for example, Cr, HoSi2. Approximately 1,000 layers are formed by TiSi2 or a composite layer thereof. Next, SiO
2. For example, the gate insulating film 13 such as Si3N4 is
An insulating film 15 such as a polycrystalline Si film 14.5iQ2 is formed thereon. The polycrystalline Si film 14 is a non-doped film or a film that finally contains H or H and 8 of 1000 ppH or less. Thereafter, a multi-film island region of size J is formed by photoetching. Thereafter, a photoresist 16 is applied again, and the back side is exposed to light 17 to remove the photoresist 16 at least in the source/drain region.
6 and the insulating film 15 are removed, and openings 18 and 19 are formed in the source/drain regions.
しかる後、ゲート電極２上方のフォトレジスト１６を除
去し、絶縁ＷＡ１５をマスクとして例えば低温でＶ族の
リンネ純物２０を第１図（Ｂ）のように多結晶Ｓｉ層１
４のソース・ドレイン領域に導入する。このリンネ純物
２０を活性化するために、後で例えば６００℃で熱処理
する。不純物導入法として１（２ガスを主成分とし、ｐ
Ｈ３ガスを例えば１〜２０％程度含むガスのグロー放電
中あるいはその放電空間近（ηに基板を設置し、プラズ
マ成型を用いた不純物導入を行なう。こうしてソース領
域２１、ドレイン領域２２が形成される。その後にソー
ス電極２３とドレイン電極２４が形成され、第１図（Ｃ
）に示すＴ［丁が得られる。Thereafter, the photoresist 16 above the gate electrode 2 is removed, and using the insulating WA 15 as a mask, for example, V-group Linnaeus 20 is applied to the polycrystalline Si layer 1 at a low temperature as shown in FIG. 1(B).
4 into the source/drain regions. In order to activate this Linnaeus pure substance 20, it is later heat-treated at, for example, 600°C. Impurity introduction method 1 (mainly composed of 2 gases, p
A substrate is placed during a glow discharge of a gas containing, for example, 1 to 20% H3 gas or near the discharge space (η), and impurities are introduced using plasma molding. In this way, a source region 21 and a drain region 22 are formed. After that, a source electrode 23 and a drain electrode 24 are formed, as shown in FIG.
) is obtained.
フォトレジスト１６を除去して例えば１００〜５００℃
のＷ４状態でソース・ドレイン領域に不純物２０を選択
導入覆るときは、特に多結晶Ｓｉの場合Ｐ原子とともに
水素原子が基板１１に導入され、しかも水素の方がＰ原
子より拡散係数が大きいため、Ｐ原子による接合付近の
欠陥を補償し、良好な接合形成が得られる。また、例え
ば絶縁膜１５として５１０２を用いる場合、水素原子が
５ｉ０２−ＰｏｌｙＳｉ界面のみならず、多結晶Ｓｉ全
体の欠陥を補償し、良好なＴＰＴ特性が青られる原因と
なる。なお、不純物とし′ＣＶ族の元素の代りに、■族
の元素を用いてもよい。After removing the photoresist 16, for example, at 100 to 500°C.
When selectively introducing impurities 20 into the source/drain regions in the W4 state, especially in the case of polycrystalline Si, hydrogen atoms are introduced into the substrate 11 together with P atoms, and since hydrogen has a larger diffusion coefficient than P atoms, Defects near the junction due to P atoms are compensated for, and a good junction can be formed. Further, when using 5102 as the insulating film 15, for example, hydrogen atoms compensate for defects not only at the 5i02-PolySi interface but also in the entire polycrystalline Si, causing good TPT characteristics to deteriorate. Incidentally, instead of the 'CV group element, an element of the group (2) may be used as an impurity.
ブで明の効果
以上本発明によるＴＰＴ製造工程では、従来と比べて工
程の簡略化、コンタクト抵抗の改善、ａ−８ｉＴ Ｆ
Ｔのみならず多結晶５ｉＴＦＴにも拡張展間が容易で、
しかも逆方向リーク電流の低減、応答速度の改善が図ら
れ、工業上極めて大きな効果を有するものである。As described above, the TPT manufacturing process according to the present invention simplifies the process, improves contact resistance, and improves the a-8iT F
It is easy to expand not only TFT but also polycrystalline 5i TFT.
In addition, the reverse leakage current is reduced and the response speed is improved, which has extremely large industrial effects.
第１図は本発明の一実施例によるＴＰＴの製造工程を示
す断面図、第２図は従来のＴ Ｐ Ｔの製造工程を示す
断面図である。
１１・・・透明具板、１２・・・ゲート電極、１３・・
・ゲート絶縁膜、１４・・・多結晶Ｓｉ膜、１５・・・
絶＊ｉ １１９．１６・・パノ４トレジスト、１７・・
・光、１８．１９・・・ソース・ドレイン領域！：ｎ孔
部、２０・・・リンネ純物〈ト１２ガスを主成分とする
ｐ１１３ガス） 、 ２１．２２・・・ソース・ドレイ
ン領域、２３、２４・・・ソース・ドレイン電極代理人
森 本 八 弘ヘ
へ
〈 ジ
Ｃ＼ 〜 勺 聾偽喝 トFIG. 1 is a sectional view showing the manufacturing process of a TPT according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional TPT. 11...Transparent plate, 12...Gate electrode, 13...
・Gate insulating film, 14... Polycrystalline Si film, 15...
Zetsu*i 119.16... Pano 4 Tresist, 17...
・Light, 18.19...source/drain region! : N hole part, 20... Linnaean pure substance (P113 gas whose main component is T12 gas), 21.22... Source/drain region, 23, 24... Source/drain electrode representative Morimoto Hachihirohe
He〈 Ji C
Claims (1)
、活性Ｓｉ層、絶縁保護膜、フォトレジストを形成し、
前記基板の他主面からの露光により前記ゲート電極をマ
スクとして前記フォトレジストおよび絶縁膜を選択的に
除去し、前記フォトレジストを除去した後前記絶縁保護
膜をマスクとしてソース・ドレインとなるべき前記活性
Ｓｉの領域にIII族あるいはＶ族元素と水素原子を用い
て不純物のドーピングを行なう薄膜トランジスタの製造
方法。 ２、透明絶縁基板をIII族またはＶ族元素を含むガスを
用いたプラズマ放電中あるいはその放電空間近傍に置き
不純物をドーピングすることを特徴とする特許請求の範
囲第１項記載の薄膜トランジスタの製造方法。 ３、不純物のドーピングを１００〜５００℃の昇温状態
で行なうことを特徴とする特許請求の範囲第１項記載の
薄膜トランジスタの製造方法。[Claims] 1. A gate electrode, a gate insulating film, an active Si layer, an insulating protective film, and a photoresist are formed on one main surface of a transparent insulating substrate,
The photoresist and the insulating film are selectively removed by exposure from the other main surface of the substrate using the gate electrode as a mask. A method for manufacturing a thin film transistor in which an active Si region is doped with impurities using Group III or Group V elements and hydrogen atoms. 2. A method for manufacturing a thin film transistor according to claim 1, characterized in that the transparent insulating substrate is placed in or near a plasma discharge using a gas containing a Group III or V element and doped with an impurity. . 3. The method for manufacturing a thin film transistor according to claim 1, wherein the impurity doping is carried out at an elevated temperature of 100 to 500°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4888686A JPS62205664A (en) | 1986-03-06 | 1986-03-06 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4888686A JPS62205664A (en) | 1986-03-06 | 1986-03-06 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62205664A true JPS62205664A (en) | 1987-09-10 |
Family
ID=12815759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4888686A Pending JPS62205664A (en) | 1986-03-06 | 1986-03-06 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62205664A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63158875A (en) * | 1986-12-22 | 1988-07-01 | Nec Corp | Manufacture of thin-film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPS6427271A (en) * | 1987-07-22 | 1989-01-30 | Nec Corp | Manufacture of thin-film transistor |
| JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
| JPH01235384A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01235383A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film field-effect transistor |
| JPH02177323A (en) * | 1988-12-27 | 1990-07-10 | Matsushita Electric Ind Co Ltd | Impurity introduction |
| JPH04273445A (en) * | 1991-02-28 | 1992-09-29 | G T C:Kk | Thin film semiconductor device and its production |
| EP0902481A2 (en) * | 1997-09-10 | 1999-03-17 | Xerox Corporation | Thin film transistor with reduced parasitic capacitance |
| US5926701A (en) * | 1994-12-21 | 1999-07-20 | Sony Electronics, Inc. | Thin film transistor fabrication technique |
| US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6500703B1 (en) | 1993-08-12 | 2002-12-31 | Semicondcutor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP2016520205A (en) * | 2013-04-28 | 2016-07-11 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Array substrate, manufacturing method thereof, and display device including the array substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168278A (en) * | 1982-03-30 | 1983-10-04 | Toshiba Corp | Manufacture of thin film transistor |
| JPS6114762A (en) * | 1984-06-29 | 1986-01-22 | Toshiba Corp | Manufacture of thin film field effect transistor |
-
1986
- 1986-03-06 JP JP4888686A patent/JPS62205664A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168278A (en) * | 1982-03-30 | 1983-10-04 | Toshiba Corp | Manufacture of thin film transistor |
| JPS6114762A (en) * | 1984-06-29 | 1986-01-22 | Toshiba Corp | Manufacture of thin film field effect transistor |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63158875A (en) * | 1986-12-22 | 1988-07-01 | Nec Corp | Manufacture of thin-film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPS6427271A (en) * | 1987-07-22 | 1989-01-30 | Nec Corp | Manufacture of thin-film transistor |
| JPH01115162A (en) * | 1987-10-29 | 1989-05-08 | Matsushita Electric Ind Co Ltd | Thin film transistor and manufacture thereof |
| JPH01235384A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH01235383A (en) * | 1988-03-16 | 1989-09-20 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film field-effect transistor |
| JPH02177323A (en) * | 1988-12-27 | 1990-07-10 | Matsushita Electric Ind Co Ltd | Impurity introduction |
| JPH04273445A (en) * | 1991-02-28 | 1992-09-29 | G T C:Kk | Thin film semiconductor device and its production |
| US6323069B1 (en) | 1992-03-25 | 2001-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor using light irradiation to form impurity regions |
| US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
| US6569724B2 (en) | 1992-03-25 | 2003-05-27 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and method for forming the same |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6437366B1 (en) | 1993-08-12 | 2002-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US6500703B1 (en) | 1993-08-12 | 2002-12-31 | Semicondcutor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US7381598B2 (en) | 1993-08-12 | 2008-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| US5926701A (en) * | 1994-12-21 | 1999-07-20 | Sony Electronics, Inc. | Thin film transistor fabrication technique |
| EP0902481A3 (en) * | 1997-09-10 | 2000-06-21 | Xerox Corporation | Thin film transistor with reduced parasitic capacitance |
| EP0902481A2 (en) * | 1997-09-10 | 1999-03-17 | Xerox Corporation | Thin film transistor with reduced parasitic capacitance |
| JP2016520205A (en) * | 2013-04-28 | 2016-07-11 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Array substrate, manufacturing method thereof, and display device including the array substrate |
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