JPS61154077A - Manufacture of mosfet - Google Patents
Manufacture of mosfetInfo
- Publication number
- JPS61154077A JPS61154077A JP27369184A JP27369184A JPS61154077A JP S61154077 A JPS61154077 A JP S61154077A JP 27369184 A JP27369184 A JP 27369184A JP 27369184 A JP27369184 A JP 27369184A JP S61154077 A JPS61154077 A JP S61154077A
- Authority
- JP
- Japan
- Prior art keywords
- concentration impurity
- gate
- oxide film
- polycrystalline silicon
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 23
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 10
- 239000011574 phosphorus Substances 0.000 abstract description 10
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000001039 wet etching Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 2
- -1 Phosphorus ions Chemical class 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 1
- YLPGTOIOYRQOHV-UHFFFAOYSA-N Pretilachlor Chemical compound CCCOCCN(C(=O)CCl)C1=C(CC)C=CC=C1CC YLPGTOIOYRQOHV-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に係り、特に基板とドレ
イン間の耐圧を向上した構造のＭＯＳＦＥＴの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a MOSFET having a structure with improved breakdown voltage between a substrate and a drain.
〔発明の技術的背景とその間４点〕
Ｍ０８ＦＦｆＴの通常の構造では基板とドレイン間の接
合の逆電界の他にゲートとドレインの電界が加わるため
ドレインの基板側に拡がる空乏層は基板表面のチャネル
領域付近で余り拡がらず、電界の高い領域が生じ、なだ
れ降伏が起り易くなる。[Technical background of the invention and 4 points] In the normal structure of M08FFfT, in addition to the reverse electric field of the junction between the substrate and drain, the electric field of the gate and drain is applied, so the depletion layer that spreads toward the substrate side of the drain becomes a channel on the substrate surface. It does not spread much near the region, creating a region with a high electric field, making avalanche breakdown more likely.
そのため、ＭＯＳＦＥＴのドレインと基板間の耐圧は、
ドレインと基板間のｐｎ接合単独のそれと比べてかなり
低い値となってしまい、素子としての特性上低下させ信
頼性を落としてしまう。これを改善した他の構造のＭＯ
ＳＦＥＴが知られている。Therefore, the breakdown voltage between the MOSFET drain and substrate is
This value is considerably lower than that of the pn junction alone between the drain and the substrate, which deteriorates the characteristics of the device and reduces its reliability. MO of other structure that improved this
SFET is known.
半導体のｐｎ接合には空乏層領域が生じる。その空乏層
領域の幅は、ｐ形ｎ形各々の半導体の不純物濃度に関係
し、その値が小さい種牛じる空乏層の幅は大きくなる。A depletion layer region occurs in a pn junction of a semiconductor. The width of the depletion layer region is related to the impurity concentration of the p-type and n-type semiconductors, and the smaller the value, the larger the width of the depletion layer.
したがって、ＭＯ８ＦＢＴの中でｐｎ接合の１つである
ドレインと基板間において、ドレインの不純物濃度を低
くするとその間に生じる空乏層が拡がるので、今まで幅
の小さな空乏層に印加されていた電圧が幅の大きな空乏
層に印加されるようになり１界集中が緩和され、ドレイ
ンと基板間の耐圧が向上する。Therefore, when the impurity concentration of the drain is lowered between the drain, which is one of the pn junctions in MO8FBT, and the substrate, the depletion layer formed between the drain and the substrate expands, so that the voltage that was previously applied to the narrow depletion layer becomes wider. Since the current is applied to a large depletion layer, the concentration of one field is alleviated, and the withstand voltage between the drain and the substrate is improved.
上記を実現させるＭＯ８ＦＢＴの構造として、ゲートと
ドレイン、が離れているオフセットゲート構造のＭＯ８
ＦＢＴにおいてイオン注入によりオフセット部分に自己
整合的に低濃度不純物領域を形成したものが知られてい
る。低濃度不純物領域とゲート間での耐圧低下は起こら
ないためドレインと基板間の耐圧は向上する。一般にこ
のような構造をＬ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐ
ｅｄ Ｄｒａｉｎ ）構造と呼ぶ。The MO8FBT structure that achieves the above is an offset gate structure in which the gate and drain are separated.
An FBT in which a low concentration impurity region is formed in a self-aligned manner at an offset portion by ion implantation is known. Since no reduction in breakdown voltage occurs between the low concentration impurity region and the gate, the breakdown voltage between the drain and the substrate is improved. Generally, such a structure is called LDD (Lightly Dop
ed Drain) structure.
以下、ＬＤＤ＠造のＭＯ８ＦＢＴの従来の製造方法を図
によって説明する。第２図は従来の一例を示すＬＤＤ構
造のＭＯ１９ＦＥＴの製造工程断面図である。Hereinafter, a conventional manufacturing method of MO8FBT manufactured by LDD@ will be explained with reference to the drawings. FIG. 2 is a cross-sectional view of a manufacturing process of an MO19FET having an LDD structure, showing an example of the conventional method.
第２図（１）に示すように、ｐ形シリコン基板２１上△
に膜厚５００又のゲート酸化膜２２を熱酸化法により形
成し、その上に化学気相成長（以下ＣＶＤと略す）法に
より膜厚ａｏｏｏ、にの多結晶シリコン層２３を形成し
、燐（Ｐ）を拡教する。その後、ゲート形状に多結墨シ
リコン層２３とゲート酸化膜２２をパターニングする。As shown in FIG. 2 (1), a gate oxide film 22 with a thickness of 500 mm is formed on a p-type silicon substrate 21 by thermal oxidation method, and then chemical vapor deposition (hereinafter abbreviated as CVD) is applied on top of the gate oxide film 22. A polycrystalline silicon layer 23 with a thickness of aooo is formed using the following steps, and phosphorus (P) is diffused therein. Thereafter, the multi-ink silicon layer 23 and the gate oxide film 22 are patterned into a gate shape.
次に第２図（ｂ）に示すように、多結晶シリコン層２３
をマスクとして、注入量２ Ｘ １０■（ｃｍ−”）
＋注入エネルギー４０（ＫｅＶ：）の条件で燐（Ｐ）の
イオン注入を行ない浅い低濃度不純物領域２４を形成す
る。次に第２図（ｃ）に示すように、ＣＶＤ法を用いて
膜厚５０００λの酸化膜２５を形成する。次に第２図（
ｃ＋）に示すように、反応性イオンエツチング（以下几
１１３と略す）により多結晶シリコン層２３が露出する
まで酸化膜２５（ｉ−除去する。この際、多結晶シリコ
ン２３の側面では膜厚的３ｏｏｏ＆の酸化膜２５Ａが残
る。次に第２図（ｅ）に示すように、多結晶シリコン層
２３及びその側面の酸化膜２５人をマスクとして注入量
２ Ｘ １０” （ｍ−”） 、注入エネルギー４０
（Ｋｅｙ）の条件で燐（Ｐｌのイオン注入を行ない深い
高１度不純物領域２６を形成する。その後、熱処理によ
り各不純物領域の不純物は活性化され、ＬＤＤ構造のＭ
ＯＳ Ｆ ＥＴが得られる。Next, as shown in FIG. 2(b), a polycrystalline silicon layer 23
As a mask, injection amount 2 x 10cm (cm-”)
A shallow low concentration impurity region 24 is formed by ion implantation of phosphorus (P) under the condition of +implantation energy of 40 (KeV:). Next, as shown in FIG. 2(c), an oxide film 25 having a thickness of 5000λ is formed using the CVD method. Next, Figure 2 (
As shown in c+), the oxide film 25 (i-) is removed by reactive ion etching (hereinafter abbreviated as 113) until the polycrystalline silicon layer 23 is exposed. An oxide film 25A of 3ooo& is left behind. Next, as shown in FIG. energy 40
(Key) ion implantation of phosphorus (Pl) is performed to form a deep high degree impurity region 26. After that, the impurity in each impurity region is activated by heat treatment, and the M of the LDD structure is
OS FET is obtained.
しかし、従来の技術には以下のような問題点がある。However, the conventional technology has the following problems.
ＣＶＤ法により形成される酸化膜の厚さは所定数値の士
約１０％であり熱酸化法による士約２にに比ベバラツキ
が大きい。したがって、ゲート電極である多結晶シリコ
ン層２３上の酸化膜２５は一七の膜厚にバラツキが大き
いため、その総てをＲＩ）３により除去する際、活性イ
オンがシリコン基板２１表面及び多結−晶シリコン層２
３表面に直接衝突する部分がありその表面がエツチング
され損傷が生じる恐れがある。The thickness of the oxide film formed by the CVD method is about 10% of the predetermined value, and the variation is large compared to about 2% of the predetermined value. Therefore, since the oxide film 25 on the polycrystalline silicon layer 23 which is the gate electrode has large variations in film thickness, when all of it is removed by RI)3, active ions are -crystalline silicon layer 2
3. There is a part that directly collides with the surface, and there is a risk that the surface will be etched and damaged.
又、ＲＩＢによるエツチングそれ自体にも多少場所によ
るバラツキがあるため、上述と同様な恐れがある。Furthermore, since the etching by RIB itself has some variation depending on the location, there is a possibility similar to that described above.
又、ゲート酸化膜である多結晶シリコン層２３の側面に
形成する酸化膜２５Ａの形状は、多結晶シリコン層２３
の厚さ及び長さ及び幅や酸化膜２５の厚さに依存するの
で、所定の形状に制御することは−しい。そのため、そ
の形状がなだらかに伸びてしまい、後工程のイオン注入
におけるマスクとして所定１部分のみを覆うことが難し
い。Further, the shape of the oxide film 25A formed on the side surface of the polycrystalline silicon layer 23, which is the gate oxide film, is similar to that of the polycrystalline silicon layer 23.
It is difficult to control the shape to a predetermined shape because it depends on the thickness, length, and width of the oxide film 25 and the thickness of the oxide film 25. Therefore, its shape stretches gently, making it difficult to cover only one predetermined portion as a mask for ion implantation in a subsequent process.
本発明の目的は、信頼性の高い微細化されたＬＤＤ構造
のＭ０８ＦＦｉＴを容易に得ることができる製造方法を
提供することにある。An object of the present invention is to provide a manufacturing method that can easily obtain a highly reliable M08FFiT having a miniaturized LDD structure.
本発明は、半導体基板上にゲート絶縁膜を形成し、その
上にゲート形状に物質を形成し、このゲート形状の物質
をマスクとして半導体基板と反対導電型の高濃度不純物
領域を形成し、全面を酸化した後に総て除去し、酸化さ
れて小さくなったゲート形状の物質をマスクとして半導
体基板と反対導電型の低濃度不純物領域を形成するドレ
インと基板間が高耐圧であるＭＯ８ＦＥＴの製造方法で
ある。In the present invention, a gate insulating film is formed on a semiconductor substrate, a material is formed in the shape of a gate on it, and a highly concentrated impurity region of the opposite conductivity type to the semiconductor substrate is formed using this gate-shaped material as a mask. This method of manufacturing MO8FETs has a high breakdown voltage between the drain and the substrate, in which the oxidized gate-shaped material is used as a mask to form a low concentration impurity region of the opposite conductivity type to the semiconductor substrate. be.
以下本発明の一実施例を図面によって説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す製造工程断面図である
。FIG. 1 is a sectional view of a manufacturing process showing an embodiment of the present invention.
第１図（ａ）に示すように、Ｐ型シリコン基板ｌｌ上に
ドライ酸素雰囲気中で９００℃１０分間のＭｄ化により
膜厚５００Ｘのゲート酸化膜１２を形成し、その上面に
ＣＶＤ法により膜厚３０００Ｘの多結晶シリコン層１３
を形成する。その後反応性イオンエツチング（８丁・Ｅ
）により多結晶シリコン層１３を、７ツ化アンモニウム
（ＮＨ，Ｆ）液を用いたウェットエツチングによりゲー
ト酸化膜１２を頭次ゲート形状にバターニングする。次
に第１図（ｂ）に示すように、ゲート形状にパターニン
グした多結晶７リコン層１３をマスクとして、注入量２
ＸＩ０１１〔副〕、注入エネルギー４０ （ＫｅＶ ）
の条件で燐（Ｐ）のイオン注入を行ない、深い高濃度不
純物層１６を形成する。次に第１図（ｃ）に示すよりＶ
Ｃ，ドライ酸素雰囲気中で９５０℃、１５分間の熱酸化
により全面に酸化膜１５を形成する。この際、多結晶シ
リコン層１３の表出部側は酸化されるので、多結晶シリ
コン層１３Ａは小さくなってしまり。As shown in FIG. 1(a), a gate oxide film 12 with a thickness of 500× is formed on a P-type silicon substrate 11 by Md treatment at 900° C. for 10 minutes in a dry oxygen atmosphere, and a film is deposited on its upper surface by CVD. Polycrystalline silicon layer 13 with a thickness of 3000X
form. After that, reactive ion etching (8 pieces/E
), and the gate oxide film 12 is patterned into a vertical gate shape by wet etching using an ammonium 7tride (NH,F) solution. Next, as shown in FIG. 1(b), using the polycrystalline silicon layer 13 patterned in the gate shape as a mask, the implantation amount is 2.
XI011 [sub], implantation energy 40 (KeV)
Phosphorus (P) ion implantation is performed under these conditions to form a deep high concentration impurity layer 16. Next, as shown in Fig. 1(c), V
C. An oxide film 15 is formed on the entire surface by thermal oxidation at 950° C. for 15 minutes in a dry oxygen atmosphere. At this time, since the exposed side of the polycrystalline silicon layer 13 is oxidized, the polycrystalline silicon layer 13A becomes smaller.
次に第１図（ｄ）に示すように、酸化膜１５をフッ化ア
ンモニウム（ＮＨ，ＰＪ液を用い九ウェットエツチング
により除去する。ここで、前工程の酸化により、多結晶
シリコン層１３人のゲートは小さくなりているので、ゲ
ートとソース・ドレインが重ならないオフセット構造と
なっている。次に第１図（＋りに示すように、小さくな
った多結晶シリコン層１３Ａのゲートをマスクとして注
入量２Ｘ１０”（ｍ 、ｌ。Next, as shown in FIG. 1(d), the oxide film 15 is removed by wet etching using ammonium fluoride (NH, PJ solution). Since the gate is smaller, it has an offset structure in which the gate and source/drain do not overlap. Next, as shown in Figure 1 (+), implantation is performed using the gate of the polycrystalline silicon layer 13A, which has become smaller, as a mask. Amount 2X10” (m, l.
注入エネルギー４０（ＫｅＶ”ｌの条件で燐（Ｐ）のイ
オン注入を行ない、浅い低濃度不純物層１４を形成する
。その後、１０５０℃、２０分間の熱処理により低濃度
不純物領域１４と、高濃度不純物領域１６を形成するた
めに注入した燐（Ｐｌを活性化する。Phosphorus (P) ions are implanted under conditions of implantation energy of 40 (KeV"l) to form a shallow low concentration impurity layer 14. Thereafter, a heat treatment at 1050° C. for 20 minutes forms the low concentration impurity region 14 and the high concentration impurity layer. Activate the phosphorus (Pl) implanted to form region 16.
以上のようにして、ＬＤＤ構造のＭＯＳ Ｆ ）！ｉＴ
を得ることができる。As described above, the LDD structure MOS F)! iT
can be obtained.
以上説明したこの実施例によれば以下の効果が得られる
。According to this embodiment described above, the following effects can be obtained.
従来技術ではＣＶＤ法による膜厚の不均一な酸化膜２５
を、場所によるエツチングのバラツキのあるＲＩＦｉｔ
−用いて、多結晶シリコン層２３が露出するまで除去す
る。したがって、１％ｌｌ１ｔによるシリコン基板２１
表面の損傷が部分的に生じ、又後のイオン注入の際にマ
スクとなる多結晶シリコン層２３のゲートの側面に形成
される酸化膜２５人の形状制御が難しい。しかし、 こ
の実施例ではＲＩＥによる活性イオンがシリコン基板１
１に直接衝突する可能性はないので、シリコン基板１１
表面に損傷を与えることはない。更に、多結晶シリコン
層のゲートの側面に酸化膜１５を形成する際、ＣＶＤ法
ではなく熱酸化法を用いるのでその形状制御が正確にな
るので、微細化が可能となる。In the conventional technology, an oxide film 25 with a non-uniform thickness is formed using the CVD method.
, RIFit has variations in etching depending on location.
- Remove the polycrystalline silicon layer 23 until it is exposed. Therefore, the silicon substrate 21 by 1%ll1t
The surface is partially damaged, and it is difficult to control the shape of the oxide film 25 formed on the side surface of the gate of the polycrystalline silicon layer 23, which will serve as a mask during subsequent ion implantation. However, in this example, the active ions due to RIE are
Since there is no possibility of direct collision with silicon substrate 11
Will not damage surfaces. Further, when forming the oxide film 15 on the side surface of the gate of the polycrystalline silicon layer, a thermal oxidation method is used instead of a CVD method, so that its shape can be precisely controlled, and miniaturization becomes possible.
なお、本発明は上述し九実施例に限定されるものではな
く、その要旨を脱しない範囲で変更して実施することが
できる。例えば、シリコン基板１．１の導′−型はｐ形
に限らすル形でもよいのは勿論のことである。又、酸化
工程の際、実施例ではドライ熱酸化法によるが、ＣＶＤ
法を除く他の酸化法例えばウェット熱酸化法で置きかえ
てもよい。又、多結晶シリコン層１３や熱酸化法による
酸化Ｊ［１５をエツチングする際十分な膜厚であれば、
実施例では几Ｉｇｔ−用いているが、ウェットエツチン
グ等それ以外のエツチング方法で置きかえてもよい。It should be noted that the present invention is not limited to the nine embodiments described above, and can be implemented with modifications within the scope of the invention. For example, the conductive type of the silicon substrate 1.1 is not limited to the p-type, but it goes without saying that it may be of the round type. In addition, during the oxidation process, although dry thermal oxidation method is used in the example, CVD
Alternatively, other oxidation methods such as wet thermal oxidation may be used instead. Also, if the film thickness is sufficient when etching the polycrystalline silicon layer 13 or the oxidized J[15 by thermal oxidation method,
Although Igt etching is used in the embodiment, other etching methods such as wet etching may be used instead.
又、多結晶シリコン層１３のゲートをマスクトシて不純
物のイオン注入を行なう際、実施例では注入する部分の
ゲート酸化［１２を除去した後に行なりたが、ゲート酸
化膜１２は十分薄いので除去せずにそれを介して行なう
こともできる。又、ゲート物質として、実施例では燐（
ＰＪを含んだ多結晶シリコン層１３ｔ−用いているが、
半導体基板よりも酸化速度が早い物質であれば置きかえ
てもよい。Furthermore, when performing impurity ion implantation by masking the gate of the polycrystalline silicon layer 13, in the embodiment, the implantation was performed after removing the gate oxidation [12] of the implanted portion, but since the gate oxide film 12 is sufficiently thin, it is not necessary to remove it. You can also do it through it. In addition, as a gate material, phosphorus (
Although a polycrystalline silicon layer 13t containing PJ is used,
Any substance may be replaced as long as it has a faster oxidation rate than the semiconductor substrate.
ｃ′発明の効果〕
本発明によれば、製造工程の中でＣＶＤ法や半導体基板
表面に損傷を与える恐れのめるＲＩＢｔ−用いず、又自
己整合的に不純物領域を形成するので、信頼性の高い微
細化されたドレイン基板間が高耐圧のＭＯ８Ｆ ｌ１ｉ
Ｔｔ−容易に製造できる。c' Effects of the invention] According to the present invention, impurity regions are formed in a self-aligned manner without using the CVD method or with RIBt, which may damage the semiconductor substrate surface, in the manufacturing process, resulting in high reliability. MO8F l1i with high breakdown voltage between miniaturized drain and substrate
Tt - Easy to manufacture.
第１図は本発明の一実施例を示すＭＯＳＦＥＴの製造工
程断面図、第２図は従来の一例を示すＭＯ８ＦＥＴの製
造工程断面図である。
１１．２１・・・シリコン基板。
１２．２２・・・ゲート酸化膜。
１３．２３・・・多結晶シリコン層。
１４．２４・・・低濃度不純物領域。
１５．２５・・・酸化膜。
１６．２６・・・高濃度不純物領域。
代理人 弁理士 則 近 憲 佑
（ほか１名）
第１図FIG. 1 is a cross-sectional view of the manufacturing process of a MOSFET showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the manufacturing process of a MO8FET showing an example of the conventional art. 11.21...Silicon substrate. 12.22...Gate oxide film. 13.23...Polycrystalline silicon layer. 14.24...Low concentration impurity region. 15.25...Oxide film. 16.26...High concentration impurity region. Agent: Patent attorney Noriyuki Chika (and 1 other person) Figure 1
Claims (1)
ゲート絶縁膜上にゲートとなる物質を所定形状に形成す
る工程と、この所定形状の物質をマスクとして前記半導
体基板内にこの半導体基板と反対導電型の高濃度不純物
領域を形成する工程と、前記半導体基板及び前記所定形
状の物質の表出部を酸化する工程と、この酸化膜を除去
する工程と、前記所定形状の物質の酸化されない部分を
マスクとして前記半導体基板内にこの半導体基板と反対
導電型の前記高濃度不純物領域より浅い低濃度不純物領
域を形成する工程とを含むことを特徴とするＭＯＳＦＥ
Ｔの製造方法。A step of forming a gate insulating film on a semiconductor substrate, a step of forming a material to be a gate in a predetermined shape on the gate insulating film, and a step of forming a material in the semiconductor substrate opposite to the semiconductor substrate using the material in the predetermined shape as a mask. a step of forming a high concentration impurity region of a conductive type; a step of oxidizing the exposed portion of the semiconductor substrate and the material having the predetermined shape; a step of removing the oxide film; and a portion of the material having the predetermined shape that is not oxidized. forming a low concentration impurity region shallower than the high concentration impurity region of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate using as a mask.
Method for manufacturing T.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27369184A JPS61154077A (en) | 1984-12-27 | 1984-12-27 | Manufacture of mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27369184A JPS61154077A (en) | 1984-12-27 | 1984-12-27 | Manufacture of mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61154077A true JPS61154077A (en) | 1986-07-12 |
Family
ID=17531207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27369184A Pending JPS61154077A (en) | 1984-12-27 | 1984-12-27 | Manufacture of mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61154077A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520879A (en) * | 2004-01-14 | 2007-07-26 | 東京エレクトロン株式会社 | Method for trimming gate electrode |
-
1984
- 1984-12-27 JP JP27369184A patent/JPS61154077A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007520879A (en) * | 2004-01-14 | 2007-07-26 | 東京エレクトロン株式会社 | Method for trimming gate electrode |
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