JPS6055665A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6055665A JPS6055665A JP16366883A JP16366883A JPS6055665A JP S6055665 A JPS6055665 A JP S6055665A JP 16366883 A JP16366883 A JP 16366883A JP 16366883 A JP16366883 A JP 16366883A JP S6055665 A JPS6055665 A JP S6055665A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- layer
- oxide film
- gate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000007772 electrode material Substances 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 230000000873 masking effect Effects 0.000 abstract 2
- 239000012535 impurity Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法の改良に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method for manufacturing a semiconductor device.
周知の如く、半導体装置例えばＭＯ８型トランジスタに
おいては、素子の微細化、高速化及び高密度化傾向には
めざましいものがあり、これはプロセスにおけるＰＥＰ
技術の進歩、浅い接合を形成できるイオン打込技術及び
低温プロセスによるところが大きい。As is well known, in semiconductor devices such as MO8 type transistors, there is a remarkable trend toward miniaturization, speeding up, and higher density of elements, and this is due to PEP in the process.
This is largely due to advances in technology, ion implantation techniques that can form shallow junctions, and low-temperature processes.
特に、ＭＯ８型トランジスタのゲート幅は、近年３μｍ
から２μｍへと微細化されており、素子の高速化、高密
度化に寄与している。しかしながら、ゲート幅が２μｍ
以下程度になると、いわゆるショートチャネル効果及び
バンチスルー等の不都合な問題が顕在化している。In particular, the gate width of MO8 type transistors has been increasing to 3 μm in recent years.
It has been miniaturized from 2 μm to 2 μm, contributing to higher speed and higher density devices. However, the gate width is 2μm
Below this level, disadvantageous problems such as the so-called short channel effect and bunch-through become apparent.
従来、ＭＯ８型トランジスタとして社、例えば第１図に
示すものが知られている。図中の１はＰ型の半導体基板
でおる。この基板１表面には、Ｎ型のソース、ドレイン
領域２，３が形成されている。同基板１上にはフィール
ド酸化膜４が形成されており、このフィールド酸化膜４
で囲まれた前記基板１の素子領域５上にはゲート絶縁膜
６を介してゲート電極７が形成されている。こうした第
１図のＭＯ８型トランジスタによれば、ソース、ドレイ
ン領域２，３の形成Ｖｒ、ハ、一般にセルファジインで
形成するプロセスが用いられるため、ゲート電極７とソ
ース、ドレイン領域２，３間はマスク合せの必要がなく
、素子の微細化に有利でおる。しかしながら、ソース、
ドレイン領域２，３は最終的に０．５〜１．５μｍの拡
散深度となり、横方向への拡散も等方的に考えると、ソ
ース、ドレイン領域２，３にゲート１１極７下の基板１
に侵入して形成される。その結果、実効チャネルは設計
チャネルよりも短くなり、しきい値が所定の値よりも低
くなる、いわゆるショートチャネル効果を生じる。BACKGROUND OF THE INVENTION Conventionally, MO8 type transistors, such as the one shown in FIG. 1, have been known. 1 in the figure is a P-type semiconductor substrate. On the surface of this substrate 1, N-type source and drain regions 2 and 3 are formed. A field oxide film 4 is formed on the substrate 1.
A gate electrode 7 is formed on the element region 5 of the substrate 1 surrounded by a gate insulating film 6 . According to the MO8 type transistor shown in FIG. 1, the formation of the source and drain regions 2 and 3 is generally carried out using a process of cell phasing, so the gap between the gate electrode 7 and the source and drain regions 2 and 3 is masked. There is no need for alignment, which is advantageous for miniaturization of elements. However, the source
The drain regions 2 and 3 will eventually have a diffusion depth of 0.5 to 1.5 μm, and considering the lateral diffusion isotropically, the source and drain regions 2 and 3 will have a diffusion depth of 0.5 to 1.5 μm.
is formed by invading the As a result, the effective channel becomes shorter than the design channel, resulting in a threshold value lower than a predetermined value, a so-called short channel effect.
ま友、このように実効チャネルが短くなると、ソース、
ドレイン領域２，３の空乏層がつなが９、パンチスルー
してしまい、素子の耐圧が劣化する。Mayu, when the effective channel becomes shorter like this, the source,
The depletion layers of the drain regions 2 and 3 are connected 9 and punch-through occurs, degrading the withstand voltage of the device.
しかるに、前述したショートチャネル効果、パンチスル
ー現象を抑制する最も有効な手段は、ソース、ドレイン
領域の拡散深度を浅くして実効チャネル長の短縮を防止
すればよい。しかしながら、拡散層の深さを全体的に浅
くすると、拡散層の抵抗が高くなり、回路動作上の問題
が発生する。このようなことから、最近、以下に示すＬ
Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ
）構造のＭＯ８型トランジスタが提案されている。次
に、このトランジスタの製造法を第２図（ａ）〜（ｅ）
を参照して説明する。However, the most effective means for suppressing the short channel effect and punch-through phenomenon described above is to reduce the diffusion depth of the source and drain regions to prevent shortening of the effective channel length. However, if the overall depth of the diffusion layer is made shallow, the resistance of the diffusion layer increases, causing problems in circuit operation. For this reason, recently, the following L
D D (Lightly Doped Drain
) structure has been proposed. Next, the manufacturing method of this transistor is shown in Figs. 2(a) to (e).
Explain with reference to.
まず、周知の技術により、Ｐ型の半導体基板１上にフィ
ールド酸化膜４を形成した後、このフィールド酸化膜４
で囲まれた基板１の素子領域５上にゲート絶縁膜６を介
してゲート電極７ ′を形成する。つづいて、このゲー
ト電極７等をマスクとして例えば砒素をドーズ′！ｊｋ
１０ 偏でイオン注入し、浅いＮ型の不純物層１１．．
１１゜を形成する（第２図（ａ）図示）。次いで、全面
にＣＶＤ ５ｉｎ２膜１２ ’ｌ形成Ｔル（ｔＪｆ、
２ 図（ｂ）図示）。First, a field oxide film 4 is formed on a P-type semiconductor substrate 1 using a well-known technique.
A gate electrode 7' is formed on the element region 5 of the substrate 1 surrounded by a gate insulating film 6. Next, using this gate electrode 7 etc. as a mask, for example, arsenic is dosed. jk
10 Ion implantation is performed unevenly to form a shallow N-type impurity layer 11. ．．
11° (as shown in FIG. 2(a)). Next, a CVD 5in2 film 12'l is formed on the entire surface (tJf,
2 (as shown in Figure (b)).
なお、ＣＶＤ ５ｉＱｉ膜の代りにＳ ｉ ｓ Ｎ４膜
を用いてもよい。更に、前記ＣＶＤ５ｉＯ＊膜１２を反
応性イオンエツチング（ＲＩＥ）法でエツチングし、ゲ
ート電極７、ゲート絶縁膜６及びフィールド酸化膜４の
側壁にのみｃｖｐｓｉｏ、膜１２／を残存させる（第２
図＜ｃ）図示）。この後、例えは砒素ｔドーズ１ｌｔ２
〜３ｘ１０Ｉｓｍ１テ再度イオン注入することによって
深いＮ型の不純物層１３．。Note that a Si s N4 film may be used instead of the CVD 5iQi film. Furthermore, the CVD5iO* film 12 is etched by reactive ion etching (RIE) to leave the CVPSIO film 12/ only on the side walls of the gate electrode 7, gate insulating film 6, and field oxide film 4 (second
Figure<c)Illustrated). After this, the example is arsenic t dose 1lt2
A deep N-type impurity layer 13.~3x10Ism1 is implanted again. .
１３２を形成する。その結果、不純物層１１．。132 is formed. As a result, the impurity layer 11. .
１３１によりＮ型のソース領域１４が形成され、かつ不
純物層１１＊ １１３ＭによりＮ型のドレイン領域１５
が形成される（第２図（ｄ）図示）。131 forms an N-type source region 14, and the impurity layer 11*113M forms an N-type drain region 15.
is formed (as shown in FIG. 2(d)).
しかる後、前記残存ｃｖｎｓｔｏｔ膜１２′を除去しテ
ＭＯ５ｆｆｌ ）ランジスタを製造する（第２図（ｅ）
図ボ）。ナオ、前記残存ＣＶＤ ８１０２ｇ ７２’は
必ずしも除去する必＊はない。また、前記製造方法では
浅いＮ型の不純物層１１．．１１２を先に形成したが、
逆にゲート電極７、ゲート絶縁膜６及びフィールド酸化
膜４の側壁に残存ＣＶＤ５ＩＯ，膜１２′を残して先に
深いＮ型の不純物＋＠１３１，１３．を形成し、しかる
後残存ＣＶＤ５ｉＯ，膜１２′を除去して深いＮ型の不
純物層７３．、ＪＪ、を形成してもよい。しかしながら
、前述の如く製造される第２図（ｅ）のＭＯ８型トラン
ジスタによれば、ショートチャネル効果及びパンチスル
ーな改善できるものの、深さの異なる不純物層を形成す
るために２度のイオン打込を必要とし、第１図のＭＯ８
型トランジスタと比べてプロセスが複雑となり、コスト
高を招く。Thereafter, the remaining CVNSTO film 12' is removed and a transistor is manufactured (FIG. 2(e)).
figure). Nao, the remaining CVD 8102g 72' does not necessarily have to be removed. Further, in the above manufacturing method, the shallow N-type impurity layer 11. ．． 112 was formed first, but
Conversely, deep N-type impurities +@131, 13. is formed, and then the remaining CVD 5iO film 12' is removed to form a deep N-type impurity layer 73. , JJ, may be formed. However, according to the MO8 type transistor of FIG. 2(e) manufactured as described above, although the short channel effect and punch-through can be improved, two ion implantations are required to form impurity layers with different depths. MO8 in Figure 1 is required.
Compared to conventional transistors, the process is more complicated, leading to higher costs.
本発明は、上記事情に鑑みてなされたもので、ショート
チャネル効果、パンチスルー現象を抑制するとともに、
プロセスを簡略化してコスト低減をなし得る半導体装置
の製造方法を提供することを目的とするものでおる。The present invention has been made in view of the above circumstances, and suppresses the short channel effect and punch-through phenomenon, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can simplify the process and reduce costs.
本発明は、第１導電型の半導体基板の素子領域上に絶縁
膜を介してゲート電極材料層を堆積した後、このゲート
電極材料層上にマスク材を形成し、しかる後このマスク
材を用いてゲート電極材料層を選択的に除去し、ゲート
電極を形成し、更に同マスク材を用いて絶縁膜を反応性
イオンエツチングによｐ選択的に除去しゲート絶縁膜を
形成し、つづいてマスク材を除去後イオン注入を施すこ
とによって、例えばＬＤＤ構造のＭＯＢ型トランジスタ
を形成し、ショートチャネル効果、パンチスルー現象を
抑制するとともに、コスト低減化を図ったことを骨子と
する。The present invention involves depositing a gate electrode material layer on an element region of a first conductivity type semiconductor substrate via an insulating film, forming a mask material on the gate electrode material layer, and then using this mask material. The gate electrode material layer is selectively removed to form a gate electrode, and the insulating film is selectively removed by reactive ion etching using the same mask material to form a gate insulating film. By performing ion implantation after removing the material, a MOB type transistor with, for example, an LDD structure is formed, and the main idea is to suppress short channel effects and punch-through phenomena, and to reduce costs.
以下、本発明をＬ Ｄ Ｄ構造を有したＭＯ８型トラン
ジスタに適用した場合について第３図（ａ）〜（ｄ）を
参照して説明する。Hereinafter, a case where the present invention is applied to an MO8 type transistor having an LDD structure will be described with reference to FIGS. 3(a) to 3(d).
〔１〕 まず、半導体基板としてのＰＭのＳｉ基板２ノ
土にフィールド酸化膜２２を形成した後、このフィール
ド酸化膜２２で囲まれた基板２１上に酸化膜２３を形成
した。つづいて、全面にケート電極材料層としてのリン
ドープ多結晶シリコン層２４を形成した（第３図（ａ）
図示鬼次いで、この多結晶シリコン層２４上にレジスト
パターン２５を形成した。更に、このレジストパターン
２６をマスクとしてリンドープ多結晶シリコン層２４を
化学ドライエツチング（ＣＤＩ）法で選択的にエツチン
グ除去μゲート電極２６を形成した（第３図（ｂ）図示
）。[1] First, a field oxide film 22 was formed on a PM Si substrate 2 serving as a semiconductor substrate, and then an oxide film 23 was formed on the substrate 21 surrounded by the field oxide film 22. Subsequently, a phosphorus-doped polycrystalline silicon layer 24 was formed as a cathode electrode material layer on the entire surface (Fig. 3(a)).
As shown in the figure, a resist pattern 25 was then formed on this polycrystalline silicon layer 24. Furthermore, using this resist pattern 26 as a mask, the phosphorus-doped polycrystalline silicon layer 24 was selectively etched away by chemical dry etching (CDI) to form a μ gate electrode 26 (as shown in FIG. 3(b)).
なお、同図（ｂ）において、リンドープ多結晶シリコン
層２４のサイドエッチ量ｄｏ、リンドープ多結晶シリコ
ン層２４の膜厚とほぼ同じ厚さにした。ここで、サイド
エッチ量ｄｉ、ＣＤＥ法によるエツチング量をませば大
きくなり、逆に途中までＲＩＥ法でエツチングし、残シ
をＣＤＥ法でエツチングすれば小さくなシ、適宜調整す
ることが可能である。In addition, in FIG. 2B, the side etching amount do of the phosphorus-doped polycrystalline silicon layer 24 was set to be approximately the same as the film thickness of the phosphorus-doped polycrystalline silicon layer 24. Here, the side etching amount di can be increased by reducing the etching amount by the CDE method, or conversely can be decreased by etching halfway by the RIE method and etching the remaining portion by the CDE method, so it can be adjusted as appropriate. .
叩 次に、前記レジストパターン２５をマスクとして前
記酸化膜２３をＲＩＥにて選択的にエツチング除去し、
ゲート絶縁膜２６を形成した。つづいて、レジストパタ
ーン２５を除去し７ｊ（第３図（ｃ）図示）。次いで、
前記ゲート電極２６、ゲート絶縁膜２７及びフィールド
酸化膜２２をマスクとして基板２１に例えば砒素をイオ
ン注し、熱処理を施した。この結果、ゲート電極２６近
傍が低濃度で浅く、かつ遠ざかる部分が高濃度で深いＮ
型のソース、ドレイン領域２８．１１９が自己整合的に
形成され、ＭＯ８ｍ）ランジスタが形成された（第３図
（ｄ）図示）。Next, using the resist pattern 25 as a mask, the oxide film 23 is selectively etched away by RIE,
A gate insulating film 26 was formed. Subsequently, the resist pattern 25 is removed 7j (as shown in FIG. 3(c)). Then,
Using the gate electrode 26, gate insulating film 27, and field oxide film 22 as masks, ions of, for example, arsenic were implanted into the substrate 21, and heat treatment was performed. As a result, the N region near the gate electrode 26 is low-concentration and shallow, and the part farther away is high-concentration and deep N.
The source and drain regions 28 and 119 of the type were formed in a self-aligned manner, and an MO8m) transistor was formed (as shown in FIG. 3(d)).
しかして、本発明によれば、第３図（ｂ）に示す如く、
レジストパターン２５をマスクとしリンドープ多結晶シ
リコン層２４をＣＤＥ法で選択的にエツチング除去し、
ゲート電極２６を形成した後、第３図（ｅ）に示す如く
、同レジストパターン２５をマスクとして酸化膜２３を
ＲＩＥにて選択的にエツチング除去し、ゲート絶縁膜２
７を形成するため、ゲート電極２６の幅はゲート絶縁膜
２７のそれと比べ狭くなる。従って、これらゲート電極
２６、ゲート絶縁Ｍ２７及びフィールド酸化膜２２をマ
スクとしてＳｔ基板２１に砒素をイオン注入することに
より、ゲート電極２６近傍が低濃度で浅くかつ遠ざかる
部分が高濃度で深いＮ型のソース、ドレイン領域２８゜
２９を自己整合的に形成でき、従来と比ベニ程を簡略化
してコスト低減を図ることができるとトモに、ショート
チャネル効果、パンチスルー現象を抑制できる。According to the present invention, as shown in FIG. 3(b),
Using the resist pattern 25 as a mask, the phosphorus-doped polycrystalline silicon layer 24 is selectively etched away using the CDE method.
After forming the gate electrode 26, as shown in FIG. 3(e), the oxide film 23 is selectively etched away by RIE using the same resist pattern 25 as a mask to form the gate insulating film 2.
7, the width of the gate electrode 26 is narrower than that of the gate insulating film 27. Therefore, by ion-implanting arsenic into the St substrate 21 using the gate electrode 26, gate insulator M27, and field oxide film 22 as masks, the vicinity of the gate electrode 26 becomes shallow with a low concentration, and the part farther away becomes a deep N-type with a high concentration. If the source and drain regions 28 and 29 can be formed in a self-aligned manner, and the cost can be reduced by simplifying the process compared to the conventional method, short channel effects and punch-through phenomena can be suppressed.
ｔｆｃ、第３図（ｄ）に示す如く、ゲート絶縁膜２７を
ゲート電極２６の真下のみならず、その周辺にも残存さ
せるため、ゲート電極２６とソース、ドレイン領域２８
．２９との耐圧を、通常のＭＯＳプロセスよりも向上で
きるとともに、後工程における酸化処理を省略できる。tfc, as shown in FIG. 3(d), in order to leave the gate insulating film 27 not only directly under the gate electrode 26 but also around it, the gate electrode 26 and the source and drain regions 28 are
．． The breakdown voltage with respect to No. 29 can be improved compared to the normal MOS process, and the oxidation treatment in the post-process can be omitted.
従って、トランジスタのソース、ドレイン領域２Ｂ、ｉ
！９接合のシャロー化をはかれ、微細化に適している。Therefore, the source and drain regions 2B,i of the transistor
! 9 junctions are made shallower, making it suitable for miniaturization.
なお、上記実施例ではマスク材としてレジストパターン
を用いたが、これに限らない。Note that in the above embodiments, a resist pattern is used as the mask material, but the present invention is not limited to this.
以上詳述した如く、本発明によれば、ショートチャネル
効果、パンチスルー現象を抑制するとともに、プロセス
を簡略化してコスト低減をなし得るＬＤＤ構造のＭＯ８
型トランジスタ等の半導体装置を製造する方法を提供で
きるものである。As described in detail above, according to the present invention, the MO8 of the LDD structure can suppress the short channel effect and punch-through phenomenon, and also simplify the process and reduce costs.
The present invention can provide a method for manufacturing semiconductor devices such as type transistors.
第１図は従来のＭＯ８型トランジスタの断面図、第２図
（ａ）〜（ｅ） Ｕ従来の他のＭＯ８型トランジスタの
製造方法を工程順に示す断面図、第３図（ａ）〜（ｄ）
は本発明の一実施例に係るＭＯ８型トランジスタの製造
方法を工程順に示す断面図である。
２１・・・Ｐ型の８１基板（半導体基板）、２２・・・
フィールド酸化膜、２３・・・酸化膜、２４・・・リン
ドープ多結晶シリコン層（ゲート［極材料（社）、２５
・・・レジストハターン、２６・・・ゲート電極、２７
・・・Ｎ型のソース領域、２８・・・Ｎ型のドレイン領
域。
出願人代理人 弁理士 鈴 江 武 彦第１図
第２図
第 ２ 図
第３図
４FIG. 1 is a cross-sectional view of a conventional MO8 type transistor, FIG. )
1A and 1B are cross-sectional views illustrating a method for manufacturing an MO8 type transistor according to an embodiment of the present invention in order of steps. 21... P-type 81 substrate (semiconductor substrate), 22...
Field oxide film, 23... Oxide film, 24... Phosphorus-doped polycrystalline silicon layer (gate [Kiyoku Materials Co., Ltd., 25
...Resist pattern, 26...Gate electrode, 27
. . . N-type source region, 28 . . . N-type drain region. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 2 Figure 3 Figure 4
Claims (1)
ゲート電極材料層を堆積する工程と、このゲート電極材
料層上にマスク材を形成する工程と、このマスク材を用
いてゲート電極材料層を選択的に除去しゲート電極を形
成する工程と、同マスク材を用いて前記絶縁膜を反応性
イオンエツチングにより選択的に除去しゲート絶縁膜な
形成する工程と、前記マスク材を除去後イオン注入を施
す工程と乞具備することを特徴とする半導体装置の製造
方法。A step of depositing a gate electrode material layer on the element region of a first conductivity type semiconductor substrate via an insulating film, a step of forming a mask material on this gate electrode material layer, and a step of forming a gate electrode material layer using this mask material. a step of selectively removing a material layer to form a gate electrode; a step of selectively removing the insulating film by reactive ion etching using the same mask material to form a gate insulating film; and removing the mask material. A method for manufacturing a semiconductor device, comprising a step of performing post-ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16366883A JPS6055665A (en) | 1983-09-06 | 1983-09-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16366883A JPS6055665A (en) | 1983-09-06 | 1983-09-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6055665A true JPS6055665A (en) | 1985-03-30 |
Family
ID=15778316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16366883A Pending JPS6055665A (en) | 1983-09-06 | 1983-09-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6055665A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4702000A (en) * | 1986-03-19 | 1987-10-27 | Harris Corporation | Technique for elimination of polysilicon stringers in direct moat field oxide structure |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US4978626A (en) * | 1988-09-02 | 1990-12-18 | Motorola, Inc. | LDD transistor process having doping sensitive endpoint etching |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| JPH0555573A (en) * | 1991-08-26 | 1993-03-05 | Sharp Corp | Thin film transistor and manufacture thereof |
| JPH06120249A (en) * | 1991-12-24 | 1994-04-28 | Semiconductor Energy Lab Co Ltd | Manufacture of mos transistor and structure thereof |
| US5619045A (en) * | 1993-11-05 | 1997-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor |
| US5648277A (en) * | 1993-11-05 | 1997-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US5736414A (en) * | 1994-07-14 | 1998-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6867431B2 (en) * | 1993-09-20 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| KR100469147B1 (en) * | 1997-12-29 | 2005-04-06 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
-
1983
- 1983-09-06 JP JP16366883A patent/JPS6055665A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4702000A (en) * | 1986-03-19 | 1987-10-27 | Harris Corporation | Technique for elimination of polysilicon stringers in direct moat field oxide structure |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4978626A (en) * | 1988-09-02 | 1990-12-18 | Motorola, Inc. | LDD transistor process having doping sensitive endpoint etching |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| US6555843B1 (en) | 1991-05-16 | 2003-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JPH0555573A (en) * | 1991-08-26 | 1993-03-05 | Sharp Corp | Thin film transistor and manufacture thereof |
| US7821011B2 (en) | 1991-08-26 | 2010-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect semiconductor devices and method of manufacturing the same |
| US6331723B1 (en) | 1991-08-26 | 2001-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device having at least two transistors having LDD region in one pixel |
| US7087962B1 (en) | 1991-12-24 | 2006-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a MOS transistor having lightly dopped drain regions and structure thereof |
| JPH06120249A (en) * | 1991-12-24 | 1994-04-28 | Semiconductor Energy Lab Co Ltd | Manufacture of mos transistor and structure thereof |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| US6867431B2 (en) * | 1993-09-20 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6617612B2 (en) * | 1993-11-05 | 2003-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and a semiconductor integrated circuit |
| US6475839B2 (en) | 1993-11-05 | 2002-11-05 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing of TFT device by backside laser irradiation |
| US6218678B1 (en) | 1993-11-05 | 2001-04-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US5648277A (en) * | 1993-11-05 | 1997-07-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US5619045A (en) * | 1993-11-05 | 1997-04-08 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor |
| US5736414A (en) * | 1994-07-14 | 1998-04-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| KR100469147B1 (en) * | 1997-12-29 | 2005-04-06 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
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