JPS61147564A - Integrated circuit with complementary field effect transistor - Google Patents
Integrated circuit with complementary field effect transistorInfo
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- JPS61147564A JPS61147564A JP59270175A JP27017584A JPS61147564A JP S61147564 A JPS61147564 A JP S61147564A JP 59270175 A JP59270175 A JP 59270175A JP 27017584 A JP27017584 A JP 27017584A JP S61147564 A JPS61147564 A JP S61147564A
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- 230000005669 field effect Effects 0.000 title claims description 16
- 230000000295 complement effect Effects 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 abstract description 22
- 239000012535 impurity Substances 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 15
- 230000003321 amplification Effects 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- -1 boron ion Chemical class 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、耐ランチアンプ性が優れた相補型電界効果ト
ランジスタを有する集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit having complementary field effect transistors with excellent launch amplifier resistance.
pチャネルMO8−FET(絶縁ゲート型電界効果トラ
ンジスタ)とnチャネルMO8−FETとを同一チップ
内に作り、相補動作させるようにしたC−MOS−FE
Tは、低消費電力で動作するという特長を有する反面、
入出力部分からの雑音や電源電圧の変動がトリガーにな
って、電源ラインに過剰電流が流れ、最悪の場合、デバ
イスの破壊を招くラッチアンプ現象が生じやすいという
短所を有する。このような現象はデバイスが微小化し、
高集積化するほど顕著になる。A C-MOS-FE in which a p-channel MO8-FET (insulated gate field effect transistor) and an n-channel MO8-FET are fabricated on the same chip so that they operate complementary to each other.
Although T has the feature of operating with low power consumption,
Noise from the input/output section or fluctuations in the power supply voltage can act as a trigger, causing excessive current to flow through the power supply line, and in the worst case, the latch amplifier phenomenon tends to occur, which can destroy the device. This phenomenon occurs as devices become smaller and
The higher the integration, the more noticeable this becomes.
次に、C−MOS−FETを示す第4図、及びその等価
回路を示す第5図によってラッチアップ現象を説明する
。第4図において、n基板11)の右半分の領域1cp
チヤネルのMOS−FETを構成するためにp型ソース
領域(2)とp型ドレイン領域(3)とが設けられ、こ
れ等の間の絶縁層(4)の上にゲート電極(5)が設け
られている。一方、基板(11の左半分には、nチャネ
ルMO8−FETを構成するために、一般にウェルと呼
ばれるp型島状領域(6)の中Kn型ソース領域(7)
とn型ドレイン領域(8)とが設けられ、これ等の間の
絶縁層(9)の上にゲート電極α〔が設けられている。Next, the latch-up phenomenon will be explained with reference to FIG. 4 showing a C-MOS-FET and FIG. 5 showing its equivalent circuit. In FIG. 4, a region 1cp on the right half of the n-substrate 11)
A p-type source region (2) and a p-type drain region (3) are provided to configure a channel MOS-FET, and a gate electrode (5) is provided on an insulating layer (4) between them. It is being On the other hand, in the left half of the substrate (11), in order to configure an n-channel MO8-FET, there is a Kn-type source region (7) inside a p-type island region (6) generally called a well.
and an n-type drain region (8), and a gate electrode [alpha] is provided on an insulating layer (9) between them.
なお、上記の主要構成部分の他に、p型ソース領域(2
)を基板(1)に接続するためのn型領域Qυ、ゲート
電極(5)aQが接続され+
るp屋領域(12、nuソース領域(7)をp凰島状領
域(6)K接続するためのp型領域13、ゲート電極a
l111が接続されるn型領域Iが設けられている。ま
た、2つのドレイン領域(31(8)が共通の出力端子
Vanテにそれぞれ接続され、2つのゲート電極(5)
αIが共通の入力端子v夏Nにそれぞれ接続されp型ソ
ース領域(2)が電源端子Voo K接続され、n型ソ
ース領域(7)とp型領域a3とがそれぞれ接地されて
いる。In addition to the main components mentioned above, a p-type source region (2
) to the substrate (1), the p-type region (12) to which the gate electrode (5) aQ is connected, the nu source region (7) to the p-shaped region (6) K connection p-type region 13 and gate electrode a for
An n-type region I is provided to which l111 is connected. In addition, two drain regions (31 (8) are connected to a common output terminal Vante, respectively, and two gate electrodes (5)
αI are respectively connected to the common input terminal VXN, the p-type source region (2) is connected to the power supply terminal VooK, and the n-type source region (7) and the p-type region a3 are each grounded.
第4図の装置は、2つのMOS−FETを含む外に、等
価的に示す6個の寄生トランジスタTr。The device in FIG. 4 includes two MOS-FETs and six parasitic transistors Tr, which are equivalently shown.
〜Tr6及び抵抗Rn5ub 、 Rpwellを含む
。第5図は第4図の寄生トランジスタTr+ % Tr
aの等価回路であり、ラッチアップ現象に関係するp盤
ソース領域(2)とn)基板(1)とp型島状領域(6
)とn型ソース領域(力とから成る寄生サイリスタを主
体に描いたものである。寄生サイリスタは、第5図で太
線で示す部分で構成され、等価的に2つのトランジスタ
Trl 、Tr6を含む。この寄生サイリスクのアノー
ド電流工^は次式で表わされる。~Tr6 and resistors Rn5ub and Rpwell are included. Figure 5 shows the parasitic transistor Tr+ % Tr in Figure 4.
This is an equivalent circuit of a, which is related to the latch-up phenomenon, and includes a p-board source region (2), a substrate (1), and a p-type island region (6).
) and an n-type source region (power).The parasitic thyristor is composed of the part indicated by the thick line in FIG. 5, and equivalently includes two transistors Trl and Tr6. The anode current of this parasitic silicon risk is expressed by the following equation.
但し、β2′はトランジスタTrtの実効エミッタ゛α
′
接地電流増幅率を示し、β2′二□−〇、である〇この
式のαfは、次式で示される。However, β2' is the effective emitter ゛α of the transistor Trt.
′ represents the ground current amplification factor, which is β2′2□−〇〇 αf in this equation is expressed by the following equation.
偽’:= cx、−m−
1+ Rat /Rnswb 、、、、、、、 (2
1(但し、α!はトランジスタTryのベース接地電流
増幅率、R−はトランジスタTryのエミッタ抵抗、R
n s ubはトランジスタTr=のベース抵抗である
。)β6′はトランジスタTr6の実効エミッタ接地電
流α6
増幅率を示し、11a’=−一一である。この式のαら
−aIj
は次式で示される。False':= cx, -m- 1+ Rat /Rnswb , , , , , (2
1 (However, α! is the common base current amplification factor of the transistor Try, R- is the emitter resistance of the transistor Try, R
n s ub is the base resistance of the transistor Tr=. ) β6' represents the effective emitter ground current α6 amplification factor of the transistor Tr6, and 11a'=-11. α et −aIj in this equation is expressed by the following equation.
αe
αら工□、、、、、、、 (3)
1+RII6 / Rpwell
(但シ、α、はトランジスタTr6のベース接地電流増
幅率、 RI!6はトランジスタTraのエミッタ抵抗
、RpwellはトランジスタTr6のベース抵抗であ
る。αe α et al. (3) 1+RII6 / Rpwell (However, α is the common base current amplification factor of transistor Tr6, RI!6 is the emitter resistance of transistor Tra, and Rpwell is the base of transistor Tr6. It is resistance.
(11式から寄生サイリスタがターンオンつまりラッチ
アップする条件は次式で示される。(From Equation 11, the conditions for the parasitic thyristor to turn on or latch up are shown by the following equation.
β2′βl≧1 、、、、、、、14)従って、ラッ
チアップを防止するためには次式を満足するようにC−
MOS−FETを構成する必珈がある。β2′βl≧1 , , , , , 14) Therefore, in order to prevent latch-up, C-
There is a necessity for configuring a MOS-FET.
β2′βa’ (i 、、、、。、i51なお、R1
2、Rx6 が無視できる場合には、(5)式は次式と
なる。β2′βa′ (i , , , ., i51 Note that R1
2. If Rx6 can be ignored, equation (5) becomes the following equation.
β2β6〈1 ・・・・・・・(6)
従って、ラッチアップ耐性を上げるために、次の3つの
方法が考えられる。β2β6<1 (6) Therefore, the following three methods can be considered to increase the latch-up resistance.
(1)R冨!、R冨6 を大きくする。(1) R-tomi! , increase R-toe6.
(21Rn5ub 、 Rpwe 11を小さくする。(Reduce 21Rn5ub, Rpwe 11.
(3) α鵞、α6あるいは^、β6を小さくする。(3) Reduce α, α6 or ^, β6.
しかし、上記tl+の方法によれば、電圧降下が大きく
なり、ノイズマージンが狭くなるので得策でない。従っ
て、(2)又は(3)の方法が採用されている。However, according to the above tl+ method, the voltage drop becomes large and the noise margin becomes narrow, which is not a good idea. Therefore, method (2) or (3) is adopted.
次に、上記+21 (31の従来の具体的方法及びその
問題点について述べる。Next, a specific conventional method of +21 (31) and its problems will be described.
第1<、p型島状領域(6)の拡散の深さを大きく“す
ることによってβを小さくする方法がある。一般に島状
領域(6)は、半導体基板+13の表面にボロン、イオ
y(B+)を注入し、熱処理を行うことによって形成さ
れるので、島状領域(6)の不純物分布は深さ方向に濃
度が減少する分布を示し、深さを大にすれば、寄生トラ
ンジスタTr6のβを小さくすることが出来る。しかし
、深い拡散を行うと、島状領域(6)の横方向の拡がり
が必然的に生じ、高集積化の妨げとなる。There is a method of reducing β by increasing the depth of diffusion of the p-type island region (6).Generally, the island region (6) is made of boron, ions, etc. on the surface of the semiconductor substrate +13. Since it is formed by implanting (B+) and performing heat treatment, the impurity distribution of the island region (6) shows a distribution in which the concentration decreases in the depth direction, and if the depth is increased, the parasitic transistor Tr6 However, deep diffusion inevitably causes the island region (6) to expand in the lateral direction, which hinders high integration.
第2に、pチャネルのソース・ドレインとp11島状領
域の間の距離を大きくする方法がある。しかし、この距
離を150゛μm以上にすることが要求され、微小化の
妨げになる。A second method is to increase the distance between the p-channel source/drain and the p11 island region. However, this distance is required to be 150 μm or more, which hinders miniaturization.
第3にp型島状領域(6)及びpテヤネA/MO8−F
ETをn層でそれぞれ囲み、Rn s ubを小さくす
る方法がある。しかし、この場合もn層の分だけ微小化
が妨げられる。Third, p-type island region (6) and p-Teyane A/MO8-F
There is a method to reduce Rn sub by surrounding each ET with n layers. However, in this case as well, miniaturization is hindered by the n-layer.
第4に、n型領域aυとp型ンース領域(2)、及び+
p型領域a3とn!ソース領域(7)の位置及び大きさ
を工夫してRn5ub 、 Rpwellを小さくする
方法がある。しかし、微小化を妨げずに実施することは
困難である。Fourth, the n-type region aυ and the p-type second region (2), and the +p-type region a3 and n! There is a method of reducing Rn5ub and Rpwell by changing the position and size of the source region (7). However, it is difficult to implement this without hindering miniaturization.
第5に、SOS (シリコンオンサフイヤ)基板を用い
、p型島状領域(6)の囲りを絶縁物で分離する方法が
ある。この方法は、ラッチアップ対策として最も理想的
であるが、SO8基板を用いるためにコストアップにつ
ながる。A fifth method is to use an SOS (silicon on sapphire) substrate and isolate the area surrounding the p-type island region (6) with an insulator. This method is the most ideal as a countermeasure against latch-up, but because it uses an SO8 substrate, it leads to an increase in cost.
第6に、金拡散あるいは中性子投射によって少数キャリ
アのライフタイムを小さくし、寄生トランジスタのβを
小さくする方法がある。しかし、この方法は、接合リー
ク電流が増大するという欠点をもつ。Sixthly, there is a method of reducing the lifetime of minority carriers by gold diffusion or neutron projection to reduce β of the parasitic transistor. However, this method has the disadvantage that junction leakage current increases.
第7に、カウンタイオン注入法により、p型島状領域(
6)の深い部分の一度を大きくし、n p n Trの
βとRpwe l Iを小さくする方法がある。この方
法では、例えばボロンイオンBを101t〜11013
C″′″2注入し、1200C1数時間熱処理を施し、
次に、リンイオンpを10 lICm−” カウンタ注
入し、1200C,1〜2時間熱処理をし、所望のしき
い値電圧が得られる不純物分布とする。しかし、この方
法では、イオン注入法を用℃・るために島状領域(6)
の高濃度化に限界がある。また、2回の熱処理が行われ
るために島状領域(6)の横方向の拡がりが生じ、高集
積化が妨げられる。Seventh, a p-type island region (
6) There is a method of increasing the angle of the deep part and decreasing β of n p n Tr and Rpwe l I. In this method, for example, boron ion B is 101t to 11013
Injected C''''2, heat treated at 1200C for several hours,
Next, phosphorus ions p are injected at a rate of 10 lICm-'' and heat treated at 1200C for 1 to 2 hours to obtain an impurity distribution that provides the desired threshold voltage.However, in this method, the ion implantation method is not used.・Island area (6)
There is a limit to the high concentration of Furthermore, since the heat treatment is performed twice, the island-like regions (6) expand in the lateral direction, which impedes high integration.
第8に、pチャネルMO8−FETのp型ドレイン領域
あるいはゲート接続用p型領域と、n型基板と、nチャ
ネルMO8−FETのためのp型島状領域とで構成され
るpnp寄生トランジスタのベース領域(nll基板)
Kpm層をpm島状領域と同一工程で設ける方法がある
。しかし、エミッタとして働くpチャネルMO8−FE
Tのp型ドレイン領域あるいはゲート接続用p型領域か
ら注入されたキャリアがこれ等の下部から回り込んでp
型島状領域に到達するものもあり、耐ラツチアツプ性を
大幅に向上させることはできない。Eighth, the pnp parasitic transistor is composed of the p-type drain region of the p-channel MO8-FET or the p-type region for gate connection, the n-type substrate, and the p-type island region for the n-channel MO8-FET. Base area (NLL substrate)
There is a method of providing the Kpm layer and the PM island region in the same process. However, p-channel MO8-FE acting as emitter
Carriers injected from the p-type drain region of the T or the p-type region for gate connection wrap around from below and form the p-type region.
Some of them reach the mold island-like regions, and it is not possible to significantly improve the latch-up resistance.
そこで、本発明の目的は、耐ランチアップ性及び集積度
の向上が可能な相補型電界効果トランジスタを有する集
積回路を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an integrated circuit having complementary field effect transistors that can improve launch-up resistance and integration density.
上記目的を達成するための本発明は、一方の導−電型の
半導体基体領域と、前記基体領域の中に形成された一方
の導電型の島状領域と、前記基体領域の中に形成された
他方の導電型の島状領域と、前記一方の導電型の島状領
域の中に形成された他方の導電型チャネルの絶縁ゲート
電界効果トランジスタと、前記他方の導電型の島状領域
の中に形成され且つ前記他方の導電型チャネルの絶縁ゲ
ート電界効果トランジスタと相補動作するように接続さ
れた一方の導電型チャネルの絶縁ゲート電界効果トラン
ジスタと、前記一方の導電型の島状領域の側部および下
部に設けられた他方の導電型層とを含んでいることを特
徴とする相補型絶縁ゲート電界効果トランジスタを有す
る集積回路に係わるものである。To achieve the above object, the present invention includes a semiconductor substrate region of one conductivity type, an island region of one conductivity type formed in the base region, and a semiconductor substrate region of one conductivity type formed in the base region. an insulated gate field effect transistor with a channel of the other conductivity type formed in the island region of the other conductivity type, and an island region of the other conductivity type formed in the island region of the other conductivity type; an insulated gate field effect transistor of one conductivity type channel formed in and connected to operate complementary to the insulated gate field effect transistor of the other conductivity type channel; and a side portion of the island region of the one conductivity type. and a layer of the other conductivity type provided below.
上述の如く構成すれば、他方の導電型チャネルの絶縁ゲ
ート電界効果トランジスタのドレイン領域がエミッタ、
一方の導電型の島状領域がベース、本発明に従って設け
られた一方の導電型の島状領域の側部および下部に設け
られた他方の導電型層がコレクタとなる寄生トランジス
タが生じる。このため、不測の電圧によりエミッタから
注入されたキャリアは、本発明に従って設けられた側部
の他方の導電層のみでな(、下部の他方の導電層でも吸
収され、他方の導電型の島状領域に到達するキャリアが
少な(なる。従って、他方の導電型チャネルの絶縁ゲー
ト電界効果トランジスタのドレイン領域をエミッタ、一
方の導電型チャネルの絶縁ゲート電界効果トランジスタ
が設けられている島状領域をコレクタとする寄生トラン
ジスタのエミッタ接地電流増幅率を小さくすることがで
き、耐ラツチアツプ性を大きく向上させることができる
。With the above configuration, the drain region of the insulated gate field effect transistor of the channel of the other conductivity type is the emitter,
A parasitic transistor is generated in which the island region of one conductivity type serves as the base and the layer of the other conductivity type provided on the sides and bottom of the island region of one conductivity type provided according to the present invention serves as the collector. Therefore, carriers injected from the emitter due to an unexpected voltage are absorbed not only in the other conductive layer on the side provided according to the present invention (but also in the other conductive layer at the bottom), and are absorbed in the island-like form of the other conductivity type. Therefore, the drain region of the insulated gate field effect transistor of the other conductivity type channel is used as the emitter, and the island-shaped region in which the insulated gate field effect transistor of one conductivity type channel is provided is used as the collector. The common emitter current amplification factor of the parasitic transistor can be reduced, and the latch-up resistance can be greatly improved.
〔実施例1〕
次に、第1図を参照して本発明の実施例1に係わる相補
型絶縁ゲート電界効果トランジスタ(以下、C−MOS
−FETと呼ぶ)及びその製造方法について述べる。[Example 1] Next, referring to FIG. 1, a complementary insulated gate field effect transistor (hereinafter referred to as C-MOS) according to Example 1 of the present invention will be described.
- FET) and its manufacturing method will be described.
まず、第1図囚に示すように、約3 X 10″cm”
’の濃度をもつn型(一方の導電型)シリコン半導体基
板(2υに酸化膜を形成し、レジストをマスクとして、
pチャネルおよびnチャネルのMOS−FET形成予定
部に、イオン注入法によりボロンを加速エネルギー約9
0 keV、ドーズ量約2XIO”cm−”で打ち込み
、p型(他方の導電型)不純物層を形成し、11501
:’、30時間程度の熱処理を施して拡散し、島状領域
のおよび(ハ)を形成する。First, as shown in Figure 1, approximately 3 x 10"cm"
An oxide film is formed on an n-type (one conductivity type) silicon semiconductor substrate (2υ) with a concentration of ', and a resist is used as a mask.
Boron is accelerated by ion implantation into the areas where p-channel and n-channel MOS-FETs are to be formed at an energy of approximately 9
A p-type (the other conductivity type) impurity layer was formed by implanting at 0 keV and a dose of approximately 2XIO cm-, and the 11501
:', Heat treatment is performed for about 30 hours to diffuse and form island-like regions and (c).
更に、前記p型島状領域g3には、第1図の)の如(、
この領域に囲まれるように、レジストをマスクとして、
イオン注入法によりリンを加速エネルギー約100ke
V、 ドーズ量1.2 X l O”cm−”で打ち
込み、再び1150C,16時間程度の熱処理を施して
拡散し、n型島状領域(2)を形成する。これにより、
第1図囚に示すp型島状領域(ハ)は第1図(5)に示
す如くn型島状領域(2)を取り囲むp型不純物層Q9
となる。Furthermore, in the p-type island region g3, as shown in FIG.
Use the resist as a mask so that it is surrounded by this area.
Accelerating phosphorus with energy of approximately 100 ke using ion implantation method
V, implanted at a dose of 1.2 X l O cm - , and heat treated again at 1150 C for about 16 hours to diffuse and form n-type island regions (2). This results in
The p-type island region (c) shown in FIG. 1 is a p-type impurity layer Q9 surrounding the n-type island region (2) as shown in FIG.
becomes.
次に、p型層(ハ)に囲まれたn型島状領域CI!41
にpチャネルMO8−FETを形成し、p型島状領域(
221K nチャネルMO8−FETを形成し、C−M
OS−FETを完成させる。即ち、第1図(C)に示−
すよ5に、p型層C251K囲まれたn型島状領域(2
41の中には、p型ドレイン領域(ハ)と、p型ソース
領域(2)と、このソース領域(2)をn型島状領域c
!4に接続するためのn型領域(ハ)と、ゲート接続用
p型領域(至)とを選択拡散で形成し、p型島状領域四
の中には、n型ソース領域(至)と、n型ドレイン領域
0υと、ソース接続用p型領域r33と、ゲート接続用
n型領域(至)とを選択拡散で形成する。また、ゲート
絶縁層no51をpチャネルおよびnチャネルの上にそ
れぞれ設け、この上にポリシリコングー)(36)03
ηを設げる。更に酸化物層(41、配線導体0υ、およ
び酸化物層(4zを設ける。n型島状領域(財)を囲む
p型不純物層(至)にはp型領域(至)を選択拡散で形
成し、ここをVssに接続し、p型層(ハ)とp型島状
領域四との間のnW基板Qυにはn型領域(至)を選択
拡散で形成し、ここをVDDに接続する。なお、これ以
外の各半導体領域に対する配線およびゲートに対する配
線は第4図と同一になされている。Next, the n-type island region CI! surrounded by the p-type layer (c)! 41
A p-channel MO8-FET is formed in the p-type island region (
221K n-channel MO8-FET is formed, C-M
Complete the OS-FET. That is, as shown in FIG.
In side 5, there is an n-type island region (2) surrounded by the p-type layer C251K.
41 includes a p-type drain region (c), a p-type source region (2), and an n-type island region c.
! An n-type region (c) for connecting to 4 and a p-type region (to) for gate connection are formed by selective diffusion, and an n-type source region (to) is formed in p-type island region 4. , an n-type drain region 0υ, a p-type region r33 for source connection, and an n-type region (to) for gate connection are formed by selective diffusion. In addition, a gate insulating layer no51 is provided on each of the p channel and n channel, and a polysilicon layer (36) 03
Set η. Furthermore, an oxide layer (41), a wiring conductor 0υ, and an oxide layer (4z) are provided.A p-type region (41) is formed by selective diffusion in the p-type impurity layer (41) surrounding the n-type island region (42). Then, connect this to VSS, form an n-type region (to) on the nW substrate Qυ between the p-type layer (c) and p-type island region 4 by selective diffusion, and connect this to VDD. Note that the wiring for each semiconductor region other than this and the wiring for the gate are the same as in FIG.
この相補型電界効果トランジスタの出力端子Vootあ
るいは入力端子v!翼に十分大きな正の外来雑音電圧が
印加された場合、pチャネルMO8−FETの、p型ド
レイン領域翰あるいはゲート接続用p 型領域(至)を
エミッタとし、n型島状領域Q41をベースとし、これ
を取り囲むp型層(ハ)をコレクタとする、pnp寄生
トランジスタのベース・エミッタ間は順バイアスとなり
、エミッタからホールが注入されるが、n型島状領域c
!滲をとり囲むp型層(ハ)とn型基板Qυとの間の電
場のため、p型島状領域圏に到達するホールはと(わず
かであり、多くはn型島状領域(財)を取り囲むp型層
(ハ)K吸収される。本実施例ではエミッタとして働く
p型ドレイン領域(ハ)及びゲート接続用p型領域(2
糧の下部にもp型層(ハ)が設けられているので、従来
技術で述べた第8の方法に比べ、ホールの吸収効率は非
常に大きい。従って、エミッタ接地の電流増幅率βを非
常に小さくすることができ、耐ラッチアンプ性を大きく
することができる。The output terminal Voot or the input terminal v! of this complementary field effect transistor. When a sufficiently large positive external noise voltage is applied to the wing, the p-type drain region of the p-channel MO8-FET or the p-type region for gate connection is used as the emitter, and the n-type island region Q41 is used as the base. , the pnp parasitic transistor whose collector is the p-type layer (c) surrounding it becomes a forward bias between the base and emitter, and holes are injected from the emitter, but the n-type island region c
! Due to the electric field between the p-type layer (c) surrounding the diode and the n-type substrate Qυ, the number of holes that reach the p-type island region is small (few, and most of them are n-type island region (material)). K is absorbed by the p-type layer (c) surrounding the p-type layer (c).
Since the p-type layer (c) is also provided at the bottom of the layer, the hole absorption efficiency is much higher than in the eighth method described in the prior art. Therefore, the current amplification factor β of the common emitter can be made very small, and the latch amplifier resistance can be increased.
〔実施例2〕
第2図は本発明の実施例2に係わるc−mos−FET
を示す。このC−MOS−FETを製造する際には、ま
ず、第2図(4)に示す如(、約1×10” cm−”
の濃度を有するp型シリコン半導体基板5υに酸化膜を
形成し、左側のnチャネルMO8−FET形成予定部に
、レジストをマスクとしてイオン注入法によりヒ素を、
加速エネルギー約50keV、 ドーズ量的2.5
X 1012cm−2で打ち込み、n型層5りを形成す
る。[Example 2] Figure 2 shows a c-mos-FET according to Example 2 of the present invention.
shows. When manufacturing this C-MOS-FET, first, as shown in FIG.
An oxide film is formed on a p-type silicon semiconductor substrate 5υ having a concentration of
Acceleration energy approximately 50 keV, dose 2.5
Implant at x 1012 cm-2 to form an n-type layer 5.
次に、SiH4と BF、を使いエピタキシャル成長法
により、基板61)上に約6μmの厚さで約2゜5x1
0”cm’の不純物濃度をもつpmエピタキシャル成成
長層上形成する。再びレジストをマスクとして、pチャ
ネル形成予定部および前記n型層(52の上部に、第2
図(6)に示すように、イオン注入法によりリンを加速
エネルギー約100 keV、ドーズ量的I X I
O” cm−”で打ち込み、n型層f:1i41を形成
する。更に、l 10011;、14時間程度の熱処理
を施し、第2図(C) K示すように拡散する。この時
、n型層52の不純物が拡散定数の小さいヒ素であるた
め、この層曽の拡散による広がりは小さい。Next, by epitaxial growth using SiH4 and BF, a 2°5
A second layer is formed on the pm epitaxial growth layer having an impurity concentration of 0"cm'. Using the resist as a mask again, a second
As shown in Figure (6), the ion implantation method accelerates phosphorus with an energy of about 100 keV and a dose of I
An n-type layer f:1i41 is formed by implanting at O''cm-''. Further, heat treatment is performed for about 14 hours, and the film is diffused as shown in FIG. 2(C). At this time, since the impurity in the n-type layer 52 is arsenic, which has a small diffusion constant, the spread of this layer due to diffusion is small.
次に、n型層r53の上のp型エピタキシャル成長層に
nチャネルMOS −F E Tを形成し、n型領域(
財)の中にpチャネルMO8−FETを形成し、C−M
O5−FETを完成させる。即ち、第2図0に示すよう
に、n型島状領域64)の中には、p型ドレイン領域(
至)と、p型ソース領域6?)と、ソースをnu島状領
域(財)K接続するためのn型領域鏝と、ゲート接続用
p型領域6!1とを選択拡散で形成し、n型層5々とn
型層(ト)K囲まれたp型エピタキシャル成長層曽には
、n型2−、ス領域−と、n型ドレイン領域旬と、ソー
ス接続用p型領域旬と、ゲート接続用n型領域(へ)と
を選択拡散で形成する。また、ゲート絶縁層(661(
6ηをpチャネルおよびnチャネルの上にそれぞれ設け
、この上にポリシリコングー)(68(61を設ける。Next, an n-channel MOS-FET is formed in the p-type epitaxial growth layer on the n-type layer r53, and the n-type region (
A p-channel MO8-FET is formed in the C-M
Complete O5-FET. That is, as shown in FIG. 2, there is a p-type drain region (
) and p-type source region 6? ), an n-type region for connecting the source to the nu island region K, and a p-type region for gate connection 6!1 are formed by selective diffusion, and the n-type layer 5 and n
The p-type epitaxial growth layer surrounded by the type layer (G) includes an n-type region, an n-type drain region, a p-type region for source connection, and an n-type region for gate connection ( ) is formed by selective diffusion. In addition, the gate insulating layer (661(
6η is provided on each of the p-channel and n-channel, and a polysilicon layer 68 (61) is provided on this.
更K、酸化物層σ〔、配線導体(ill)、酸化物層σ
りを設ける。nチャネルMO8−FETの外側のn型不
純物層印ICn型領域(財)を選択拡散で形成し、ここ
にvDDヲ接続し、これとn屋島状領域64Jとの間の
p型エピタキシャル成長層十
にp型領域霞を選択拡散で形成し、ここにVssを接続
する。これ以外の各半導体領域に対する配線およびゲー
トに対する配線は第4図と同一になされている。Furthermore, K, oxide layer σ [, wiring conductor (ill), oxide layer σ]
Establishment of rules. An n-type impurity layer (ICn-type region) outside the n-channel MO8-FET is formed by selective diffusion, vDD is connected thereto, and a p-type epitaxial growth layer is formed between this and the n-shaped region 64J. A p-type region haze is formed by selective diffusion, and Vss is connected thereto. The wiring for the other semiconductor regions and the wiring for the gate are the same as those in FIG. 4.
この第2図のC−MO8−FETは第1図のC−MO8
−FETと極性が逆である点を除いて同様な作用効果を
有する。即ち、寄生トランジスタにおいてエミッタとし
て働くn型ドレイン領域61)及びゲート接続用n型領
域−から電子が注入されるが、この下部にもコレクタと
して働くn型層(5つが設けられているので、ここで電
子が吸収され、右側のn型層64)に電子はほとんど到
達せず、実施例1と同様に耐ラツチアツプ性を向上させ
ることができる。This C-MO8-FET in Fig. 2 is the C-MO8-FET in Fig. 1.
- It has the same effect as the FET except that the polarity is opposite. That is, electrons are injected from the n-type drain region 61) which acts as an emitter in the parasitic transistor and the n-type region for gate connection. The electrons are absorbed by the layer 64), and almost no electrons reach the n-type layer 64) on the right side, so that the latch-up resistance can be improved as in the first embodiment.
〔実施例3〕
第3図は本発明の実施例3に係わるC−MO5−FET
を示す。このC−MO8−FETを製造する際には、ま
ず、第3図(4)に示すように、約3X 10” Cm
−5の濃度をもつp型シリコン半導体基板侶υ上に、s
iH4と P Hsを使いエピタキシャル成長法によ
り、約5 amの厚さで約3.2 X 10” cm−
’の不純物濃度をもつn型シリコンエピタキシャル成長
層(83を形成する。次に酸化膜を形成し、レジストを
マスクとしてイオン注入法によりボロンを加速エネルギ
ー約90 keV、ドーズ量的lXl0”cm−”
で打ち込み、1150C,18時間程度の熱拡散処理を
施し、第3図(B)に示すようにplL層關全形成する
。[Example 3] Figure 3 shows a C-MO5-FET according to Example 3 of the present invention.
shows. When manufacturing this C-MO8-FET, first, as shown in FIG. 3 (4), approximately 3X 10" Cm
On a p-type silicon semiconductor substrate υ with a concentration of -5, s
By epitaxial growth using iH4 and PHs, it is about 3.2 x 10” cm- with a thickness of about 5 am.
An n-type silicon epitaxial growth layer (83) is formed with an impurity concentration of
A heat diffusion treatment is performed at 1150 C for about 18 hours to completely form the PIL layer as shown in FIG. 3(B).
次に、nチャネルMO8−FET形成予定部にレジスト
をマスクとしてイオン注入法によりボロンを加速エネル
ギー約90 key、ドーズ量的2X10”cm−2で
打ち込み、1150C,5時間程度の熱処理を施し、第
3図(Qに示す如くp型島状領域(財)を形成する。Next, using the resist as a mask, boron was implanted into the area where the n-channel MO8-FET was to be formed using an ion implantation method with an acceleration energy of approximately 90 keys and a dose of 2X10"cm-2, followed by heat treatment at 1150C for approximately 5 hours. As shown in Fig. 3 (Q), a p-type island region is formed.
次に、p型層(ハ)に囲まれたn型エピタキシャル層(
ハ)にpチャネルMO8−FETを形成し、p型島状領
域(財)にnチャネルMO8−FETを形成し、C−M
OS−FETを完成する。即ち、第3図■に示すように
、p型層−に囲まれたn型領域(へ)には、p型ソース
領域(へ)と、p型ドレイン領域鈴ηと、+
ンースをn型領域(へ)に接続するためのn型領域(至
)−と、ゲート接続用p型領域翰とを選択拡散で形成し
、pH島状領域(財)の中には、nWソース領域翰と、
n型ドレイン領域のりと、ソース接続用p型領域@と、
ゲート接続用n型領域(93とを選択拡散で形成する。Next, an n-type epitaxial layer (
A p-channel MO8-FET is formed in C), an n-channel MO8-FET is formed in the p-type island region, and C-M
Complete the OS-FET. That is, as shown in FIG. An n-type region for connecting to the region and a p-type region for gate connection are formed by selective diffusion, and an nW source region and an nW source region are formed in the pH island region. ,
N-type drain region glue, p-type region for source connection @,
An n-type region for gate connection (93) is formed by selective diffusion.
また、ゲート絶縁層−(ト)をpチャネルおよびnチャ
ネルの上にそれぞれ設け、この上にポリシリコンゲー)
M(97)を設ける。更に酸化物層(9)、配線導体(
101)、および酸化物層(102)を設ける。n型領
域(へ)を囲むp型層−にはp型領域鏝を選択拡散で形
成し、これをVssに接続し、これとp型島状領域との
間のn型エビタキクヤル層(8’ZJに+
はn型領域国を選択拡散で形成し、これをVDDに接続
する。なお、これ以外の各半導体領域に対する配線およ
びゲートに対する配線は第4図と同一になされている。In addition, a gate insulating layer (T) is provided on the p channel and the n channel, respectively, and a polysilicon gate layer is placed on top of this.
M (97) is provided. Furthermore, an oxide layer (9), a wiring conductor (
101), and an oxide layer (102). A p-type region is formed in the p-type layer surrounding the n-type region by selective diffusion, connected to Vss, and an n-type layer (8' In ZJ, an n-type region is formed by selective diffusion and connected to VDD.The wiring for each semiconductor region other than this and the wiring for the gate are the same as in FIG.
この第3図のC−MOS−FETは、寄生トランジスタ
のエミッタとして働<pmドレイン領域@η及びゲート
接続用p型領域−の下部にコレクタとして働くp型基板
[F]υを有するので、エミッタから注入されたホール
がコ°レクタとして働く側面のp型層曽のみならず下部
のpm基板[F]υでも吸収され、左側のp型島状領域
(財)にほとんど達しなくなる。従って、実施例1と同
様な作用効果が得られる。The C-MOS-FET shown in FIG. 3 has a p-type substrate [F]υ that serves as a collector under the <pm drain region @η and the p-type region for gate connection, which serves as the emitter of the parasitic transistor. Holes injected from the substrate are absorbed not only by the side p-type layer acting as a collector but also by the lower PM substrate [F]υ, and hardly reach the left p-type island region. Therefore, the same effects as in Example 1 can be obtained.
本発明は上述の実施例1〜3に限定されるものではなく
、例えば、次の変形例が可能なものである。The present invention is not limited to the first to third embodiments described above, and, for example, the following modifications are possible.
(a) 実施例1において、基板Cυをp型とし、こ
とKn型島状領域、p型島状領域、p型島状領域を取り
囲むn厘層を形成する場合にも適用可能である。(a) In Example 1, the present invention can also be applied to the case where the substrate Cυ is of p type and an n-type island region, a p-type island region, and an n-layer surrounding the p-type island region are formed.
(b) ソース領域帽1又はl57)−又は@6)翰
、ドレイン領域c!e C31)又は田6υ又は[F]
η0υ以外の領域は必要に応じて増減しても差支えない
。例えば、フィールド反転防止層を設けてもよい。(b) Source region cap 1 or l57) - or @6) 翰, drain region c! e C31) or 6υ or [F]
Areas other than η0υ may be increased or decreased as necessary. For example, a field inversion prevention layer may be provided.
(c) 多結晶シリコンゲート(ト)Gη又は鏝[F
]■又は翰(資)を、AIゲート、シリコンゲート等に
する場合にも適用可能である。(c) Polycrystalline silicon gate (G) or trowel [F
] ■It is also applicable to the case where a wire (material) is made into an AI gate, a silicon gate, etc.
(d) 実施例2において、n型不純物層印と、埋め
込みn型不純物層曽とは必ずしも両側で重なり合ってな
くてもよい。どちらか一方の側で重なり合つ【いても、
両方の側ではなれていてもよい。(d) In Example 2, the n-type impurity layer mark and the buried n-type impurity layer mark do not necessarily have to overlap on both sides. Even if they overlap on either side,
They can be separated on both sides.
(e) 実施例2におい【、基板15υをn型として
もよい。(e) In the second embodiment, the substrate 15υ may be of n-type.
(f) 実施例2Vcおいて、エピタキシャル成長層
−をn型としてここにp型島状領域、p型埋め込み層、
p型不純物層を形成する場合にも適用可能である。(f) In Example 2Vc, the epitaxial growth layer is of n-type, and here a p-type island region, a p-type buried layer,
It is also applicable when forming a p-type impurity layer.
(g) 実施例3において、基板侶υをnWとして、
ここKp型エピタキシャル層、p型不純物層、p型島状
領域を形成する場合にも適用可能である。(g) In Example 3, the substrate size υ is nW,
It is also applicable to the case of forming a Kp type epitaxial layer, a p type impurity layer, and a p type island region.
上述から明らかな如く、一方の導電型の島状領域の側部
のみならず、下部にも他方の導電型層を設けたので、寄
生トランジスタ作用で注入されたキャリアがここでも吸
収され、他方の導電型の島状領域にほとんど到達しなく
なる。従って、C−MOS−FETの耐ランチアップ性
を大幅に向上させることが出来る。As is clear from the above, since the layer of the other conductivity type is provided not only on the sides of the island-like region of one conductivity type but also under the other conductivity type, carriers injected by the parasitic transistor action are absorbed here as well, and are absorbed by the other conductivity type. Almost no conductive type island regions are reached. Therefore, the launch-up resistance of the C-MOS-FET can be greatly improved.
第1図は本発明の実施例IC係わるC−MOS−FET
を製造工程順に示す断面図、
第2図は本発明の実施例21C係わるC−MOS−FE
Tを製造工程順に示す断面図、
第3図は本発明の実施例3に係わるC−MOS−FET
を製造工程順に示す断面図、
第4図は従来のC−MOS−FETを示す断面図、
第5図は第1図のC−MOS−FETの等価回路図であ
る。
CI)・・・基板、@・・・p型島状領域、(財)・・
・n型島状領域、(ハ)・・・pm不純物層、(イ)・
・・p型ドレイン領域、■・・・p型ドレイン領域、(
至)・・・n型ソース領域、6η+
・・・n型ドレイン領域、Cl6)07)・・・ゲート
。Figure 1 shows a C-MOS-FET related to an embodiment IC of the present invention.
FIG. 2 is a cross-sectional view showing a C-MOS-FE according to Example 21C of the present invention in the order of manufacturing steps.
3 is a sectional view showing T in the order of manufacturing steps, and FIG. 3 is a C-MOS-FET according to Example 3 of the present invention.
FIG. 4 is a cross-sectional view showing a conventional C-MOS-FET, and FIG. 5 is an equivalent circuit diagram of the C-MOS-FET shown in FIG. 1. CI)...Substrate, @...p-type island region, Foundation...
・N-type island region, (c)...PM impurity layer, (b)・
...p-type drain region, ■...p-type drain region, (
to)...n-type source region, 6η+...n-type drain region, Cl6)07)...gate.
Claims (1)
と、 前記基体領域の中に形成された他方の導電型の島状領域
と、 前記一方の導電型の島状領域の中に形成された他方の導
電型チャネルの絶縁ゲート電界効果トランジスタと、 前記他方の導電型の島状領域の中に形成され且つ前記他
方の導電型チャネルの絶縁ゲート電界効果トランジスタ
と相補動作するように接続された一方の導電型チャネル
の絶縁ゲート電界効果トランジスタと、 前記一方の導電型の島状領域の側部および下部に設けら
れた他方の導電型層と を含んでいることを特徴とする相補型絶縁ゲート電界効
果トランジスタを有する集積回路。(1) A semiconductor substrate region of one conductivity type, an island region of one conductivity type formed within the base region, and an island region of the other conductivity type formed within the base region. , an insulated gate field effect transistor with a channel of the other conductivity type formed in the island region of the one conductivity type, and a channel of the other conductivity type formed in the island region of the other conductivity type. an insulated gate field effect transistor of one conductivity type channel connected for complementary operation with an insulated gate field effect transistor of the other conductivity type provided on the side and under the island region of the one conductivity type; 1. An integrated circuit having a complementary insulated gate field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59270175A JPS61147564A (en) | 1984-12-21 | 1984-12-21 | Integrated circuit with complementary field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59270175A JPS61147564A (en) | 1984-12-21 | 1984-12-21 | Integrated circuit with complementary field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61147564A true JPS61147564A (en) | 1986-07-05 |
Family
ID=17482568
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59270175A Pending JPS61147564A (en) | 1984-12-21 | 1984-12-21 | Integrated circuit with complementary field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61147564A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244876A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Complementary mis type semiconductor device and manufacture thereof |
JPH0415955A (en) * | 1990-05-09 | 1992-01-21 | Mitsubishi Electric Corp | Manufacture of input circuit of semiconductor device |
JPH06314773A (en) * | 1993-03-03 | 1994-11-08 | Nec Corp | Semiconductor device |
US6043522A (en) * | 1997-10-06 | 2000-03-28 | Mitsubishi Electric System Lsi Design Corporation | Field effect transistor array including doped two-cell isolation region for preventing latchup |
JP2006165056A (en) * | 2004-12-02 | 2006-06-22 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
JP2014011336A (en) * | 2012-06-29 | 2014-01-20 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method of the same |
JP2014027111A (en) * | 2012-07-26 | 2014-02-06 | Fujitsu Semiconductor Ltd | Semiconductor device and driving method of the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
JPS58158961A (en) * | 1982-03-17 | 1983-09-21 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS58196045A (en) * | 1982-05-11 | 1983-11-15 | Toshiba Corp | Complementary mos semiconductor device |
JPS59110153A (en) * | 1982-12-15 | 1984-06-26 | Fujitsu Ltd | Complementary mis field effect semiconductor device |
-
1984
- 1984-12-21 JP JP59270175A patent/JPS61147564A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
JPS58158961A (en) * | 1982-03-17 | 1983-09-21 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS58196045A (en) * | 1982-05-11 | 1983-11-15 | Toshiba Corp | Complementary mos semiconductor device |
JPS59110153A (en) * | 1982-12-15 | 1984-06-26 | Fujitsu Ltd | Complementary mis field effect semiconductor device |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244876A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Complementary mis type semiconductor device and manufacture thereof |
JPH0415955A (en) * | 1990-05-09 | 1992-01-21 | Mitsubishi Electric Corp | Manufacture of input circuit of semiconductor device |
JPH06314773A (en) * | 1993-03-03 | 1994-11-08 | Nec Corp | Semiconductor device |
US6043522A (en) * | 1997-10-06 | 2000-03-28 | Mitsubishi Electric System Lsi Design Corporation | Field effect transistor array including doped two-cell isolation region for preventing latchup |
JP2006165056A (en) * | 2004-12-02 | 2006-06-22 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
JP4530823B2 (en) * | 2004-12-02 | 2010-08-25 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
US7999327B2 (en) | 2004-12-02 | 2011-08-16 | Sanyo Electric Co., Ltd. | Semiconductor device, and semiconductor manufacturing method |
JP2014011336A (en) * | 2012-06-29 | 2014-01-20 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method of the same |
JP2014027111A (en) * | 2012-07-26 | 2014-02-06 | Fujitsu Semiconductor Ltd | Semiconductor device and driving method of the same |
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