JP2000058823A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000058823A JP2000058823A JP10229081A JP22908198A JP2000058823A JP 2000058823 A JP2000058823 A JP 2000058823A JP 10229081 A JP10229081 A JP 10229081A JP 22908198 A JP22908198 A JP 22908198A JP 2000058823 A JP2000058823 A JP 2000058823A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- base impurity
- trench
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000010354 integration Effects 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、素子分離用溝部を
有する半導体装置およびその製造方法に係わり、特に、
パワーＭＯＳ−ＦＥＴ／ＩＧＢＴに用いられるトレンチ
ゲート型半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench for element isolation and a method of manufacturing the same.
The present invention relates to a trench gate type semiconductor device used for a power MOS-FET / IGBT and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】トランジスタなどの半導体装置を、微細
加工技術により高密度に集積させた高集積回路におい
て、さらなる高集積化および高い駆動能力が求められて
いる。2. Description of the Related Art In a highly integrated circuit in which semiconductor devices such as transistors are integrated at a high density by a fine processing technique, higher integration and higher driving capability are required.
【０００３】近年、中でも注目されているのがトレンチ
（溝）を有する半導体装置である。ゲートをトレンチ構
造にすると、基板上のゲート部分の占有面積を狭くする
ことができ、その結果電流値の大きな、性能の良い高集
積化回路が実現される。In recent years, a semiconductor device having a trench (groove) has attracted particular attention. When the gate has a trench structure, the area occupied by the gate on the substrate can be reduced, and as a result, a highly integrated circuit with a large current value and high performance can be realized.
【０００４】このトレンチゲート構造を有するパワーＭ
ＯＳ−ＦＥＴおよびＩＧＢＴ等の半導体装置は、１００
Ｖ以下の低耐圧デバイスのオン抵抗を改善するために用
いられている。パターニング技術やエッチング技術の進
歩に伴い、最小線幅が０．５から１μｍに縮小され、そ
れがそのままトレンチ幅（ゲート幅）になっており、ト
レンチゲート間のセルピッチも４から８μｍとプレーナ
型では達成できなかった集積度が可能となっている。The power M having the trench gate structure
Semiconductor devices such as OS-FET and IGBT are 100
It is used to improve the on-resistance of a low breakdown voltage device of V or less. With the progress of patterning technology and etching technology, the minimum line width has been reduced from 0.5 to 1 μm, which has become the trench width (gate width) as it is, and the cell pitch between the trench gates is 4 to 8 μm. The degree of integration that could not be achieved is now possible.
【０００５】しかし、このようなセルピッチの縮小に伴
い、キャリア抜きに要するベース不純物高濃度領域幅が
縮小し、ベース不純物高濃度領域でキャリアが集中する
ことにより、Ｌ負荷耐量、すなわち外部回路における破
壊耐量、あるいは熱放散によるダメージのパラメータで
あるラッチアップ耐量が低減してしまう。このように、
トレンチ幅がたとえ０．５μｍ以下に縮小できたとして
も、トレンチ−トレンチ間距離の縮小には限界がある。However, as the cell pitch is reduced, the width of the high-concentration region of the base impurity required for carrier removal is reduced, and carriers are concentrated in the high-concentration region of the base impurity. The resistance or the latch-up resistance, which is a parameter of damage due to heat dissipation, is reduced. in this way,
Even if the trench width can be reduced to 0.5 μm or less, there is a limit in reducing the distance between trenches.
【０００６】従来のトレンチゲート構造を採用したＮチ
ャネル型パワーＭＯＳ−ＦＥＴのストライプパターンの
断面図を図５に、平面図を図６に、オフセットメッシュ
パターンを図７に示す。これらの図から明らかな通り、
トレンチ−トレンチ間には高濃度不純物（Ｐ＋）拡散領
域であるベース不純物高濃度領域が必ず形成されてい
る。FIG. 5 is a sectional view of a stripe pattern of an N-channel power MOS-FET employing a conventional trench gate structure, FIG. 6 is a plan view, and FIG. 7 is an offset mesh pattern. As is clear from these figures,
A base impurity high concentration region, which is a high concentration impurity (P + ) diffusion region, is always formed between the trenches.
【０００７】従来のＮチャネル型パワーＭＯＳ−ＦＥＴ
の製造工程を図８に示す。Conventional N-channel type power MOS-FET
8 is shown in FIG.
【０００８】まず、図８（ａ）に示す通り、Ｎ＋型シリ
コン基板１上にＮ−型エピタキシャル層２とＰ型ベース
領域３を形成して、その上にマスクを介してホウ素等の
イオンを注入して所定の位置にＰ＋不純物高濃度拡散領
域４を形成する。First, as shown in FIG. 8A, an N − type epitaxial layer 2 and a P type base region 3 are formed on an N + type silicon substrate 1, and ions of boron or the like are formed thereon via a mask. Is implanted to form a P + impurity high concentration diffusion region 4 at a predetermined position.
【０００９】次に、図８（ｂ）に示す通り、不純物高濃
度拡散領域４の間に砒素、りん等のイオンを注入してＮ
＋ソース領域５を形成する。Next, as shown in FIG. 8B, ions of arsenic, phosphorus or the like are implanted between the high impurity concentration diffusion regions 4 to form N.
+ Source region 5 is formed.
【００１０】そして、図８（ｃ）に示すように、Ｎ＋ソ
ース領域５を貫くようにしてトレンチ６をＣｌ2 ／ＣＨ
Ｆ3 等のガスを用いた反応性イオンエッチング（ＲＩ
Ｅ）により形成する。Then, as shown in FIG. 8C, a trench 6 is formed so as to penetrate the N + source region 5 with Cl 2 / CH.
Reactive ion etching using F 3, etc. of the gas (RI
E).
【００１１】さらに、図８（ｄ）に示すように、トレン
チ６にゲート絶縁膜７を積層した後、ゲート電極８を埋
め込んで平坦化処理を施し、層間絶縁膜９を堆積する。Further, as shown in FIG. 8D, after laminating a gate insulating film 7 in the trench 6, a gate electrode 8 is buried and a flattening process is performed, and an interlayer insulating film 9 is deposited.
【００１２】さらに、図８（ｅ）に示すように、層間絶
縁膜９をＣＦ4 ／Ｈ2 等のガスを用いたＲＩＥにより加
工した後、ソース電極１０を全面に堆積させて半導体装
置とする。Further, as shown in FIG. 8E, after processing the interlayer insulating film 9 by RIE using a gas such as CF 4 / H 2 , a source electrode 10 is deposited on the entire surface to obtain a semiconductor device. .
【００１３】図５〜８から明らかな通り、トレンチ−ト
レンチ間（セルピッチ）には高濃度不純物高濃度拡散領
域４およびソース領域５があるために、セルピッチには
一定の距離が必要となる。また、セルピッチを無理に縮
小させると、ベース不純物高濃度領域でキャリアが集中
してしまい、破壊耐量が低下してしまう。As is apparent from FIGS. 5 to 8, since a high-concentration impurity high-concentration diffusion region 4 and a source region 5 exist between trenches (cell pitch), a certain distance is required for the cell pitch. If the cell pitch is forcibly reduced, carriers are concentrated in the high-concentration region of the base impurity, and the breakdown strength is reduced.
【００１４】[0014]
【発明が解決しようとする課題】上述した通り、トレン
チ幅の縮小に伴って、トレンチ−トレンチ間距離を狭め
ると、ベース不純物高濃度領域でキャリアが集中するこ
とにより破壊耐量が低下してしまうという問題があっ
た。As described above, when the trench-to-trench distance is reduced as the trench width is reduced, the concentration of carriers in the high-concentration region of the base impurity lowers the breakdown strength. There was a problem.
【００１５】従って、本発明の目的は、セルピッチを狭
めて高集積化を図りながら、破壊耐量を低減させること
のないトレンチ構造を有する半導体装置およびその製造
方法を提供することである。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device having a trench structure which does not reduce breakdown strength while narrowing the cell pitch and achieving high integration, and a method of manufacturing the same.
【００１６】[0016]
【課題を解決するための手段】本発明の半導体装置は、
複数の素子分離用溝部が形成された半導体基板と、前記
半導体基板上に形成されたゲート絶縁膜と、前記ゲート
絶縁膜上に形成された導電層と具備する半導体装置であ
って、前記複数の素子分離用溝部の溝部間領域にはベー
ス不純物高濃度領域が形成されている領域と前記ベース
不純物高濃度領域が形成されていない領域があることを
特徴としている。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising: a semiconductor substrate having a plurality of element isolation trenches formed therein; a gate insulating film formed on the semiconductor substrate; and a conductive layer formed on the gate insulating film. The region between the trenches of the element isolation trench includes a region where the base impurity high concentration region is formed and a region where the base impurity high concentration region is not formed.
【００１７】本発明の半導体装置において、前記ベース
不純物高濃度領域が形成されていない前記溝部間領域の
幅は、前記ベース不純物高濃度領域が形成されている前
記溝部間領域の幅よりも小さいことを特徴としている。
また、前記ベース不純物高濃度領域は、ＩＣチップの少
なくとも５％、好ましくは５〜１０％、より好ましくは
１０〜１５％となるように形成することを特徴としてい
る。In the semiconductor device of the present invention, the width of the inter-groove region where the base impurity high concentration region is not formed is smaller than the width of the inter-groove region where the base impurity high concentration region is formed. It is characterized by.
Further, the base impurity high concentration region is formed so as to be at least 5%, preferably 5 to 10%, more preferably 10 to 15% of the IC chip.
【００１８】本発明の半導体装置の製造方法は、半導体
基板上の所定の位置にベース不純物高濃度領域を形成す
る工程と、少なくとも前記ベース不純物高濃度領域以外
に複数の素子分離用溝部を形成する工程と、前記溝部の
形成された半導体基板上にゲート絶縁膜を形成する工程
と、前記ゲート絶縁膜の形成された前記溝部にゲート電
極を埋め込む工程と、前記ゲート電極を埋め込んだ前記
溝部を少なくとも覆うように層間絶縁膜を堆積する工程
と、前記半導体基板、前記ベース不純物高濃度領域およ
び前記層間絶縁膜上を覆うようにソース電極を堆積する
工程とを少なくとも具備する半導体装置の製造方法であ
って、前記複数の素子分離用溝部の溝部間領域にはベー
ス不純物高濃度領域が形成されている領域と前記ベース
不純物高濃度領域が形成されていない領域があることを
特徴としている。According to the method of manufacturing a semiconductor device of the present invention, a step of forming a base impurity high-concentration region at a predetermined position on a semiconductor substrate, and forming a plurality of element isolation trenches at least other than the base impurity high-concentration region. A step of forming a gate insulating film on the semiconductor substrate on which the groove is formed, a step of embedding a gate electrode in the groove on which the gate insulating film is formed, and at least the step of embedding the gate electrode. A method of manufacturing a semiconductor device, comprising: at least a step of depositing an interlayer insulating film so as to cover; and a step of depositing a source electrode so as to cover the semiconductor substrate, the base impurity-rich region and the interlayer insulating film. A region in which a high-concentration base impurity region is formed in the inter-groove region of the plurality of isolation trenches; It is characterized in that there is is not formed region.
【００１９】本発明の半導体装置の製造方法において、
前記ベース不純物高濃度領域が形成されていない前記溝
部間領域の幅は、前記ベース不純物高濃度領域が形成さ
れている前記溝部間領域の幅よりも小さいことを特徴と
している。また、前記ベース不純物高濃度領域は、ＩＣ
チップの少なくとも５％、好ましくは５〜１０％、より
好ましくは１０〜１５％となるように形成することを特
徴としている。In the method of manufacturing a semiconductor device according to the present invention,
A width of the inter-groove region where the base impurity high concentration region is not formed is smaller than a width of the inter-groove region where the base impurity high concentration region is formed. Further, the high-concentration base impurity region includes an IC
It is characterized in that it is formed so as to be at least 5%, preferably 5 to 10%, more preferably 10 to 15% of the chip.
【００２０】すなわち、本発明は、トレンチゲート構造
を有するパワーＭＯＳ−ＦＥＴあるいはＩＧＢＴにおい
て、ソースあるいはエミッタ電極とベース不純物高濃度
領域であるＰ＋領域が存在するセル（トレンチ−トレン
チ間領域）と存在しないセルとに分け、ベース不純物高
濃度領域の存在するセルを周期的に配置するものであ
る。ベース不純物高濃度領域の存在しないセルの幅を狭
くすることができ、これにより微細化が促進される。こ
のように、本発明によれば、破壊耐量を減少することな
く、ＩＣチップ全体のチャネルの周囲長を増大してオン
電圧の低減を図ることができる。That is, the present invention relates to a power MOS-FET or IGBT having a trench gate structure, in which a cell (trench-trench region) in which a source or emitter electrode and a P + region which is a base impurity high concentration region exists. The cell in which the base impurity high concentration region exists is periodically arranged. The width of the cell where the base impurity high-concentration region does not exist can be reduced, thereby promoting miniaturization. As described above, according to the present invention, the on-voltage can be reduced by increasing the peripheral length of the channel of the entire IC chip without reducing the breakdown strength.
【００２１】本発明で用いる半導体基板は、例えば、シ
リコン、ＧａＡｓ、ＳｉＣ等であり、ゲート電極は、例
えば、ポリシリコン、ＢＰＳＧ（Boron Phospharus Sil
icate Glass ）、ＰＳＧ（Phospho Silicate Glass）メ
タル等であり、ゲート絶縁膜はシリコン酸化膜、ＣＶＤ
（Chemical Vapor Deposition ）窒化膜等、層間絶縁膜
はシリコン酸化膜、ＵＰＤ（Un-Doped Oxide）等、ソー
ス電極は、例えば、アルミニウム等である。The semiconductor substrate used in the present invention is, for example, silicon, GaAs, SiC or the like, and the gate electrode is, for example, polysilicon, BPSG (Boron Phospharus Silane).
icate Glass), PSG (Phospho Silicate Glass) metal, etc., and the gate insulating film is a silicon oxide film, CVD
(Chemical Vapor Deposition) An interlayer insulating film such as a nitride film is a silicon oxide film, an UPD (Un-Doped Oxide) or the like, and a source electrode is aluminum, for example.
【００２２】また、本発明は、ＭＯＳ−ＦＥＴばかりで
なく、半導体基板の裏面全面にｐ型層を形成したｎ型半
導体基板を用いればＩＧＢＴ（絶縁ゲート型バイポーラ
トランジスタ）にも適用することができる。The present invention can be applied not only to a MOS-FET but also to an IGBT (insulated gate bipolar transistor) if an n-type semiconductor substrate having a p-type layer formed on the entire back surface of the semiconductor substrate is used. .
【００２３】[0023]
【発明の実施の形態】［実施例１］本発明の半導体装置
の一例を、図１および２を用いて説明する。図１および
図２は、ストライプパターンを採用した本発明の半導体
装置の断面図と平面図である。[Embodiment 1] An example of a semiconductor device according to the present invention will be described with reference to FIGS. 1 and 2 are a sectional view and a plan view of a semiconductor device of the present invention employing a stripe pattern.
【００２４】図１を参照すると、Ｎ＋型シリコン基板１
上に堆積されたＮ−型エピタキシャル層２とＰ型ベース
領域３に、トレンチが形成されており、Ｐ＋不純物高濃
度拡散領域４とＮ＋ソース領域５の両領域が形成されて
いるトレンチ−トレンチ間領域と、Ｎ＋ソース領域５の
みが形成されているトレンチ−トレンチ間領域がある。
トレンチにはゲート絶縁膜７が堆積され、ゲート電極８
が中に埋め込まれ平坦化されている。ゲート電極８の上
に形成された層間絶縁膜９、Ｐ＋不純物高濃度拡散領域
４およびＮ＋ソース領域５を覆うようにソース電極１０
が堆積されている。Referring to FIG. 1, an N + type silicon substrate 1
A trench is formed in the N − -type epitaxial layer 2 and the P-type base region 3 deposited thereon, and a trench in which both the P + impurity high concentration diffusion region 4 and the N + source region 5 are formed. There is an inter-trench region and a trench-trench region in which only the N + source region 5 is formed.
A gate insulating film 7 is deposited in the trench, and a gate electrode 8
Are buried inside and flattened. The source electrode 10 covers the interlayer insulating film 9 formed on the gate electrode 8, the P + impurity high concentration diffusion region 4 and the N + source region 5.
Has been deposited.
【００２５】ベース不純物高濃度領域である不純物高濃
度拡散領域４のあるセル列は４列に１列しかないが、そ
の代わり、トレンチ−トレンチ間距離は他の３列に比べ
て広くとってある。不純物拡散領域のないセル列は、コ
ンタクトのパターニング技術やエッチング技術そしてソ
ース電極の埋め込み技術の許す限り狭くすることによっ
て全体の集積度を上げている。ただし、ベースが電気的
に浮いている状態を避けるため、半導体装置終端部の近
辺のみソース領域５のない領域を設け（図示せず）、ベ
ースをソース電極と接地させてある。Although there is only one cell row in every four rows having a high impurity concentration diffusion region 4 as a base impurity high concentration area, the trench-to-trench distance is set wider than the other three rows. . The cell array without the impurity diffusion region increases the overall integration by making the contact patterning technology, etching technology, and source electrode embedding technology as narrow as possible. However, in order to avoid the state where the base is electrically floating, a region without the source region 5 is provided only near the terminal portion of the semiconductor device (not shown), and the base is grounded to the source electrode.
【００２６】本実施例においては、ベース不純物高濃度
領域のあるセル列を４列に１列しか形成していないが、
半導体装置のＬ負荷耐量は、チップサイズに対するベー
ス不純物高濃度領域の割合を調整することで一定に保つ
ことができる。従って、微細度やチップサイズに応じて
トレンチ−トレンチ間のピッチやベース不純物高濃度領
域を含むセル列の周期を変えればよい。In this embodiment, although only one cell line having four base impurity concentration regions is formed in four columns,
The L load tolerance of the semiconductor device can be kept constant by adjusting the ratio of the base impurity high concentration region to the chip size. Therefore, the pitch between the trenches and the cycle of the cell row including the base impurity high-concentration region may be changed according to the fineness and the chip size.
【００２７】［実施例２］本発明の半導体装置の変形例
を図３を用いて説明する。図３は、オフセットメッシュ
パターンを適用した本発明の半導体装置の変形例の平面
図である。不純物高濃度拡散領域４のあるセルはトレン
チで区切っているのに対し、不純物高濃度拡散領域４の
ないセルはベースが電気的に浮かないように列方向はト
レンチで区切らず、１本の列内のセルが同電位に保たれ
るようにした以外は実施例１と同様である。また、これ
に限らず、列方向に揃ったメッシュパターンにも適用可
能である。Embodiment 2 A modification of the semiconductor device of the present invention will be described with reference to FIG. FIG. 3 is a plan view of a modified example of the semiconductor device of the present invention to which the offset mesh pattern is applied. A cell having the high impurity concentration diffusion region 4 is divided by a trench, whereas a cell having no high impurity concentration diffusion region 4 is not divided by a trench in the column direction so that the base does not float electrically. This is the same as the first embodiment except that the cells in the cells are kept at the same potential. Further, the present invention is not limited to this, and can be applied to a mesh pattern aligned in the column direction.
【００２８】［実施例３］本発明の半導体装置の製造方
法を図４を用いて説明する。Embodiment 3 A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
【００２９】まず、図４（ａ）に示す通り、Ｎ＋型シリ
コン基板１上にＮ−型エピタキシャル層２とＰ型ベース
領域３をそれぞれ５μｍと２μｍの厚さで、例えばエピ
層はエピタキシャル法で堆積、ベース領域はホウ素等の
イオンを４０〜６０ｋｅＶ、ドーズ量１〜５×１０13ｃ
ｍ-2の条件で打ち込み、１０００℃〜１１００℃の熱処
理にて拡散により形成し、その上にマスクを介してホウ
素等のイオンを、例えば、４０〜６０ｋｅＶの加速エネ
ルギー、ドーズ量１〜６×１０15ｃｍ-2の条件で注入し
て所定の位置にＰ＋不純物高濃度拡散領域４を形成す
る。このＰ＋不純物高濃度拡散領域４は、従来のように
各トレンチ−トレンチ間に設けずに、ＩＣチップ面積の
５％となるように疎らに形成する。これはマスクを変更
するだけで容易に制御できる。First, as shown in FIG. 4A, an N − type epitaxial layer 2 and a P type base region 3 are formed on an N + type silicon substrate 1 to a thickness of 5 μm and 2 μm, respectively. The base region is formed by depositing ions such as boron at 40 to 60 keV and at a dose of 1 to 5 × 10 13 c.
It is implanted under the condition of m −2 , and is formed by diffusion at a heat treatment at 1000 ° C. to 1100 ° C., and ions such as boron are further applied thereon through a mask by, for example, an acceleration energy of 40 to 60 keV and a dose of 1 to 6 ×. Implantation is performed under the condition of 10 15 cm -2 to form a P + impurity high concentration diffusion region 4 at a predetermined position. The P + impurity high concentration diffusion region 4 is not provided between the trenches as in the related art, but is formed sparsely so as to be 5% of the IC chip area. This can be easily controlled simply by changing the mask.
【００３０】次に、図４（ｂ）に示す通り、Ｐ＋不純物
高濃度拡散領域４の間に砒素、アンチモン、りん等のイ
オンを、例えば、４０〜５０ｋｅＶの加速エネルギー、
ドーズ量２〜５×１０15ｃｍ-2の条件で注入してＮ＋ソ
ース領域５を形成する。Next, as shown in FIG. 4B, ions of arsenic, antimony, phosphorus or the like are introduced between the P + impurity high concentration diffusion regions 4 by, for example, an acceleration energy of 40 to 50 keV,
The N + source region 5 is formed by implanting under a condition of a dose amount of 2 to 5 × 10 15 cm −2 .
【００３１】そして、図４（ｃ）に示すように、Ｎ＋ソ
ース領域５を貫くようにしてトレンチ６をＣｌ2 ／ＣＨ
Ｆ3 等のガスを用いた反応性イオンエッチング（ＲＩ
Ｅ）により形成する。トレンチの幅は約１μｍ、深さは
約３μｍとする。このとき、本発明によれば、従来とは
異なり、ソース領域のみしかないトレンチ−トレンチ間
も存在することになる。Then, as shown in FIG. 4C, a trench 6 is formed so as to penetrate the N + source region 5 with Cl 2 / CH.
Reactive ion etching using F 3, etc. of the gas (RI
E). The width of the trench is about 1 μm and the depth is about 3 μm. At this time, according to the present invention, unlike the related art, there is a trench-to-trench having only a source region.
【００３２】さらに、図４（ｄ）に示すように、トレン
チ６にゲート絶縁膜７を堆積した後、ゲート電極８を埋
め込んで平坦化処理を施し、層間絶縁膜９を堆積する。
この後、Ｔｉ、ＴｉＷ等のバリアメタルを堆積してもよ
い。Further, as shown in FIG. 4D, after depositing a gate insulating film 7 in the trench 6, a gate electrode 8 is buried and subjected to a flattening process, and an interlayer insulating film 9 is deposited.
Thereafter, a barrier metal such as Ti or TiW may be deposited.
【００３３】さらに、図４（ｅ）に示すように、層間絶
縁膜９をＣＦ4 ／Ｈ2 等のガスを用いたＲＩＥにより加
工した後、ソース電極１０を全面に堆積させて半導体装
置とする。Further, as shown in FIG. 4E, after processing the interlayer insulating film 9 by RIE using a gas such as CF 4 / H 2 , a source electrode 10 is deposited on the entire surface to obtain a semiconductor device. .
【００３４】以上、Ｎチャネル型について説明してきた
が、言うまでもなく、Ｐチャネル型についても同様に作
成できる。The N-channel type has been described above. Needless to say, the P-channel type can be similarly created.
【００３５】[0035]
【発明の効果】上述した通り、本発明によれば、ベース
不純物高濃度領域のあるセル列のみトレンチ−トレンチ
間距離を広げ、ベース不純物高濃度領域のないセル列の
距離をできるだけ狭めることでＩＣチップ全体の周囲長
を長くすることが可能となる。この際、ベース不純物高
濃度領域のあるセル列は必要以上に距離を広くとらなく
ても、ＩＣチップ面積に対するベース不純物高濃度領域
の総面積の割合を微細度やチップサイズに応じて調整す
ることで破壊耐量を維持することができる。As described above, according to the present invention, the distance between the trenches and the trenches is increased only in the cell row having the base impurity high concentration region, and the distance between the cell rows without the base impurity high concentration region is reduced as much as possible. It is possible to lengthen the perimeter of the entire chip. At this time, the ratio of the total area of the base impurity high-concentration region to the IC chip area is adjusted according to the fineness and the chip size, even if the cell row having the base impurity high-concentration region does not take an excessively large distance. With this, the breakdown strength can be maintained.
【００３６】また、たとえＩＣチップ当りのベース不純
物高濃度領域の総面積が同じであっても従来の等間隔ピ
ッチのセルに比べてセル当たりのコンタクト孔の面積が
大きい分、コンタクト孔でのキャリアの集中が緩和さ
れ、破壊耐量は大きくなるという効果を奏する。Even if the total area of the base impurity high-concentration region per IC chip is the same, the contact hole area per cell is larger than that of a conventional cell at a regular pitch. This has the effect of alleviating the concentration of water and increasing the breakdown strength.
【００３７】すなわち、本発明によれば、セルピッチを
狭めて高集積化を図る一方で、破壊耐量を増大まではさ
せないものの、低減させることのないトレンチ構造を有
する半導体装置およびその製造方法を提供することがで
きる。That is, according to the present invention, there is provided a semiconductor device having a trench structure which does not reduce but does not increase the breakdown strength while reducing the cell pitch to achieve high integration and a method of manufacturing the same. be able to.
【図１】本発明の一実施例による半導体装置の拡大断面
図。FIG. 1 is an enlarged sectional view of a semiconductor device according to one embodiment of the present invention.
【図２】本発明の図１の半導体装置の拡大平面図。FIG. 2 is an enlarged plan view of the semiconductor device of FIG. 1 of the present invention.
【図３】本発明の他の実施例による半導体装置の拡大平
面図。FIG. 3 is an enlarged plan view of a semiconductor device according to another embodiment of the present invention.
【図４】本発明の半導体装置の製造工程を示す拡大断面
図。FIG. 4 is an enlarged sectional view showing a manufacturing process of the semiconductor device of the present invention.
【図５】従来の半導体装置の拡大断面図。FIG. 5 is an enlarged sectional view of a conventional semiconductor device.
【図６】従来の図５の半導体装置の拡大平面図。FIG. 6 is an enlarged plan view of the conventional semiconductor device of FIG. 5;
【図７】従来の半導体装置の拡大平面図。FIG. 7 is an enlarged plan view of a conventional semiconductor device.
【図８】従来の半導体装置の製造工程を示す拡大断面
図。FIG. 8 is an enlarged sectional view showing a manufacturing process of a conventional semiconductor device.
１…Ｎ＋型シリコン基板 ２…Ｎ−型エピタキシャル層 ３…ベース領域 ４…不純物高濃度拡散領域 ５…ソース領域 ６…トレンチ ７…ゲート絶縁膜 ８…ゲート電極 ９…層間絶縁膜 １０…ソース電極1 ... N + -type silicon substrate 2 ... N - -type epitaxial layer 3 ... base region 4 ... high-concentration impurity diffusion region 5 ... source region 6 ... trench 7 ... gate insulating film 8 ... gate electrode 9 ... interlayer insulating film 10 ... source electrode
Claims (6)
基板と、前記半導体基板上に形成されたゲート絶縁膜
と、前記ゲート絶縁膜上に形成された導電層と具備する
半導体装置であって、 前記複数の素子分離用溝部の溝部間領域にはベース不純
物高濃度領域が形成されている領域と前記ベース不純物
高濃度領域が形成されていない領域があることを特徴と
する半導体装置。1. A semiconductor device comprising: a semiconductor substrate having a plurality of isolation trenches formed therein; a gate insulating film formed on the semiconductor substrate; and a conductive layer formed on the gate insulating film. The semiconductor device according to claim 1, wherein the inter-groove regions of the plurality of isolation trenches include a region where a base impurity high concentration region is formed and a region where the base impurity high concentration region is not formed.
いない前記溝部間領域の幅は、前記ベース不純物高濃度
領域が形成されている前記溝部間領域の幅よりも小さい
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the width of the inter-groove region where the base impurity high-concentration region is not formed is smaller than the width of the inter-groove region where the base impurity high-concentration region is formed. Item 2. The semiconductor device according to item 1.
プの少なくとも５％となるように形成することを特徴と
する請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein said high-concentration base impurity region is formed to be at least 5% of an IC chip.
高濃度領域を形成する工程と、 少なくとも前記ベース不純物高濃度領域以外に複数の素
子分離用溝部を形成する工程と、 前記溝部の形成された半導体基板上にゲート絶縁膜を形
成する工程と、 前記ゲート絶縁膜の形成された前記溝部にゲート電極を
埋め込む工程と、 前記ゲート電極を埋め込んだ前記溝部を少なくとも覆う
ように層間絶縁膜を堆積する工程と、 前記半導体基板、前記ベース不純物高濃度領域および前
記層間絶縁膜上を覆うようにソース電極を堆積する工程
とを少なくとも具備する半導体装置の製造方法であっ
て、 前記複数の素子分離用溝部の溝部間領域にはベース不純
物高濃度領域が形成されている領域と前記ベース不純物
高濃度領域が形成されていない領域があることを特徴と
する半導体装置の製造方法。4. A step of forming a base impurity high-concentration region at a predetermined position on a semiconductor substrate; a step of forming a plurality of element isolation trenches at least in a region other than the base impurity high-concentration region; Forming a gate insulating film on the semiconductor substrate that has been formed, burying a gate electrode in the trench in which the gate insulating film is formed, and depositing an interlayer insulating film so as to cover at least the trench in which the gate electrode is buried. And a step of depositing a source electrode so as to cover the semiconductor substrate, the base impurity high-concentration region, and the interlayer insulating film. In the inter-groove region of the groove portion, there are a region where the base impurity high concentration region is formed and a region where the base impurity high concentration region is not formed. The method of manufacturing a semiconductor device according to claim and.
いない前記溝部間領域の幅は、前記ベース不純物高濃度
領域が形成されている前記溝部間領域の幅よりも小さい
ことを特徴とする請求項４記載の半導体装置の製造方
法。5. A width of the inter-groove region where the base impurity high concentration region is not formed is smaller than a width of the inter-groove region where the base impurity high concentration region is formed. Item 5. The method for manufacturing a semiconductor device according to Item 4.
プの少なくとも５％となるように形成することを特徴と
する請求項４記載の半導体装置の製造方法。6. The method according to claim 4, wherein the high-concentration base impurity region is formed so as to cover at least 5% of the IC chip.
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|---|---|---|---|
| JP10229081A JP2000058823A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229081A JP2000058823A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000058823A true JP2000058823A (en) | 2000-02-25 |
Family
ID=16886461
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10229081A Withdrawn JP2000058823A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device and its manufacture |
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| Country | Link |
|---|---|
| JP (1) | JP2000058823A (en) |
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| WO2005048352A1 (en) | 2003-11-12 | 2005-05-26 | Toyota Jidosha Kabushiki Kaisha | Trench gate field effect devices |
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| WO2008010148A1 (en) * | 2006-07-14 | 2008-01-24 | Nxp B.V. | Trench field effect transistors |
| JP2010077007A (en) * | 2008-08-26 | 2010-04-08 | Hiroki Ago | Base material for forming carbon nanotube, carbon nanotube orientedly grown on the base material and their production method |
| DE112008004038T5 (en) | 2008-10-14 | 2011-09-29 | Mitsubishi Electric Corporation | power device |
| US8129818B2 (en) | 2008-10-14 | 2012-03-06 | Mitsubishi Electric Corporation | Power device |
| JP2011023675A (en) * | 2009-07-21 | 2011-02-03 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JP2012064686A (en) * | 2010-09-15 | 2012-03-29 | Toshiba Corp | Semiconductor device |
| CN102403358A (en) * | 2010-09-15 | 2012-04-04 | 株式会社东芝 | Semiconductor device |
| US9029918B2 (en) | 2010-09-15 | 2015-05-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9293548B2 (en) | 2010-09-15 | 2016-03-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN104183634A (en) * | 2014-09-16 | 2014-12-03 | 株洲南车时代电气股份有限公司 | Trench gate IGBT chip |
| US10593787B2 (en) | 2015-05-14 | 2020-03-17 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US10943997B2 (en) | 2015-05-14 | 2021-03-09 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
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