JPS61144884A - Temperature compensation circuit - Google Patents
Temperature compensation circuitInfo
- Publication number
- JPS61144884A JPS61144884A JP26783584A JP26783584A JPS61144884A JP S61144884 A JPS61144884 A JP S61144884A JP 26783584 A JP26783584 A JP 26783584A JP 26783584 A JP26783584 A JP 26783584A JP S61144884 A JPS61144884 A JP S61144884A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resistor
- temperature
- operational amplifier
- temperature compensation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Circuit For Audible Band Transducer (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Pressure Sensors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体変換器の温度上昇にともなう出力感度
の変化を補償する温度補償回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a temperature compensation circuit that compensates for changes in output sensitivity due to increases in temperature of a semiconductor converter.
従来、半導体変換器として、半導体ピエゾ抵抗素子を用
いた圧力変換器がよく知られている。該ピエゾ抵抗素子
のゲージ率は一般に負の温度系数を示し、核ピエゾ抵抗
素子を含むブリッジ回路からなる変換器の圧力・電気変
換感度は周囲温度の上昇に伴ない低下する。この感度低
下を補償する集積化レベルの温度補償回路として、従来
（１）パイポー２・トランジスタのベース・エミッタ間
順方向電圧ＶＢＩの負の温度系数を利用し、電源電圧か
らＶＢΣに比例した電圧を差しひくことによシブリッジ
励起電圧を温度上昇に対して直線的に増大させるように
した温度補償回路（信学技報ＥＤ８０−２０）、
（２）電流密度の異なるバイポーラ・トランジスタのベ
ース・エミッタ間電圧の差ΔＶｉｌｌが絶対温度に比例
する（アイ・イー・イー・イー・ジャーナル・オプ・ソ
リッド・ステート・サーキッツ（ＩＥＥＥＪ、 ５ｏｌ
ｉｄ−５ｔａｔｅ Ｃ１ｒｃｕｉｔｓ ） ６巻、 １
９７１年、２〜７ページ）ことを利用して、ブリッジ励
起電圧に正の温度係数を与えるようにした温度補償回路
（センサースア／ドアクチ為エータ（Ｓｅｎｓｏｒｓ
ａｎｄ Ａｃｔｕａｔｏｒｓ ）４巻、１９８３年、６
３〜６９ページ）等が報告されている。上記の２例には
いずれもパイボー２集積技術が用いられている。しかし
ながら、集積化変換器の目標は多機能化、インテリジェ
ント化にあシ、これらの目標を実現する集積回路技術と
しては、バイポーラ技術よりもＭＤＳ技術の方が優れて
いる。すなわち、将来の集積化変換器には、半導体検知
素子と同一基板上に、単に温度補償機能のみでなく、増
幅機能、マルチプレックス機能、チップ内での演算処理
機能、コンピュータとのディジタルインターフェースを
可能にするＡ／Ｄ変換及びディジタル信号処理機能等を
塔載することが要求される。これらの要求には、スイッ
チトキャパシタ回路、アナログ・スイッチ、 Ａ／Ｄ変
換マイクロ・プロセッサ等を含むアナログ・ディジタル
混載回路の分野で実績があシ、バイポーラ技術に比べ、
低消費電力化と大規模集積化が可能なＭＯ３集積回路技
術が適している。Conventionally, a pressure transducer using a semiconductor piezoresistive element is well known as a semiconductor transducer. The gauge factor of the piezoresistive element generally exhibits a negative temperature coefficient, and the pressure-to-electrical conversion sensitivity of a transducer consisting of a bridge circuit including the nuclear piezoresistive element decreases as the ambient temperature rises. Conventionally, a temperature compensation circuit at an integrated level that compensates for this decrease in sensitivity utilizes the negative temperature coefficient of the forward voltage VBI between the base and emitter of the Pipo2 transistor, and calculates a voltage proportional to VBΣ from the power supply voltage. Temperature compensation circuit (IEICE Technical Report ED80-20) that increases the Sibridge excitation voltage linearly with respect to temperature rise (2) Between the base and emitter of bipolar transistors with different current densities The voltage difference ΔVill is proportional to the absolute temperature (IEEJ Journal of Solid State Circuits (IEEEJ, 5ol
id-5tate C1rcuits) Volume 6, 1
971, pp. 2-7), a temperature compensation circuit (Sensors
and Actuators) Volume 4, 1983, 6
Pages 3 to 69) have been reported. Both of the above two examples use Pibo 2 integration technology. However, the goal of integrated converters is to make them multi-functional and intelligent, and MDS technology is superior to bipolar technology as an integrated circuit technology that achieves these goals. In other words, future integrated converters will have not only a temperature compensation function, but also an amplification function, multiplex function, on-chip arithmetic processing function, and a digital interface with a computer on the same substrate as the semiconductor sensing element. It is required to incorporate A/D conversion and digital signal processing functions, etc. These requirements have been met by a proven track record in the field of analog-digital hybrid circuits, including switched capacitor circuits, analog switches, A/D conversion microprocessors, etc., and compared to bipolar technology,
MO3 integrated circuit technology, which allows for low power consumption and large-scale integration, is suitable.
しかしながら、周知の集積化温度補償回路は、いずれも
バイポーラ集積化を前提としておシ、根本的にＭＯ５集
積化プロセスに適合し得ないものであった。However, all known integrated temperature compensation circuits are based on bipolar integration and are fundamentally incompatible with the MO5 integration process.
上記問題点を解決するために、ＭＯ３集積化に適した構
成を備えた温度補償回路（特願昭５９−１８７６３３号
）が考えられた。第２図に該温度補償回路の構成を示す
。図において１００はピエゾ抵抗素子１．２゜３．４か
ら成るブリッジ回路、５は基準電圧発生回路、６は演算
増幅器、７は抵抗、８は抵抗７よりも大きな正の温度係
数を有する感温拡散抵抗である。この回路では、抵抗７
と感温拡散抵抗８とが、演算増幅器６の出力電圧の一部
を反転側へ力端子に戻す負帰還ループを形成している。In order to solve the above-mentioned problems, a temperature compensation circuit (Japanese Patent Application No. 187633/1982) was devised having a configuration suitable for MO3 integration. FIG. 2 shows the configuration of the temperature compensation circuit. In the figure, 100 is a bridge circuit consisting of a piezoresistive element 1.2°3.4, 5 is a reference voltage generation circuit, 6 is an operational amplifier, 7 is a resistor, and 8 is a temperature sensor having a larger positive temperature coefficient than the resistor 7. It is a diffusion resistance. In this circuit, resistor 7
and the temperature-sensitive diffused resistor 8 form a negative feedback loop that returns part of the output voltage of the operational amplifier 6 to the inverting side to the power terminal.
演算増幅器６をも含めた回路としては、基準電圧発生回
路５の出力電圧に対する反転形回路になっておシ、該演
算増幅器６の出力電圧でブリッジ回路１００−が励起さ
れる構成になっている。The circuit including the operational amplifier 6 is an inverting circuit for the output voltage of the reference voltage generation circuit 5, and the bridge circuit 100- is excited by the output voltage of the operational amplifier 6. .
したがって、いま抵抗７及び感温拡散抵抗８の抵抗値を
Ｒ１及びＲ２とし、基準電圧発生回路５の出力電圧をＶ
ｒｅｆとし、抵抗７の温度係数が事実上温度に不感と見
なし得る程度に小さいと仮定すると、演算増幅器６の出
力電圧す表わちブリッジ回路１００に供給される励起電
圧Ｖｅｘｃは次式で与えられる。Therefore, let us assume that the resistance values of the resistor 7 and the temperature-sensitive diffused resistor 8 are R1 and R2, and the output voltage of the reference voltage generation circuit 5 is V.
ref, and assuming that the temperature coefficient of the resistor 7 is so small that it can be considered virtually insensitive to temperature, the output voltage of the operational amplifier 6, that is, the excitation voltage Vexc supplied to the bridge circuit 100, is given by the following equation. .
Ｖｅｘｃ ＝ −Ｒｔ ＃ Ｖｒｅｆ
ここで、 Ｒ２（０）及びａは、感温拡散抵抗８の成る
基準温度における抵抗値及び抵抗温度係数、ｔは基準温
度からの温度遷移である。上式から明らかなように、第
２図の回路によれば、ブリッジ回路１００の励起電圧Ｖ
ｅｘｃに感温拡散抵抗８の温度係数Ｃに基づく正の温度
係数を与えることができ、ピエゾ抵抗係数の負の温度係
数に基づくブリッジ回路１００の圧力−電気変換感度の
負の温度係数を補償することができる。Vexc = -Rt #Vref Here, R2(0) and a are the resistance value and resistance temperature coefficient at the reference temperature of the temperature-sensitive diffused resistor 8, and t is the temperature transition from the reference temperature. As is clear from the above equation, according to the circuit of FIG. 2, the excitation voltage V of the bridge circuit 100
A positive temperature coefficient based on the temperature coefficient C of the temperature-sensitive diffused resistor 8 can be given to exc, which compensates for the negative temperature coefficient of the pressure-electrical conversion sensitivity of the bridge circuit 100 based on the negative temperature coefficient of the piezoresistance coefficient. be able to.
第２図の回路で、圧力−電気変換感度の温度係数を零に
するためには、ブリッジ励起電圧の温度係数すなわち感
温拡散抵抗８の抵抗温度係数−（正の値）をブリッジ回
路１ｏｏを構成するピエゾ抵抗素子１〜４のピエゾ抵抗
係数の温度係数と等しく選べばよい。これに一般には、
ピエゾ抵抗素子１ぞれ適宜制御することによシ達成され
る。ｎ形シリコン基板に形成されたｐ形不純物領域から
なる拡散抵抗の場合には、表面不純物濃度が３×１０及
び２Ｘ１０２０ｃ＋＋＋−”の近傍において、抵抗温度
係数（正の値）とピエゾ抵抗係数温度係数（負の値）の
絶対値が等しくなる。したがって表面不純物濃度を上記
条件に選ぺば、温度補償のための感温拡散抵抗８をピエ
ゾ抵抗素子１〜４と同一工程で製造できる。In the circuit shown in Fig. 2, in order to make the temperature coefficient of the pressure-electrical conversion sensitivity zero, the temperature coefficient of the bridge excitation voltage, that is, the resistance temperature coefficient of the temperature-sensitive diffused resistor 8 - (positive value) must be changed to the bridge circuit 1oo. It may be selected to be equal to the temperature coefficient of the piezoresistance coefficient of the piezoresistance elements 1 to 4 constituting the piezoresistance elements 1 to 4. In general,
This is achieved by appropriately controlling each piezoresistive element 1. In the case of a diffused resistor consisting of a p-type impurity region formed on an n-type silicon substrate, the temperature coefficient of resistance (positive value) and the temperature coefficient of piezo resistance coefficient are (negative values) are the same. Therefore, if the surface impurity concentration is selected to meet the above conditions, the temperature-sensitive diffused resistor 8 for temperature compensation can be manufactured in the same process as the piezoresistive elements 1 to 4.
第２図の回路に使用される基準電圧発生回路５ハ、エン
ハンスメント形ＭＯ５ＦＥＴ ドア’ ７’ リ−シ＝
ｚ ｙ形ＭＯ５ＦＥＴのスレッシ冒ルド電圧の差を検出
する回路方式（アイ・イー・イー・イー・ジャーナル・
オプ・ソリッド・ステート・サーキ、ツツ（ＩＥＥＥＪ
、 ５ｏｌｉｄ −５ｔａｔｅ Ｃ１ｒｃｕｉｔｓ ）
１３巻、１９７８ 紙７６７〜７７４ページ）を用い
ることによｊｊ７ＭＯ５集積化プロセスで製造可能であ
シ、これとＭＯ５演算増幅器、感温拡散抵抗、拡散形ピ
エゾ抵抗素子を同一半導体基板上に一体化することによ
ｐＭＯ５集積化された温度補償回路が構成される。Reference voltage generation circuit 5c used in the circuit of Fig. 2, enhancement type MO5FET door'7'
z Circuit method for detecting the difference in threshold voltage of y-type MO5FET (IEE Journal
Op Solid State Sarki, Tutu (IEEEJ
, 5olid-5tate C1rcuits)
13, 1978, paper pages 767-774), it can be manufactured using the jj7 MO5 integration process, and this, an MO5 operational amplifier, a temperature-sensitive diffused resistor, and a diffused piezoresistive element can be integrated on the same semiconductor substrate. By doing so, a pMO5 integrated temperature compensation circuit is constructed.
以上、ＭＯ５集積化に適した温度補償回路の従来例を述
べたが、この回路は、ピエゾ抵抗素子１〜４から成るブ
リッジ回路１００−及び感温拡散抵抗８が大負荷電流の
供給には不向きなＭＯ５演算増幅器６の負荷となるため
、ピエゾ抵抗素子１〜４及び感温拡散抵抗８の抵抗値、
すなわち拡散抵抗長を小さくできない欠点がある。最も
広く用いられているダイア２ム形圧力変換器の場合、圧
力−電気変換感度はピエゾ抵抗素子の長さとともに著し
く低下するので、抵抗長の増大は感度の著しい劣化をま
ねく。また、感温拡散抵抗は圧力不感部であるダイアス
ラム周辺の狭い厚肉部領域に配置されるので抵抗長の増
大はパターン配置の困難さを惹起する。これらを回避す
る方法は演算増幅器出力段の寸法を大きくシ、負荷能力
を高めることであるが、出力段の寸法増大は、前段に影
響を及ぼし、演算増幅器全体の周波数特性を劣化させる
。これを防止するには、前段さらに前段の寸法を増大さ
せる必要があり、結果として演算増幅器の消費電力と占
有面積は著しく増大してしまう。The conventional example of the temperature compensation circuit suitable for MO5 integration has been described above, but this circuit is not suitable for supplying large load current because the bridge circuit 100- consisting of piezoresistive elements 1 to 4 and the temperature-sensitive diffused resistor 8 are not suitable for supplying large load current. The resistance values of the piezoresistive elements 1 to 4 and the temperature-sensitive diffused resistor 8 are
That is, there is a drawback that the length of the diffused resistance cannot be made small. In the case of the most widely used diamond pressure transducer, the pressure-to-electrical conversion sensitivity decreases significantly with the length of the piezoresistive element, so an increase in the resistance length leads to a significant deterioration of the sensitivity. Furthermore, since the temperature-sensitive diffused resistor is arranged in a narrow thick region around the diaslum which is a pressure-insensitive part, an increase in the resistance length causes difficulty in pattern arrangement. A way to avoid these problems is to increase the size of the operational amplifier output stage and increase the load capacity, but increasing the size of the output stage affects the previous stage and deteriorates the frequency characteristics of the entire operational amplifier. To prevent this, it is necessary to further increase the size of the previous stage, and as a result, the power consumption and occupied area of the operational amplifier significantly increase.
本発明の目的は、ＭＯ５集積化に適し、かつ上記従来技
術の欠点が除去された温度補償回路を提供することにあ
ろう
〔問題点を解決するための手段〕
本発明は、基準電圧発生回路と、非反転入力端子がコモ
ン端子に接続された演算増幅器と、該増幅器出力がゲー
トに接続されたソースフォロワ構成のＦＥＴと、前記演
算増幅器の反転側入力端子と前記基準電圧発生回路出力
及び前記ＦＥＴのソースとの間にそれぞれ接続された抵
抗及び該抵抗よりも大きな正の温度係数を有する感温拡
散抵抗とを備え、前記ＦＥＴの出力を受けて励起される
検出回路とを備えたことを特徴とする温度補償回路であ
る。An object of the present invention is to provide a temperature compensation circuit that is suitable for MO5 integration and eliminates the drawbacks of the above-mentioned prior art. an operational amplifier whose non-inverting input terminal is connected to a common terminal; an FET having a source follower configuration in which the output of the amplifier is connected to a gate; an inverting input terminal of the operational amplifier, an output of the reference voltage generating circuit, and the The detection circuit includes a resistor connected between the source of the FET and a temperature-sensitive diffused resistor having a larger positive temperature coefficient than the resistor, and is excited by receiving the output of the FET. This is a characteristic temperature compensation circuit.
以下、実施例によシ本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail by way of examples.
第１図は、本発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.
図において、１００は第２図の構成と同じくピエゾ抵抗
素子１．２．３．４から成るブリッジ回路、 １０は基
準電圧発生回路、２０は非反転側入力端子が接地された
演算増幅器、３０はゲートに該演算増幅器２０の出力が
接続され九ＦＥＴ、 １１は基準電圧発生回路１０の出
力と演算増幅器２０の反転側入力端子との間に接続され
た抵抗、１２はＦＥＴ３０のソースと演算増幅器２０の
非反転側入力端子との間に接続された感温拡散抵抗であ
シ、検出回路としてのブリッジ回路１００はドレインが
電源端子１３に接続されたソースフォロワ構成のＦＥＴ
３０の出力で励起される。In the figure, 100 is a bridge circuit consisting of piezoresistive elements 1, 2, 3, and 4 as in the configuration shown in FIG. 2, 10 is a reference voltage generation circuit, 20 is an operational amplifier whose non-inverting side input terminal is grounded, and 30 is a 11 is a resistor connected between the output of the reference voltage generating circuit 10 and the inverting input terminal of the operational amplifier 20; 12 is a resistor connected between the source of the FET 30 and the operational amplifier 20; The bridge circuit 100 as a detection circuit is an FET with a source follower configuration whose drain is connected to the power supply terminal 13.
Excited with a power of 30.
本実施例において、抵抗１１及び感温拡散抵抗１２は、
第２図における抵抗７及び感温拡散抵抗８にそれぞれ対
応しており、演算増幅器２０の負帰還回路を形成してブ
リッジ回路１００の励起電圧に感温拡散抵抗１２の温度
係数に基づく正の温度係数を与える。抵抗１１としては
、事実上温度に不感な抵抗と見なし得る程度に温度係数
の小さい、例えば金属皮膜、厚膜あるいは薄膜抵抗を、
感温拡散抵抗１２としては、抵抗１１よりも大きな正の
温度係数を有する、例えばピエゾ抵抗素子と同一基板上
の圧力不感部に形成された拡散抵抗を用いることができ
る。In this embodiment, the resistor 11 and the temperature-sensitive diffused resistor 12 are
They respectively correspond to the resistor 7 and the temperature-sensitive diffused resistor 8 in FIG. Give the coefficient. As the resistor 11, for example, a metal film, thick film, or thin film resistor with a small temperature coefficient that can be considered as a virtually temperature-insensitive resistor is used.
As the temperature-sensitive diffused resistor 12, a diffused resistor having a larger positive temperature coefficient than the resistor 11 and formed, for example, in a pressure-insensitive portion on the same substrate as the piezoresistive element can be used.
本実施例の特徴は、ブリッジ回路１００が演算増幅器２
０よシソースフォロワを構成するＦＥＴ３０を介して励
起させている点にある。すなわち、第２図に示した従来
の温度補償回路が演算増幅器６の出力で直接ブリッジ回
路１００を励起するよう構成されていたのに対し、本実
施例では、ブリッジ回路１００が演算増幅器２０の出力
に直接接続されるのではなく、ソースフォロワ構成のＦ
ＥＴ３０を介して励起されるようにその構成が修正され
ている。The feature of this embodiment is that the bridge circuit 100 is connected to the operational amplifier 2.
0 is excited via the FET 30 that constitutes a source follower. That is, while the conventional temperature compensation circuit shown in FIG. F in a source follower configuration rather than directly connected to
Its configuration has been modified to be excited via ET30.
本実施例の構成によれば、ブリッジ回路１００及び感温
拡散抵抗１２はＦＥＴ３０によるソースフォロワの負荷
となυ、演算増幅器２０の負荷は単にＦ ＥＴ ３０の
ゲート容量のみとなる。抵抗負荷がなく容量性負荷のみ
となるので演算増幅器２０の大幅な低消費電力化が可能
である。さらに、第２図の回路ではインバータあるいは
ソースフォロワで構成される演算増幅器出力段の一方の
ＭＯＳＦＥＴと負荷であるブリッジ回路１００及び感温
拡散抵抗８が並列に接続されていたためもう一方のＭＯ
９ＦＥＴＦＣ負荷電流と動作点電流の和の電流を流す必
要があったが、本実施例ではＦＥ７３０は負荷電流に等
しい電流を負担するだけでよい。したがって回路全体と
しても大幅な低消費電力化が図れる。According to the configuration of this embodiment, the bridge circuit 100 and the temperature-sensitive diffused resistor 12 serve as a load on the source follower of the FET 30, and the load on the operational amplifier 20 is simply the gate capacitance of the FET 30. Since there is no resistive load and there is only a capacitive load, the power consumption of the operational amplifier 20 can be significantly reduced. Furthermore, in the circuit shown in FIG. 2, one MOSFET of the operational amplifier output stage composed of an inverter or a source follower is connected in parallel with the bridge circuit 100 and the temperature-sensitive diffused resistor 8, so that the other MOSFET is connected in parallel.
Although it was necessary to flow a current equal to the sum of the 9FET FC load current and the operating point current, in this embodiment, the FE 730 only needs to bear a current equal to the load current. Therefore, the power consumption of the entire circuit can be significantly reduced.
したがりて、本実施例によれば、大電力を消費すること
なく、また大面積を占有することなく、上記従来技術の
欠点がことごとく解消され、ＭＯ５集積化に適した極め
て有用な温度補償回路が得られる。Therefore, according to this embodiment, all the drawbacks of the above-mentioned conventional techniques are eliminated without consuming large amounts of power or occupying a large area, and an extremely useful temperature compensation circuit suitable for MO5 integration is achieved. is obtained.
以上、ピエゾ抵抗素子を用いた圧力変換器の場合を説明
したが、本発明は圧力変換器のみならず、検知対象の変
化に応答して抵抗値変化を示す半導体検知素子を用いる
半導体変換器の温度補償回路に広く適用できる。Although the case of a pressure transducer using a piezoresistive element has been described above, the present invention is applicable not only to a pressure transducer but also to a semiconductor transducer using a semiconductor sensing element that shows a change in resistance value in response to a change in a detection target. Widely applicable to temperature compensation circuits.
以上のように本発明によれば、上記従来技術の欠点がこ
とごとく解消され、 ＭＯ５集積化に適した極めて有用
な温度補償回路が実現される。本発明による温度補償回
路は半導体変換器のマイクロコンピュータどの組合せに
よるインテリジェント化に寄与し、その効果は大きいも
のである。As described above, according to the present invention, all the drawbacks of the above-mentioned prior art are eliminated, and an extremely useful temperature compensation circuit suitable for MO5 integration is realized. The temperature compensation circuit according to the present invention contributes to making semiconductor converters intelligent by combining them with microcomputers, and its effects are significant.
【図面の簡単な説明】
第１図は本発明の一実施例を示す回路図、第２図は半導
体変換器の温度補償回路の従来例を示す回路図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example of a temperature compensation circuit for a semiconductor converter.
Claims (1)
子に接続された演算増幅器と、該増幅器出力がゲートに
接続されたソースフォロワ構成のＦＥＴと、前記演算増
幅器の反転側入力端子と前記基準電圧発生回路出力及び
前記ＦＥＴのソースとの間にそれぞれ接続された抵抗及
び該抵抗よりも大きな正の温度係数を有する感温拡散抵
抗と、前記ＦＥＴの出力を受けて励起される検出回路と
を備えたことを特徴とする温度補償回路。(1) a reference voltage generation circuit, an operational amplifier whose non-inverting input terminal is connected to a common terminal, an FET having a source follower configuration whose output of the amplifier is connected to its gate, an inverting side input terminal of the operational amplifier, and an operational amplifier whose non-inverting input terminal is connected to a common terminal; a resistor connected between the reference voltage generation circuit output and the source of the FET, a temperature-sensitive diffused resistor having a larger positive temperature coefficient than the resistor, and a detection circuit excited in response to the output of the FET; A temperature compensation circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26783584A JPS61144884A (en) | 1984-12-19 | 1984-12-19 | Temperature compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26783584A JPS61144884A (en) | 1984-12-19 | 1984-12-19 | Temperature compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61144884A true JPS61144884A (en) | 1986-07-02 |
| JPH0578951B2 JPH0578951B2 (en) | 1993-10-29 |
Family
ID=17450279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26783584A Granted JPS61144884A (en) | 1984-12-19 | 1984-12-19 | Temperature compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61144884A (en) |
-
1984
- 1984-12-19 JP JP26783584A patent/JPS61144884A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0578951B2 (en) | 1993-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4680963A (en) | Semiconductor flow velocity sensor | |
| US4556807A (en) | Pressure transducer with temperature compensation circuit | |
| US6019508A (en) | Integrated temperature sensor | |
| US4004462A (en) | Temperature transducer | |
| JPH0570326B2 (en) | ||
| JPH02183126A (en) | Temperature threshold detecting circuit | |
| GB2096771A (en) | Temperature sensing device | |
| JPS5961736A (en) | Integrated pressor sensor | |
| CN115357086A (en) | Band gap reference circuit, operating method thereof and electronic device | |
| JPH0972805A (en) | Semiconductor sensor | |
| JP2575611B2 (en) | Integrated circuit semiconductor converter | |
| JPS61144884A (en) | Temperature compensation circuit | |
| US5663574A (en) | Power semiconductor component with monolithically integrated sensor arrangement as well as manufacture and employment thereof | |
| JP2000283790A (en) | Low frequency noise removing method and cmos sensor circuit | |
| JPS6197543A (en) | Compensation circuit for semiconductor pressure sensor | |
| US6810745B2 (en) | Temperature dependent sensitivity compensation structure of sensor | |
| Dobkin | Monolithic temperature transducer | |
| JPS6166105A (en) | Temperature compensating circuit | |
| JPH0721402B2 (en) | Temperature compensation circuit | |
| JPS5844303A (en) | Semiconductor strain gauge | |
| JP4424762B2 (en) | pressure sensor | |
| JPS63210635A (en) | Detection circuit of semiconductor sensor | |
| JPS62267604A (en) | Temperature compensating circuit for semiconductor transducer | |
| Falconi et al. | Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems | |
| JP2586103B2 (en) | Temperature compensation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |