JPS61119079A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

Info

Publication number
JPS61119079A
JPS61119079A JP59241239A JP24123984A JPS61119079A JP S61119079 A JPS61119079 A JP S61119079A JP 59241239 A JP59241239 A JP 59241239A JP 24123984 A JP24123984 A JP 24123984A JP S61119079 A JPS61119079 A JP S61119079A
Authority
JP
Japan
Prior art keywords
film
thin film
impurities
semiconductor thin
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59241239A
Other languages
Japanese (ja)
Other versions
JPH0824184B2 (en
Inventor
Hisao Hayashi
久雄 林
Takashi Noguchi
隆 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59241239A priority Critical patent/JPH0824184B2/en
Priority to KR1019850007608A priority patent/KR930010978B1/en
Priority to GB08527737A priority patent/GB2167899B/en
Priority to NL8503123A priority patent/NL194524C/en
Priority to DE3540452A priority patent/DE3540452C2/en
Priority to FR858516906A priority patent/FR2573248B1/en
Priority to CN198585109088A priority patent/CN85109088A/en
Publication of JPS61119079A publication Critical patent/JPS61119079A/en
Publication of JPH0824184B2 publication Critical patent/JPH0824184B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To simplify the manufacturing process compared with the conventional methods by eliminating the necessity of carrying out a heat treatment for a solid-phase growth and a heat treatment for electrically activating the impurities for forming source and drain regions, separately as in the conventional methods. CONSTITUTION:A polycrystalline silicon film 4 is formed on a glass substrate 1 and an amorphous silicon film 3 is formed by ion implantation of Si<+>. A gate insulating film 8 consisting of an SiO2 film 5 and a gate electrode 7 consisting of an Mo film 6 are formed. By using the gate electrode 7 and the gate insulating film 8 as a mask, phosphorus for forming source and drain regions is introduced into a semiconductor thin film and a heat treatment is made. Thus the amorphous semiconductor thin film is grown by solid phase and impurities are activated electrically to form N<+> type source region 9 and drain region 10.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は薄膜トランジスタの製造方法に関するものであ
って、多結晶シリコン薄膜トランジスタの製造に適用し
て最適なものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing thin film transistors, and is most suitable for application to manufacturing polycrystalline silicon thin film transistors.

従来の技術 従来、低温プロセスによる多結晶シリコン薄膜トランジ
スタ（ＴＰＴ）の製造は例えば次のような方法により行
われている。すなわち、まず第２Ａ図に示すように、例
えば融点が６８０°Ｃ程度の゛ガラス基板１上にＬＰＣ
ＶＤ法により６００℃以下の温度で多結晶シリコン膜２
を被着形成した後、この多結晶シリコン膜２にＳｉ″−
等の電気的に不活性な元素のイオンをイオン注入するこ
とにより、第２Ｂ図に示すように非晶質シリコン膜３と
する。2. Description of the Related Art Conventionally, polycrystalline silicon thin film transistors (TPT) have been manufactured by low-temperature processes, for example, by the following method. That is, as shown in FIG. 2A, for example, LPC is placed on a glass substrate 1 having a melting point of about 680°C.
Polycrystalline silicon film 2 is formed at a temperature of 600°C or less using the VD method.
After depositing Si″- on this polycrystalline silicon film 2,
By implanting ions of electrically inert elements such as, an amorphous silicon film 3 is formed as shown in FIG. 2B.

次に５００〜６００℃の温度でアニールを行うことによ
り上記非晶質シリコン膜３を固相成長させて結晶化を行
う。その結果、第２Ｃ図に示すように、多結晶シリコン
膜２よりもその結晶粒の大きさが大きい多結晶シリコン
膜４が形成される。次に第２Ｄ図に示すように、この多
結晶シリコン膜４の所定部分をエツチング除去して所定
形状とした後、ＣＶＤ法により４００℃程度で全面にＳ
ｉＯ□膜５を被着形成し、次いでスパッタ法により例え
ばＭｏ膜６を被着形成する。次にこれらの門０膜６及び
ＳｉＯ□膜５の所定部分を順次エツチング除去して、第
２Ｅ図に示すように、所定形状の門。膜から成るゲート
電極７及び所定形状のＳｉｎ、膜から成るゲート絶縁膜
８を形成する。次にこれらのゲート電極７及びゲート絶
縁膜８をマスクとして多結晶シリコン膜４にリン（Ｐ）
等のｎ型不純物を高濃度にイオン注入した後（多結晶シ
リコン膜４中のＰを０で表す）、６００℃程度の温度で
アニールを行うことによりこの不純物を電気的に活性化
させて、第２Ｆ図に示すように、ｎ４型のソース領域９
及びドレイン領域１ｏを形成する。次に第２Ｇ図に示す
ように、ＣＶＤ法により４００’Ｃ程度の温度で全面に
パッシベーション膜としてのＳｉｎｇ膜１１全１１形成
し、次いでこのＳｉｎｇ膜ＩＩ’の所定部分をエツチン
グ除去して開口１１ａ、ｌｌｂを形成した後、これらの
開口１１ａ、ｌｌｂを通じてＡＮから成る電極１２．１
３を被着形成して、ｎチャネル多結晶シリコンＴＰＴを
完成させる。Next, annealing is performed at a temperature of 500 to 600° C. to cause solid phase growth of the amorphous silicon film 3 and crystallize it. As a result, as shown in FIG. 2C, a polycrystalline silicon film 4 whose crystal grain size is larger than that of the polycrystalline silicon film 2 is formed. Next, as shown in FIG. 2D, a predetermined portion of this polycrystalline silicon film 4 is removed by etching to obtain a predetermined shape, and then the entire surface is etched by CVD at about 400°C.
An iO□ film 5 is deposited, and then, for example, a Mo film 6 is deposited by sputtering. Next, predetermined portions of the gate 0 film 6 and the SiO□ film 5 are sequentially etched away to form gates of a predetermined shape, as shown in FIG. 2E. A gate electrode 7 made of a film and a gate insulating film 8 made of a Sin film having a predetermined shape are formed. Next, using these gate electrodes 7 and gate insulating films 8 as masks, phosphorus (P) is applied to the polycrystalline silicon film 4.
After ion-implanting a high concentration of n-type impurities such as (P in the polycrystalline silicon film 4 is represented by 0), this impurity is electrically activated by annealing at a temperature of about 600°C. As shown in FIG. 2F, an n4 type source region 9
and a drain region 1o. Next, as shown in FIG. 2G, a Sing film 11 as a passivation film is formed on the entire surface at a temperature of about 400'C by CVD, and then a predetermined portion of this Sing film II' is etched away to form an opening 11a. , llb, an electrode 12.1 made of AN is formed through these openings 11a and llb.
3 is deposited to complete the n-channel polycrystalline silicon TPT.

上述の従来の低温プロセスによる多結晶シリコンＴＰＴ
の製造方法は次のような欠点を有している。すなわち、
非晶質シリコン膜３を固相成長させるためのアニールと
、ソース領域９及びドレイン領域１０形成用の不純物を
電気的に活性化させるためのアニールとを別々に行わな
ければならないので、製造工程が簡便でない。また多結
晶シリコン膜４にイオン注入された上記不純物の一部は
、この多結晶シリコン膜４中の結晶粒界に存在するが、
この結晶粒界に存在する不純物はアニールによっても電
気的に活性化されにくいため、全体として不純物の活性
化率が低い。さらに多結晶シリコン膜４への不純物のイ
オン注入の際には、注入不純物のチャネリングがある程
度生じてしまうのは避けられないので、その後のアニー
ルにより形成されるソース領域９及びドレイン領域１０
中の不純物の活性化率の均一性が悪い。Polycrystalline silicon TPT by the conventional low temperature process mentioned above
The manufacturing method has the following drawbacks. That is,
Since annealing for solid-phase growth of amorphous silicon film 3 and annealing for electrically activating impurities for forming source region 9 and drain region 10 must be performed separately, the manufacturing process is simplified. It's not convenient. Furthermore, some of the impurities ion-implanted into the polycrystalline silicon film 4 are present at grain boundaries in the polycrystalline silicon film 4;
Since impurities present in the grain boundaries are difficult to be electrically activated even by annealing, the activation rate of impurities is low overall. Furthermore, when impurity ions are implanted into the polycrystalline silicon film 4, it is inevitable that channeling of the implanted impurities will occur to some extent.
The activation rate of impurities inside is not uniform.

なおＴＰＴに関する先行文献としては、日本応用物理学
会第４５回学術講演会予稿集、１４ｐ−Ａ−４〜１４ｐ
−Ａ−６（１９８４）が挙げられる。Prior literature on TPT includes Proceedings of the 45th Academic Conference of the Japanese Society of Applied Physics, p.14-A-4 to p.14.
-A-6 (1984).

発明が解決しようとする問題点 本発明は、上述の問題にかんがみ、従来の薄膜トランジ
スタの製造方法が有する上述のような欠点を是正した薄
膜トランジスタの製造方法を提供することを目的とする
。Problems to be Solved by the Invention In view of the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a thin film transistor that corrects the above-described drawbacks of conventional methods for manufacturing a thin film transistor.

問題点を解決するための手段 本発明に係る薄膜トランジスタの製造方法は、所定の基
板（例えばガラス基板１）上に多結晶の半導体薄膜（例
えば多結晶シリコン膜２）を形成する工程と、上記多結
晶の半導体薄膜に所定のイオン（例えばＳｉ’　）をイ
オン注入することにより非晶質の半導体薄膜（例えば非
晶質シリコン膜３）を形成する工程と、上記非晶質の半
導体薄膜上にゲート絶縁膜（例えば５ｉＯｚ膜から成る
ゲート絶縁膜８）゛及びゲート電極（例えばＭｏ膜から
成るゲート電極７）を形成する工程と、上記ゲート電極
及び上記ゲート絶縁膜をマスクとして上記非晶質の半導
体薄膜にソース領域及びドレイン領域形成用の不純物（
例えばリン）を導入する工程と、熱処理を行うことによ
り上記非晶質の半導体薄膜を固相成長させると共に上記
不純物を電気的に活性化させて上記ソース領域及び上記
ドレイン領域（例えばｎ゛型のソース領域９及びドレイ
ン領域１０）を形成する工程とをそれぞれ具備している
。Means for Solving the Problems The method for manufacturing a thin film transistor according to the present invention includes the steps of forming a polycrystalline semiconductor thin film (for example, polycrystalline silicon film 2) on a predetermined substrate (for example, glass substrate 1), and A process of forming an amorphous semiconductor thin film (for example, an amorphous silicon film 3) by implanting predetermined ions (for example, Si') into a crystalline semiconductor thin film, and forming a gate on the amorphous semiconductor thin film. A step of forming an insulating film (for example, a gate insulating film 8 made of a 5iOz film) and a gate electrode (for example, a gate electrode 7 made of a Mo film), and a step of forming the amorphous semiconductor using the gate electrode and the gate insulating film as a mask. Impurities (for forming source and drain regions) are added to the thin film.
The amorphous semiconductor thin film is grown in a solid phase by introducing phosphorus (for example, phosphorus) and heat treatment, and the impurities are electrically activated to form the source region and the drain region (for example, n-type A source region 9 and a drain region 10) are formed.

実施例 以下本発明に係る薄膜トランジスタの製造方法を多結晶
シリコンＴＰＴの製造方法に適用した一実施例を図面に
基づいて説明する。なお以下の第１Ａ図〜第１Ｃ図にお
いては、第２Ａ図〜第２Ｇ図と同一部分には同一の符号
を付し、必要に応してその説明を省略する。EXAMPLE An example in which the method for manufacturing a thin film transistor according to the present invention is applied to a method for manufacturing a polycrystalline silicon TPT will be described below with reference to the drawings. In the following FIGS. 1A to 1C, the same parts as in FIGS. 2A to 2G are denoted by the same reference numerals, and the explanation thereof will be omitted if necessary.

まず第２Ａ図と同様に、Ｌｌｌ）ＣＶＤ法により５８０
〜６００℃程度の温度でガラス基板ｌ上に例えば膜厚８
００人の多結晶シリコン膜２を被着形成する。First, as in Fig. 2A, 580
For example, a film with a thickness of 8 cm is formed on a glass substrate l at a temperature of ~600°C.
A polycrystalline silicon film 2 of 0.000 mm is deposited.

次にこの多結晶シリコン膜２にＳｉ゛を例えばエネルギ
ー４０ＫｅＶ、ドーズｌｉ　ｌ　〜５　Ｘ　１０　ｌ″
ｃｍ−２程度の条件でイオン注入することにより、第２
Ｂ図と同様に非晶質シリコン膜３を形成する。Next, Si'' is applied to this polycrystalline silicon film 2 at an energy of 40 KeV and a dose of li l ~5 x 10 l''.
By implanting ions under conditions of about cm-2, the second
An amorphous silicon film 3 is formed in the same manner as in FIG.

次に第１Ａ図に示すように、上記非晶質シリコン膜３の
所定部分をエツチングすることにより所定形状とした後
、第２Ｄ図と同様に、ＬＰＣＶＤ法により例えば膜厚１
０００人のＳｉＯ□膜５を被着形成し、次いでスパッタ
法により例えば膜厚３０００人のＭＯ膜６を全面に被着
形成する。Next, as shown in FIG. 1A, a predetermined portion of the amorphous silicon film 3 is etched to form a predetermined shape, and then, as shown in FIG.
A SiO□ film 5 having a thickness of 3,000 thick is deposited, and then an MO film 6 having a thickness of 3,000 thick, for example, is deposited over the entire surface by sputtering.

次に第１Ｂ図に示すように、これらのＭｏ膜６及びＳｉ
Ｏ□膜５の所定部分を順次エツチング除去して、第２Ｅ
図と同様にゲート電極７及びゲート絶縁膜８を形成する
。この後、これらのゲート電極７及びゲート絶縁膜８を
マスクとして非晶質シリコン膜３に例えばＰ゛をイオン
注入する（非晶質シリコン膜３中のＰを０で表す）。Next, as shown in FIG. 1B, these Mo films 6 and Si
Predetermined portions of the O□ film 5 are sequentially etched away to form a second E
A gate electrode 7 and a gate insulating film 8 are formed in the same manner as shown in the figure. Thereafter, using these gate electrodes 7 and gate insulating film 8 as masks, ions of, for example, P' are implanted into the amorphous silicon film 3 (P in the amorphous silicon film 3 is represented by 0).

次に第１Ｃ図に示すように、例えば６００℃程度の温度
でアニールを行うことにより、非晶質シリコン膜３を固
相成長させて多結晶シリコン膜４を形成すると共に、注
入された上記Ｐを電気的に一活性化させて、ｎ゛型のソ
ース領域９及びドレイン領域１０を形成する。この後、
第２Ｇ図と同様に、パッシベーション膜としてのＳｉＯ
□膜１１、電極１２，１３を形成して、目的とするｎチ
ャネル多結晶シリコンＴＰＴを完成させる。Next, as shown in FIG. 1C, by performing annealing at a temperature of, for example, about 600° C., the amorphous silicon film 3 is grown in a solid phase to form a polycrystalline silicon film 4, and the implanted P is electrically activated to form an n' type source region 9 and drain region 10. After this,
Similar to Figure 2G, SiO as a passivation film
□ Film 11 and electrodes 12 and 13 are formed to complete the desired n-channel polycrystalline silicon TPT.

上述の実施例によれば、非晶質シリコン膜３の固相成長
と、ソース領域９及びドレイン領域１０形成用の不純物
の活性化とを一度のアニールで同時に行っているので、
第２Ａ図〜第２Ｇ図に示す従来の製造方法に比べてアニ
ール工程を一回省略することができ、このため製造工程
を簡略化することができる。また上述のアニール時にお
いては、非晶質シリコン膜３の固相成長と同時に注入不
純物の活性化が行われるので、アニールにより形成され
るソース領域９及びドレイン領域１０中の不純物の活性
化率は従来に比べて均一である。According to the embodiment described above, the solid phase growth of the amorphous silicon film 3 and the activation of impurities for forming the source region 9 and drain region 10 are performed simultaneously in a single annealing process.
Compared to the conventional manufacturing method shown in FIGS. 2A to 2G, one annealing step can be omitted, thereby simplifying the manufacturing process. Furthermore, during the above-mentioned annealing, the implanted impurities are activated at the same time as the solid-phase growth of the amorphous silicon film 3, so the activation rate of the impurities in the source region 9 and drain region 10 formed by the annealing is It is more uniform than before.

さらに上述のアニールによる非晶質シリコン膜３の固相
成長の際には、まずこの非晶質シリコン膜３中のＰのイ
オン注入部から核形成が起きやす（、この核が微小な結
晶に成長し、さらにより大きな結晶粒に成長するので、
ソース領域９及びドレイン領域１０中の結晶粒の大きさ
を従来に比べて大きくすることができる。従って、結晶
粒界の面積が従来に比べて小さくなるので、この分だけ
不純物の活性化率を高くすることが可能である。Furthermore, during the solid phase growth of the amorphous silicon film 3 by the above-mentioned annealing, nucleation tends to occur first from the P ion-implanted part of the amorphous silicon film 3 (this nucleus becomes a microcrystal). As it grows and further grows into larger grains,
The size of the crystal grains in the source region 9 and drain region 10 can be made larger than in the prior art. Therefore, since the area of the grain boundaries is smaller than in the conventional case, it is possible to increase the activation rate of impurities by this amount.

のみならず、上述の微小な結晶を種結晶として、非晶質
シリコン膜３の表面と平行な方向に結晶成長が進行する
ため、上述の固相成長により得られる多結晶シリコン膜
４中の結晶粒の大きさは、ＴＰＴの動作時にチャネルが
形成されるチャネル領域４ａ（第１Ｃ図参照）において
従来に比べて特に大きくなる。従って、キャリアの移動
度が従来に比べて大きいＴＰＴを得ることができる。In addition, since crystal growth proceeds in a direction parallel to the surface of the amorphous silicon film 3 using the above-mentioned minute crystal as a seed crystal, the crystals in the polycrystalline silicon film 4 obtained by the above-mentioned solid phase growth The size of the grains is particularly larger in the channel region 4a (see FIG. 1C) where a channel is formed during TPT operation compared to the conventional one. Therefore, it is possible to obtain a TPT in which the carrier mobility is greater than that in the prior art.

また上述の実施例においては、Ｓ１３等のイオン注入に
より多結晶シリコン膜２を一旦非晶質シリコン膜３とし
た後、この非晶質シリコン膜３にソース領域９及びドレ
イン領域１０形成用の不純物をイオン注入しているで、
注入不純物のチャネリングがほとんど起こらない。従っ
て、従来に比べて注入不純物の分布がより均一となるの
で、これによってもソース領域９及びドレイン領域１０
中の不純物の活性化率を従来に比べてより均一とするこ
とができる。In the above embodiment, after the polycrystalline silicon film 2 is once made into an amorphous silicon film 3 by ion implantation such as S13, impurities for forming the source region 9 and the drain region 10 are added to the amorphous silicon film 3. is ion-implanted,
Channeling of implanted impurities hardly occurs. Therefore, the distribution of the implanted impurities becomes more uniform than in the past, and this also makes it possible for the source region 9 and drain region 10 to
The activation rate of impurities therein can be made more uniform than in the past.

以上本発明の一実施例につき説明したが、本発明は上述
の実施例に限定されるものではなく、本発明の技術的思
想に基づ（種々の変形が可能である。例えば、多結晶シ
リコン膜２を非晶質化するためのイオン注入用のイオン
種としては、上述の実施例で用いたＳｉ”の他にＦ゛等
の電気的に不活性な元素のイオンを用いてもよい。また
ソース領域９及びドレイン領域１０形成用の注入不純物
のイオン種も上述の実施例で用いたＰ゛に限定されるも
のではなく、必要に応じて他の種類のイオン種を用いて
もよい。またゲート電極７の材料としては、Ｍｏ以外に
Ｗ等の他の種類の高融点金属や高融点金属ケイ化物等を
用いることも可能である。Although one embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment, but is based on the technical idea of the present invention (various modifications are possible. For example, polycrystalline silicon As the ion species for ion implantation to make the film 2 amorphous, ions of an electrically inert element such as F' may be used in addition to Si'' used in the above embodiment. Further, the ion species of the implanted impurities for forming the source region 9 and the drain region 10 are not limited to P' used in the above embodiment, and other types of ion species may be used as necessary. In addition to Mo, other types of high melting point metals such as W, high melting point metal silicides, etc. can also be used as the material for the gate electrode 7.

さらに必要に応じて多結晶シリコン膜２の代わりに他の
種類の多結晶半導体薄膜を用いることも可能である。Furthermore, it is also possible to use other types of polycrystalline semiconductor thin films instead of polycrystalline silicon film 2, if necessary.

発明の効果 本発明に係る薄膜トランジスタの製造方法によれば、従
来のように固相成長のための熱処理とソース領域及びド
レイン領域形成用の不純物を電気的に活性化するための
熱処理とを別々に行う必要がないので、従来に比べて製
造工程を簡略化することができる。またソース領域及び
ドレイン領域中の不純物の活性化率を従来に比べてより
均一とすることが可能である。Effects of the Invention According to the method for manufacturing a thin film transistor according to the present invention, heat treatment for solid phase growth and heat treatment for electrically activating impurities for forming source and drain regions can be performed separately, unlike conventional methods. Since there is no need to carry out this process, the manufacturing process can be simplified compared to the conventional method. Furthermore, it is possible to make the activation rate of impurities in the source region and the drain region more uniform than in the past.

【図面の簡単な説明】[Brief explanation of drawings]

第１Ａ図〜第１Ｃ図は本発明に係る薄膜トランジスタの
製造方法をｎチャネル多結晶シリコンＴＰＴの製造に適
用した一実施例を工程順に示す断面図、第２Ａ図〜第２
Ｇ図は従来の低温プロセスによる多結晶シリコンＴＰＴ
の製造方法を工程順に示す断面図である。 なお図面に用いた符号において、 １−・・−−一−−・−・−−−−−ガラス基板２、、
Ｌ−−−・−・−−−−一多結晶シリコン膜３−・−・
−・−・−・・−非晶質シリコン膜７−・−−−−−・
・−・・・−・−ゲート電極８−〜−−−−−−−−−
−−−−・・−ゲート絶縁膜９−〜−−・−・−・−・
−・−・・ソース領域１０・−−−一−−−−−−−−
−−ドレイン領域である。1A to 1C are cross-sectional views showing, in order of process, an embodiment in which the method for manufacturing a thin film transistor according to the present invention is applied to the manufacture of an n-channel polycrystalline silicon TPT, and FIGS.
Figure G shows polycrystalline silicon TPT produced by conventional low-temperature process.
FIG. In addition, in the symbols used in the drawings, 1-...--1---------Glass substrate 2,,
L----------- polycrystalline silicon film 3---
−・−・−・・−Amorphous silicon film 7 −・−−−−−・
・−・・・−・−Gate electrode 8−−−−−−−−−
−−−−・・−Gate insulating film 9−−−−・−・−・−・
−・−・Source area 10・−−−−−−
--Drain region.

Claims (1)

【特許請求の範囲】[Claims] 　所定の基板上に多結晶の半導体薄膜を形成する工程と
、上記多結晶の半導体薄膜に所定のイオンをイオン注入
することにより非晶質の半導体薄膜を形成する工程と、
上記非晶質の半導体薄膜上にゲート絶縁膜及びゲート電
極を形成する工程と、上記ゲート電極及び上記ゲート絶
縁膜をマスクとして上記非晶質の半導体薄膜にソース領
域及びドレイン領域形成用の不純物を導入する工程と、
熱処理を行うことにより上記非晶質の半導体薄膜を固相
成長させると共に上記不純物を電気的に活性化させて上
記ソース領域及び上記ドレイン領域を形成する工程とを
それぞれ具備することを特徴とする薄膜トランジスタの
製造方法。forming a polycrystalline semiconductor thin film on a predetermined substrate; forming an amorphous semiconductor thin film by implanting predetermined ions into the polycrystalline semiconductor thin film;
A step of forming a gate insulating film and a gate electrode on the amorphous semiconductor thin film, and using the gate electrode and the gate insulating film as a mask, impurities for forming a source region and a drain region are added to the amorphous semiconductor thin film. The process to introduce and
A thin film transistor comprising the steps of growing the amorphous semiconductor thin film in a solid phase by performing heat treatment and electrically activating the impurity to form the source region and the drain region. manufacturing method.
JP59241239A 1984-11-15 1984-11-15 Method for manufacturing thin film transistor Expired - Lifetime JPH0824184B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP59241239A JPH0824184B2 (en) 1984-11-15 1984-11-15 Method for manufacturing thin film transistor
KR1019850007608A KR930010978B1 (en) 1984-11-15 1985-10-16 Manufacturing method of thin film transistor
GB08527737A GB2167899B (en) 1984-11-15 1985-11-11 Methods of manufacturing thin film transistors
NL8503123A NL194524C (en) 1984-11-15 1985-11-13 Method for manufacturing a thin film transistor.
DE3540452A DE3540452C2 (en) 1984-11-15 1985-11-14 Method of manufacturing a thin film transistor
FR858516906A FR2573248B1 (en) 1984-11-15 1985-11-15 PROCESS FOR MANUFACTURING A THIN FILM TRANSISTOR AND TRANSISTOR THUS MANUFACTURED
CN198585109088A CN85109088A (en) 1984-11-15 1985-11-15 The manufacture method of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59241239A JPH0824184B2 (en) 1984-11-15 1984-11-15 Method for manufacturing thin film transistor

Publications (2)

Publication Number Publication Date
JPS61119079A true JPS61119079A (en) 1986-06-06
JPH0824184B2 JPH0824184B2 (en) 1996-03-06

Family

ID=17071271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59241239A Expired - Lifetime JPH0824184B2 (en) 1984-11-15 1984-11-15 Method for manufacturing thin film transistor

Country Status (7)

Country Link
JP (1) JPH0824184B2 (en)
KR (1) KR930010978B1 (en)
CN (1) CN85109088A (en)
DE (1) DE3540452C2 (en)
FR (1) FR2573248B1 (en)
GB (1) GB2167899B (en)
NL (1) NL194524C (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242507A (en) * 1989-04-05 1993-09-07 Boston University Impurity-induced seeding of polycrystalline semiconductors
US5347146A (en) * 1991-12-30 1994-09-13 Goldstar Co., Ltd. Polysilicon thin film transistor of a liquid crystal display
US7952097B2 (en) 1993-02-15 2011-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242858A (en) * 1990-09-07 1993-09-07 Canon Kabushiki Kaisha Process for preparing semiconductor device by use of a flattening agent and diffusion
JP3556679B2 (en) * 1992-05-29 2004-08-18 株式会社半導体エネルギー研究所 Electro-optical device
US5403756A (en) * 1991-11-20 1995-04-04 Sharp Kabushiki Kaisha Method of producing a polycrystalline semiconductor film without annealing, for thin film transistor
JP3587537B2 (en) * 1992-12-09 2004-11-10 株式会社半導体エネルギー研究所 Semiconductor device
KR100612853B1 (en) * 2004-07-21 2006-08-14 삼성전자주식회사 Si based material layer having wire type silicide and method of forming the same
CN104409635B (en) 2014-12-16 2017-02-22 京东方科技集团股份有限公司 Organic thin film transistor and manufacturing method thereof, array substrate, and display unit

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Publication number Priority date Publication date Assignee Title
JPS558026A (en) * 1978-06-30 1980-01-21 Matsushita Electric Ind Co Ltd Semi-conductor device manufacturing method
JPS59165451A (en) * 1983-03-11 1984-09-18 Toshiba Corp Manufacture of semiconductor device

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Publication number Priority date Publication date Assignee Title
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
JPS5856409A (en) * 1981-09-30 1983-04-04 Toshiba Corp Production of semiconductor device
JPS61191070A (en) * 1985-02-20 1986-08-25 Toshiba Corp Manufacture of semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS558026A (en) * 1978-06-30 1980-01-21 Matsushita Electric Ind Co Ltd Semi-conductor device manufacturing method
JPS59165451A (en) * 1983-03-11 1984-09-18 Toshiba Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5242507A (en) * 1989-04-05 1993-09-07 Boston University Impurity-induced seeding of polycrystalline semiconductors
US5347146A (en) * 1991-12-30 1994-09-13 Goldstar Co., Ltd. Polysilicon thin film transistor of a liquid crystal display
US7952097B2 (en) 1993-02-15 2011-05-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
GB2167899B (en) 1988-04-27
KR860004455A (en) 1986-06-23
JPH0824184B2 (en) 1996-03-06
NL194524B (en) 2002-02-01
GB8527737D0 (en) 1985-12-18
NL8503123A (en) 1986-06-02
CN85109088A (en) 1986-08-27
NL194524C (en) 2002-06-04
KR930010978B1 (en) 1993-11-18
DE3540452A1 (en) 1986-06-05
FR2573248A1 (en) 1986-05-16
FR2573248B1 (en) 1991-06-21
GB2167899A (en) 1986-06-04
DE3540452C2 (en) 1999-07-29

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