JPS61127117A - Method for forming polycrystalline semiconductor thin film - Google Patents
Method for forming polycrystalline semiconductor thin filmInfo
- Publication number
- JPS61127117A JPS61127117A JP59248343A JP24834384A JPS61127117A JP S61127117 A JPS61127117 A JP S61127117A JP 59248343 A JP59248343 A JP 59248343A JP 24834384 A JP24834384 A JP 24834384A JP S61127117 A JPS61127117 A JP S61127117A
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- Prior art keywords
- thin film
- crystal grains
- film
- polycrystalline
- semiconductor thin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02513—Microstructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は多結晶半導体薄膜の形成方法に関するものであ
って、結晶粒の大きい多結晶シリコン膜を絶縁体基板上
に形成するのに用いて最適なものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming a polycrystalline semiconductor thin film, which method is most suitable for forming a polycrystalline silicon film with large crystal grains on an insulating substrate. It is something.
従来の技術
従来、結晶粒の大きい多結晶シリコン膜を絶縁体基板上
に形成するためには次のような方法が用いられている。2. Description of the Related Art Conventionally, the following method has been used to form a polycrystalline silicon film with large crystal grains on an insulating substrate.
すなわち、第３Ａ図に示すように、まず例えば石英基板
１上に形成されているＳｉＯ□膜２上にＬＰＣＶＤ法に
より多結晶シリコン膜３を被着形成し、次いでＳｔ＋等
をイオン注入することによりこの多結晶シリコン膜３を
非晶質化させて第３Ｂ図に示すように非晶質シリコン膜
４を形成した後、６００℃程度の温度でアニールを行う
ことにより固相成長による再結晶化を行う。この再結晶
の際には、第３Ｂ図に示すように、まず非晶質シリコン
膜４中に核５が形成され、次いでこの核５を基にして矢
印方向に結晶化が進行する。その結果、第３Ｃ図に示す
ように、最初に形成した多結晶シリコン膜３よりも粒径
が大きい結晶粒６を有する多結晶シリコン膜７が形成さ
れる。That is, as shown in FIG. 3A, a polycrystalline silicon film 3 is first deposited on a SiO□ film 2 formed on a quartz substrate 1 by the LPCVD method, and then St+ or the like is ion-implanted. After amorphizing this polycrystalline silicon film 3 to form an amorphous silicon film 4 as shown in FIG. 3B, recrystallization by solid phase growth is performed by annealing at a temperature of about 600°C. conduct. During this recrystallization, as shown in FIG. 3B, a nucleus 5 is first formed in the amorphous silicon film 4, and then crystallization progresses in the direction of the arrow based on this nucleus 5. As a result, as shown in FIG. 3C, a polycrystalline silicon film 7 having crystal grains 6 having a larger grain size than the initially formed polycrystalline silicon film 3 is formed.
この方法によれば、粒径が比較的大きい結晶粒６を得る
ことができるが、この方法では非晶質シリコン膜４中に
核５がランダムに形成されるので、従来よりも粒径がさ
らに大きい結晶粒６を得ることは難しい。従って、上記
多結晶シリコン膜７を用いて薄膜トランジスタ（ＴＰＴ
）を構成する場合、移動度をより高くして特性を向上さ
せることは難しい。According to this method, crystal grains 6 having a relatively large grain size can be obtained, but since the nuclei 5 are randomly formed in the amorphous silicon film 4 in this method, the grain size is even larger than that of the conventional method. It is difficult to obtain large crystal grains 6. Therefore, using the polycrystalline silicon film 7, thin film transistor (TPT)
), it is difficult to improve the characteristics by increasing the mobility.
なおＴＰＴに関する先行文献としては、日本応用物理学
会学術講演会予稿集、１４ｐ−Ａ−４〜１４ｐ−Ａ−６
（１９８４）が挙げられる。Prior literature regarding TPT includes the proceedings of the Japan Society of Applied Physics Academic Conference, 14p-A-4 to 14p-A-6.
(1984).
発明が解決しようとする問題点
本発明は、上述の問題にかんがみ、従来の多結晶半導体
薄膜の形成方法が有する上述のような欠点を是正した多
結晶半導体薄膜の形成方法を提供することを目的とする
。Problems to be Solved by the Invention In view of the above-mentioned problems, an object of the present invention is to provide a method for forming a polycrystalline semiconductor thin film that corrects the above-mentioned drawbacks of conventional methods for forming a polycrystalline semiconductor thin film. shall be.
問題点を解決するための手段
本発明に係る多結晶半導体薄膜の形成方法は、熱処理に
より結晶粒に分断可能な第１の半導体薄膜（例えば多結
晶シリコン膜３）を所定の基板（例えば石英基板１）上
に形成する工程と、熱処理を行うことにより上記第１の
半導体薄膜を分断させて結晶粒（例えばシリコンの結晶
粒８）を形成する工程と、上記結晶粒を被覆する第２の
半導体薄膜（例えば多結晶シリコン膜１０）を形成する
工程と、上記第２の半導体薄膜に所定のイオン（例えば
Ｓｉ’ ）をイオン注入することにより非晶質の半導体
層（例えば非晶質シリコン層１１）を形成する工程と、
熱処理を行うことにより上記非晶質の半導体層を上記結
晶粒を種結晶として同相エピタキシャル成長させる工程
とをそれぞれ具備している。Means for Solving the Problems The method for forming a polycrystalline semiconductor thin film according to the present invention involves depositing a first semiconductor thin film (for example, a polycrystalline silicon film 3) that can be divided into crystal grains by heat treatment on a predetermined substrate (for example, a quartz substrate). 1) A step of forming a semiconductor thin film on top, a step of dividing the first semiconductor thin film by heat treatment to form crystal grains (for example, silicon crystal grains 8), and a second semiconductor covering the crystal grains. An amorphous semiconductor layer (for example, the amorphous silicon layer 11 ),
and a step of performing in-phase epitaxial growth of the amorphous semiconductor layer using the crystal grains as seed crystals by performing heat treatment.
実施例
実施例を述べる前に本発明を案出するに至った背景を述
べる。すなわち、本発明者等は、石英基板等の上に膜厚
が１００〜３００人程度の多結晶シリコン膜を形成し、
次いでこの多結晶シリコン膜をエツチングにより所定形
状（アイランド状）とした後、Ｎ２雰囲気において１０
００℃で数時間アニールを行うと、この多結晶シリコン
膜が微小な結晶粒に分断される現象を観察した。従って
、この結晶粒を種結晶として再結晶を行えば、従来に比
べて結晶粒の粒径が大きい多結晶シリコン膜が得られる
との考えに至ったものである。なお上述のように多結晶
シリコン膜が結晶粒に分断される現象は、一種の二次的
結晶粒成長であり、これは表面エネルギーを最小化する
ために起こるものと考えられる。Embodiments Before describing embodiments, the background behind the invention of the present invention will be described. That is, the present inventors formed a polycrystalline silicon film with a thickness of about 100 to 300 nm on a quartz substrate or the like,
Next, this polycrystalline silicon film was etched into a predetermined shape (island shape), and then etched for 10 minutes in an N2 atmosphere.
When annealing was performed at 00° C. for several hours, a phenomenon was observed in which this polycrystalline silicon film was divided into minute crystal grains. Therefore, we have come up with the idea that if recrystallization is performed using these crystal grains as seed crystals, a polycrystalline silicon film with larger crystal grain sizes than before can be obtained. Note that the phenomenon in which a polycrystalline silicon film is divided into crystal grains as described above is a type of secondary crystal grain growth, and this is thought to occur in order to minimize surface energy.
以下本発明に係る多結晶半導体薄膜の形成方法を多結晶
シリコンＴＰＴの製造に適用した一実施例につき図面を
参照しながら説明する。なお以下の第１Ａ図〜第１Ｌ図
においては、第３Ａ図〜第３Ｃ図と同一部分には同一の
符号を付し、必要に応じてその説明を省略する。An embodiment in which the method for forming a polycrystalline semiconductor thin film according to the present invention is applied to manufacturing a polycrystalline silicon TPT will be described below with reference to the drawings. In the following FIGS. 1A to 1L, the same parts as in FIGS. 3A to 3C are denoted by the same reference numerals, and the explanation thereof will be omitted if necessary.
まず第１Ａ図に示すように、石英基板１上にＳｉｎｇ膜
２を被着形成し、次いでこの５ｉＯｚ膜２上に膜厚が１
００〜３００人程度の多結晶シリコン膜３をＬＰＣＶＤ
法により被着形成する。First, as shown in FIG. 1A, a Sing film 2 is deposited on a quartz substrate 1, and then a film thickness of 1 is deposited on this 5iOz film 2.
LPCVD polycrystalline silicon film 3 of about 00 to 300
Adhesion is formed by the method.
次に上記多結晶シリコン膜３の所定部分をエツチング除
去して、第１Ｂ図に示すように所定形状とする。Next, a predetermined portion of the polycrystalline silicon film 3 is removed by etching to obtain a predetermined shape as shown in FIG. 1B.
次にＮ２雰囲気中において１０００℃で数時間アニール
を行う。このアニールにより、上記多結晶シリコン膜３
は、第１Ｃ図に示すように多数の結晶粒８に分断される
。Next, annealing is performed at 1000° C. for several hours in an N2 atmosphere. By this annealing, the polycrystalline silicon film 3
is divided into many crystal grains 8 as shown in FIG. 1C.
次に第１Ｄ図に示すように、上記結晶粒８を覆うように
してレジスト９を全面に塗布する。Next, as shown in FIG. 1D, a resist 9 is applied to the entire surface so as to cover the crystal grains 8.
次にレジスト９を所定厚さだけラッピングにより研削し
て、第１Ｅ図に示すように、各結晶粒８の表面を平坦化
する。Next, the resist 9 is ground by lapping to a predetermined thickness to flatten the surface of each crystal grain 8, as shown in FIG. 1E.
次にレジスト９を除去した後、第１Ｆ図に示すように全
面に例えば膜厚８００人の多結晶シリコン膜１０を被着
形成する。After removing the resist 9, a polycrystalline silicon film 10 having a thickness of, for example, 800 wafers is deposited over the entire surface as shown in FIG. 1F.
次に上記結晶粒８に実質的に損傷を与えないような条件
で上記多結晶シリコン膜１０にＳｉｏ等のイオン注入を
行うことにより、第１Ｇ図に示すように、この多結晶シ
リコン膜１０をその最下部を除いて非晶質シリコン層１
１とした後、６００℃程度の温度でアニールを行う。こ
のアニールにより、上記非晶質シリコン層１１は上記結
晶粒８を種結晶として固相エピタキシャル成長により再
結晶し、その結果、第１Ｈ図に示すように多結晶シ・リ
コン膜７が形成される。この再結晶の様子を詳述すると
、第１Ｆ図に示す状態においては、第２Ａ図に示すよう
に多結晶シリコン膜１０中の結晶粒６の粒径は小さいが
、アニールにより、結晶粒８を種結晶として固相エピタ
キシャル成長による再結晶が起きて次第に大きな結晶粒
へと成長するため、第１Ｈ図に示す状態においては、第
２Ｂ図に示すように、多結晶シリコン膜７中の結晶粒６
の大きさは極めて大きくな る。Next, by implanting ions such as Sio into the polycrystalline silicon film 10 under conditions that do not substantially damage the crystal grains 8, this polycrystalline silicon film 10 is formed as shown in FIG. 1G. Amorphous silicon layer 1 except for its bottom part
1, and then annealing is performed at a temperature of about 600°C. By this annealing, the amorphous silicon layer 11 is recrystallized by solid phase epitaxial growth using the crystal grains 8 as seed crystals, and as a result, a polycrystalline silicon film 7 is formed as shown in FIG. 1H. To explain this recrystallization in detail, in the state shown in FIG. 1F, the grain size of the crystal grains 6 in the polycrystalline silicon film 10 is small as shown in FIG. 2A, but due to annealing, the crystal grains 8 are Since recrystallization occurs by solid-phase epitaxial growth as a seed crystal and gradually grows into larger crystal grains, in the state shown in FIG. 1H, as shown in FIG. 2B, the crystal grains 6 in the polycrystalline silicon film 7
becomes extremely large.
次に第１１図に示すように、この多結晶シリコン膜７を
エツチングにより所定形状とした後、全面ニＳ ｉ Ｏ
２膜１２及びＤＯＰＯ５膜１３（不純物をドープした多
結晶シリコン膜）を順次被着形成し、次いでこれらのＤ
ＯＰＯ３膜１３及びＳｉＯ□膜１２の所定部分を順次エ
ツチング除去して、第１Ｊ図に示すように所定形状のＤ
ＯＰＯ３膜から成るゲート電極１４及び所定形状のＳｉ
Ｏ□膜から成るゲート絶縁膜１５を形成する。Next, as shown in FIG. 11, after etching this polycrystalline silicon film 7 into a predetermined shape, the entire surface is etched with SiO.
2 film 12 and DOPO5 film 13 (polycrystalline silicon film doped with impurities) are deposited in sequence, and then these D
Predetermined portions of the OPO3 film 13 and the SiO□ film 12 are sequentially removed by etching to form a predetermined shape
Gate electrode 14 made of OPO3 film and Si of a predetermined shape
A gate insulating film 15 made of an O□ film is formed.
次に第１Ｋ図に示すように、全面にＰＳＧ膜１６を被着
形成した後、１０００°Ｃ程度の温度でアニールを行う
ことにより上記ＰＳＧ膜１膜中６中まれているリン（Ｐ
）を多結晶シリコン膜７に拡散させて、ｎ″″型のソー
ス領域１７及びドレイン領域１８を形成する。Next, as shown in FIG. 1K, after forming a PSG film 16 on the entire surface, annealing is performed at a temperature of about 1000°C.
) is diffused into the polycrystalline silicon film 7 to form an n″″ type source region 17 and drain region 18.
この後、第１Ｌ図に示すように、ＰＳＧ膜１６の所定部
分をエツチング除去して開口１６ａ。Thereafter, as shown in FIG. 1L, a predetermined portion of the PSG film 16 is removed by etching to form an opening 16a.
１６ｂを形成し、次いでこれらの開口１６ａ。16b and then these openings 16a.
１６ｂを通じて＾２から成る電極１９．２０を被着形成
して、目的とするｎチャネル多結晶シリコンＴＰＴを完
成させる。Electrodes 19 and 20 made of ^2 are deposited through the electrodes 16b to complete the intended n-channel polycrystalline silicon TPT.
上述の実施例によれば、第１Ｂ図に示す工程において所
定のアニールを行うことにより多結晶シリコン膜３を分
断させて得られたシリコンの結晶粒８の上部を研削して
平坦化した後、全面に多結晶シリコン膜１０を形成し、
次いでこの多結晶シリコン膜ｌＯにＳｔ”をイオン注入
することにより非晶質シリコン層１１を形成し、この後
アニールを行うことによりこの非晶質シリコン層１１を
上記結晶粒８を種結晶として同相エピタキシャル成長さ
せているので、得られる多結晶シリコン膜７中の結晶粒
６の大きさを既述のように従来に比べて大きくすること
ができる。従って、この多結晶シリコン膜７を用いて形
成された上述の実施例によるＴＰＴは、キャリアの移動
度が高くて特性が極めて良好である。According to the above-described embodiment, in the step shown in FIG. 1B, after the upper portions of the silicon crystal grains 8 obtained by dividing the polycrystalline silicon film 3 by performing a predetermined annealing are ground and flattened, A polycrystalline silicon film 10 is formed on the entire surface,
Next, an amorphous silicon layer 11 is formed by ion-implanting St'' into this polycrystalline silicon film lO, and then annealing is performed to form this amorphous silicon layer 11 in the same phase using the crystal grains 8 as seed crystals. Since epitaxial growth is performed, the size of the crystal grains 6 in the resulting polycrystalline silicon film 7 can be made larger than in the conventional method, as described above. The TPT according to the above embodiment has high carrier mobility and extremely good characteristics.
以上本発明を実施例につき説明したが、本発明は上述の
実施例に限定されるものではなく、本発明の技術的思想
に基づく種々の変形が可能である。Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.
例えば、上述の実施例においては、第１Ｅ図に示す工程
において研削により結晶粒８の表面を平坦化したが、第
１Ｃ図に示す工程終了後に多結晶シリコン膜１０を形成
し、次いで第１Ｆ図〜第１Ｈ図のいずれかの工程におい
て平坦化を行うことも可能である。また上述の実施例に
おいては、結晶粒８をレジスト９で被覆した後に研削す
ることにより平坦化を行ったが、例えばレジスト９を形
成後にこのレジスト９とシリコンの結晶粒８とのエツチ
ング速度をそろえた後に反応性イオンエツチング（ＲＩ
Ｅ）等を行うことにより平坦化することも可能である
。さらに必要に応して多結晶シリコン膜３の代わりに、
熱処理により結晶粒に分断可能な他の種類の半導体薄膜
を用いることも可能である。また石英基板１の代わりに
、ガラス基板等を用いることも可能である。For example, in the above embodiment, the surface of the crystal grain 8 was flattened by grinding in the step shown in FIG. 1E, but after the step shown in FIG. It is also possible to perform planarization in any of the steps shown in FIGS. Further, in the above-described embodiment, the crystal grains 8 were coated with a resist 9 and then ground to achieve flattening. After that, reactive ion etching (RI)
It is also possible to flatten the surface by performing E) or the like. Furthermore, if necessary, instead of the polycrystalline silicon film 3,
It is also possible to use other types of semiconductor thin films that can be broken into grains by heat treatment. Further, instead of the quartz substrate 1, it is also possible to use a glass substrate or the like.
発明の効果
本発明に係る多結晶半導体薄膜の形成方法によれば、結
晶粒の大きさが従来に比べて大きい多結晶半導体薄膜を
形成することができる。従って、この多結晶半導体薄膜
を用いて、特性が良好な薄膜半導体装置を形成すること
が可能である。Effects of the Invention According to the method for forming a polycrystalline semiconductor thin film according to the present invention, it is possible to form a polycrystalline semiconductor thin film in which the size of crystal grains is larger than that of the conventional method. Therefore, using this polycrystalline semiconductor thin film, it is possible to form a thin film semiconductor device with good characteristics.
第１Ａ図〜第１Ｌ図は本発明に係る多結晶半導体薄膜の
形成方法を多結晶シリコンＴＰＴの製造に適用した一実
施例を工程順に示す断面図、第２Ａ図及び第２Ｂ図は多
結晶シリコン膜の分断により形成された結晶粒を種結晶
として大きな結晶粒が形成される様子を説明するための
第１Ｆ図及び第１Ｈ図に対応する拡大断面図、第３Ａ図
〜第３Ｃ図は従来の多結晶シリコン膜の形成方法を工程
順に示す断面図である。
なお図面に用いた符号において、
１・・＝−・・−−−−−ｍ−・−石英基板２−−−−
−・・・−−−−−−−−−−−５ｉ Ｏ□膜３ 、７
、１０−−−−−−・−・−多結晶シリコン膜５−−
−−−・・・・−・−・−核
６ 、８−・−・・−−一一−−−−−結晶粒１１−−
−−−−−−−・・・−・−非晶質シリコン層１４−−
−−−−−−−−・・−・・ゲート電極１５−〜−−−
・・−−一−−−−−−−−−ゲート絶縁膜１７・・−
・−−−−−−一・・−・−ソース領域１ Ｂ−−−−
−−・−−一−−−−−−−−−ドレイン領域である。1A to 1L are cross-sectional views showing step-by-step an embodiment in which the method for forming a polycrystalline semiconductor thin film according to the present invention is applied to the production of polycrystalline silicon TPT, and FIGS. 2A and 2B are cross-sectional views of polycrystalline silicon TPT. The enlarged cross-sectional views corresponding to FIGS. 1F and 1H, and FIGS. 3A to 3C are for explaining how large crystal grains are formed using crystal grains formed by dividing the film as seed crystals, and FIGS. 3A to 3C are conventional FIG. 3 is a cross-sectional view showing a method for forming a polycrystalline silicon film in order of steps. In addition, in the symbols used in the drawings, 1..=-..--m-.-quartz substrate 2--
−・・・−−−−−−−−−−5i O□ film 3, 7
, 10-----Polycrystalline silicon film 5--
−−−・・−・−・−Nuclei 6, 8−・−・・−−11−−−−−Crystal grain 11−−
−−−−−−−・・・−・−Amorphous silicon layer 14−−
−−−−−−−−・・−・Gate electrode 15−−−−−
・・−−1−−−−−−−−Gate insulating film 17・・−
・--------1...-- Source region 1 B----
--------------This is the drain region.
Claims (1)
所定の基板上に形成する工程と、熱処理を行うことによ
り上記第１の半導体薄膜を分断させて結晶粒を形成する
工程と、上記結晶粒を被覆する第２の半導体薄膜を形成
する工程と、上記第２の半導体薄膜に所定のイオンをイ
オン注入することにより非晶質の半導体層を形成する工
程と、熱処理を行うことにより上記非晶質の半導体層を
上記結晶粒を種結晶として固相エピタキシャル成長させ
る工程とをそれぞれ具備することを特徴とする多結晶半
導体薄膜の形成方法。a step of forming on a predetermined substrate a first semiconductor thin film that can be divided into crystal grains by heat treatment; a step of dividing the first semiconductor thin film by performing heat treatment to form crystal grains; and a step of forming crystal grains by performing heat treatment. a step of forming a second semiconductor thin film covering the second semiconductor thin film, a step of forming an amorphous semiconductor layer by implanting predetermined ions into the second semiconductor thin film, and a step of forming an amorphous semiconductor layer by performing heat treatment. A method for forming a polycrystalline semiconductor thin film, comprising the steps of solid-phase epitaxial growth of a high-quality semiconductor layer using the crystal grains as seed crystals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248343A JPS61127117A (en) | 1984-11-24 | 1984-11-24 | Method for forming polycrystalline semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59248343A JPS61127117A (en) | 1984-11-24 | 1984-11-24 | Method for forming polycrystalline semiconductor thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61127117A true JPS61127117A (en) | 1986-06-14 |
Family
ID=17176672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59248343A Pending JPS61127117A (en) | 1984-11-24 | 1984-11-24 | Method for forming polycrystalline semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61127117A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2627012A1 (en) * | 1988-02-10 | 1989-08-11 | France Etat | PROCESS FOR DEPOSITING A LARGE GRAIN POLYCRYSTALLINE LAYER, LAYER OBTAINED AND TRANSISTOR PROVIDED WITH SUCH A LAYER |
| EP0339741A2 (en) * | 1988-04-28 | 1989-11-02 | ENVEC Mess- und Regeltechnik GmbH + Co. | Process of manufacturing a polycrystalline semiconductor resistance of silicon on a silicon substrate |
| JPH01289240A (en) * | 1988-05-17 | 1989-11-21 | Seiko Epson Corp | Formation of soi |
| JPH0311618A (en) * | 1989-06-08 | 1991-01-18 | Canon Inc | Crystalline semiconductor film and forming method thereof |
| JPH0370123A (en) * | 1989-08-10 | 1991-03-26 | Canon Inc | Formation of crystalline semiconductor film |
-
1984
- 1984-11-24 JP JP59248343A patent/JPS61127117A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2627012A1 (en) * | 1988-02-10 | 1989-08-11 | France Etat | PROCESS FOR DEPOSITING A LARGE GRAIN POLYCRYSTALLINE LAYER, LAYER OBTAINED AND TRANSISTOR PROVIDED WITH SUCH A LAYER |
| EP0339741A2 (en) * | 1988-04-28 | 1989-11-02 | ENVEC Mess- und Regeltechnik GmbH + Co. | Process of manufacturing a polycrystalline semiconductor resistance of silicon on a silicon substrate |
| JPH01289240A (en) * | 1988-05-17 | 1989-11-21 | Seiko Epson Corp | Formation of soi |
| JPH0311618A (en) * | 1989-06-08 | 1991-01-18 | Canon Inc | Crystalline semiconductor film and forming method thereof |
| JPH0370123A (en) * | 1989-08-10 | 1991-03-26 | Canon Inc | Formation of crystalline semiconductor film |
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