JPS61119073A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS61119073A
JPS61119073A JP59241004A JP24100484A JPS61119073A JP S61119073 A JPS61119073 A JP S61119073A JP 59241004 A JP59241004 A JP 59241004A JP 24100484 A JP24100484 A JP 24100484A JP S61119073 A JPS61119073 A JP S61119073A
Authority
JP
Japan
Prior art keywords
circuit
input
output
diode
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59241004A
Other languages
Japanese (ja)
Inventor
Yasunobu Okano
岡野　安伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59241004A priority Critical patent/JPS61119073A/en
Publication of JPS61119073A publication Critical patent/JPS61119073A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To enable the protection of an input and output mixed circuit from static electricity by connecting an input circuit and an output circuit by a high resistance and adding them between a protective diode between a leading electrode and a high potential level of a power source, and the input circuit. CONSTITUTION:An inverter circuit input circuit is composed of a P-channel MOS transistor TP1 and an N-channel MOS transistor TN1 and a diode D3 is connected between a gate input and a VDD terminal. The gate input of the inverter circuit is further connected to an open drain output of the N-channel MOS transistor as an output circuit through a high resistor R. A diode D4 is connected between the leading electrode 1 which can become an input terminal and a low potential level of a power source (GND level). When the N- channel MOS transistor TN2 operates, the function of N-channel transistor TN2 is kept in a normal operating state by restriction of current because the resistor R2 is a high resistance.

Description

【発明の詳細な説明】 （良業上の利用分動） 本発明はＭＯＳ）ランジスタを有する集積（ロ）路に胸
し、特にＭｏｓト’ｙンジスタを静電気等の外来サージ
電圧に対して保護する保護回路を有するＭＯ８集積回路
に関する。DETAILED DESCRIPTION OF THE INVENTION (Commercial Application) The present invention is applicable to integrated circuits having MOS transistors, and in particular protects MOS transistors from external surge voltages such as static electricity. The present invention relates to an MO8 integrated circuit having a protection circuit.

（従来の技術） 従来の静電気保護回路は、第２図に示すように引出し電
極１に対して、抵抗Ｒ１と各々の電源電位（高電位、低
電位）供給端子に対して設けられたダイオードＤ、、Ｄ
、とを有し、これによって内部回路を保護しているのが
一般的である。この構成では、電極１が入力端子として
これにつながる入力回路だけを、あるいは出力端子とし
てこれにつながる出力回路だけをそれぞれ単独に保護す
る場合、その保護機能充分なものであって優れている。(Prior Art) As shown in FIG. 2, a conventional electrostatic protection circuit includes a resistor R1 and a diode D provided for each power supply potential (high potential, low potential) supply terminal for the extraction electrode 1. ,,D
, and generally protect the internal circuit. This configuration is excellent in that the protection function is sufficient when the electrode 1 protects only the input circuit connected thereto as an input terminal, or only the output circuit connected thereto as an output terminal.

しかし、第２図に示すように電極ｌを入出力端子として
これに入力回路（ＰチャネルＭＯＳトランジスタＴＰＩ
とＮチャネルＭＯ８）ランジスタＴＮＩで構成されたイ
ンバータ回路）と出力回路（ＮチャネルＭＯ８）ランジ
スタＴＮ２のオープンドレイン回路）との両方が組合さ
った回路の保護に関しては、問題が生じる。However, as shown in FIG.
A problem arises with respect to the protection of a circuit in which both the N-channel MO8) (an inverter circuit formed by the transistor TNI) and the output circuit (the open-drain circuit of the transistor TN2 (N-channel MO8)) are combined.

（発明が触法しようとする問題点） すなわち、トランジスタＴＮ２のオープンドレイン出力
を出力回路機能として使用する場合、一般には、単ＭＯ
８）ランジスタ回路の利点を生かして出力回路の外部負
荷としては、電源電圧よりも高電位な負荷も使用出来る
様に単ＭＯＳトランジスタＴＮ２の設計が成されている
のが一般的である。従来の保論回路を使用すると、第２
図の回路が出力回路として動作した場合（Ｎチャネルト
ランジスタ）ＴＮｚ　が動作状態となる）、引出し電極
ｌには電源電圧（ＶＤＤレベル）よりも高い電位（＞Ｖ
ＤＤ　）が印加されることになり、この結果、ダイオー
ドＤ１を通してＶＤＤ側へ大電流が流れて出力回路機能
が誤動作する。一方ダイオードＤ１を削除するとＶＤＤ
に対する保護が無くなるため静電気に弱くなる。(Problem to be addressed by the invention) In other words, when using the open drain output of transistor TN2 as an output circuit function, generally a single MO
8) Taking advantage of the advantages of the transistor circuit, a single MOS transistor TN2 is generally designed so that a load with a higher potential than the power supply voltage can be used as an external load of the output circuit. Using the conventional theory circuit, the second
When the circuit in the figure operates as an output circuit (N-channel transistor TNz is in operation), the extraction electrode l has a potential (>V) higher than the power supply voltage (VDD level).
DD ) is applied, and as a result, a large current flows through the diode D1 to the VDD side, causing the output circuit function to malfunction. On the other hand, if diode D1 is removed, VDD
Since there is no protection against static electricity, it becomes vulnerable to static electricity.

本発明の目的は保護ダイオードを通して電流が流れても
、出力回路機能が語動作を生じない保護回路を提供する
ものである。An object of the present invention is to provide a protection circuit in which the output circuit function does not cause a word operation even if current flows through the protection diode.

（問題点を解決するための手段） 本発明は、入力回路と出力回路の間を高抵抗で結合し引
出し電極と電源の高電位レベル間の保護ダイオードを高
抵抗と入力回路間に付加したことを特徴とする。(Means for solving the problem) The present invention connects the input circuit and the output circuit with a high resistance, and adds a protection diode between the extraction electrode and the high potential level of the power source between the high resistance and the input circuit. It is characterized by

（実施例） 以下、本発明の一実施例を示す第１図について詳述する
。ＰチャネルＭＯ８）ランジスタＴＰｌとＮチャネルＭ
Ｏ８）ツンジスタＴＮ□とで構成されたインバータ回路
は入力回路を構成し、このゲート入力と％　ＶＤＤ端子
との間にダイオードＤ３か接続されている。インバータ
回路のゲート入力は、出力回路としてのＮチャネルＭＯ
８）ランジスタのオープンドレイン出力に高抵抗几、を
介してさらに結合されている。入力端子となり得る引出
し電極１と電源の低電位レベル（ＧＮＤレベル）との間
にダイオードＤ４が接続されている。(Example) Hereinafter, FIG. 1 showing an example of the present invention will be described in detail. P-channel MO8) Transistor TPl and N-channel M
O8) An inverter circuit constituted by a Tunsistor TN□ constitutes an input circuit, and a diode D3 is connected between this gate input and the %VDD terminal. The gate input of the inverter circuit is an N-channel MO as an output circuit.
8) Further coupled to the open drain output of the transistor via a high resistance capacitor. A diode D4 is connected between the extraction electrode 1, which can serve as an input terminal, and the low potential level (GND level) of the power source.

今、ＮチャネルＭＯ８トｊンジスタ’Ｉ’Ｎｚが動作し
た場合、ａ点の電位は、ＶＤＤ電位よりも大きくなり得
る。したがりて、外付の負荷回路からの電流経路は抵抗
几、→ダイオードＤ、→ダイオードの内部抵抗几、→Ｖ
ＤＤ端子となり、この経路を介して電流が流れることに
なる。ところが、抵抗比、は高抵抗であるため、電流制
限をしてＮチャネルＭＯ８１１ンジスタＴＮ２の機能を
正常動作状態に保持する。また、保吸機能に対しては第
２図のものと実質的に変わらないことは熱論である。Now, when the N-channel MO8 transistor 'I'Nz operates, the potential at point a can become higher than the VDD potential. Therefore, the current path from the external load circuit is resistance → diode D → internal resistance of diode → V
This becomes the DD terminal, and current will flow through this path. However, since the resistance ratio is a high resistance, the current is limited to maintain the function of the N-channel MO811 transistor TN2 in a normal operating state. Furthermore, it is a matter of opinion that the suction function is essentially the same as that shown in Fig. 2.

（発明の効果） 本発明の様な保護回路を利用することにより、入力・出
力混合回路の静電気に対する保護が可能となる。(Effects of the Invention) By using a protection circuit such as that of the present invention, it is possible to protect an input/output mixing circuit from static electricity.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す等価回路図、第２図は
従来例を示す等価回路図である。 １・・・・・・引出し電極、几、、Ｒ，、Ｒ＋、・・・
・・・抵抗、Ｄｌ、Ｄ、、Ｄ、、Ｄ、・・・・・・ダイ
オード％ＴＰｌ　　・・・・・・ＰチャネルＭＯ８）う
／ジスタ、ＴＮ　１　＋　ＴＮ　２　・・・・・・Ｎチ
ャネルＭＯ８）ランジスタ。 又じ ＶＤＤ 朧　２　習FIG. 1 is an equivalent circuit diagram showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram showing a conventional example. 1... Extraction electrode, R,, R+,...
...Resistance, Dl, D,,D,,D, ...Diode %TPl ...P channel MO8) U/Resistor, TN 1 + TN 2 ......N Channel MO8) transistor. Mataji VDD Oboro 2 Xi

Claims (1)

【特許請求の範囲】[Claims] 　同一の外部引出し電極に入力および出力回路が接続さ
れて前記電極が入出力端子となり得る集積回路において
、前記入力回路の入力端と前記出力回路の出力端とが抵
抗を介して結合され、前記入力回路の入力端と電源の一
方との間に第１のダイオードが付加され、前記出力回路
の出力端と電源の他方との間に第２のダイオードが付加
され、前記出力回路の出力端が前記引出し電極に結合さ
れていることを特徴とする集積回路。In an integrated circuit in which input and output circuits are connected to the same external extraction electrode and the electrode can serve as an input/output terminal, the input end of the input circuit and the output end of the output circuit are coupled via a resistor, and the input A first diode is added between the input end of the circuit and one of the power sources, a second diode is added between the output end of the output circuit and the other power source, and the output end of the output circuit is connected to the power source. An integrated circuit characterized in that the integrated circuit is coupled to an extraction electrode.
JP59241004A 1984-11-15 1984-11-15 Integrated circuit Pending JPS61119073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59241004A JPS61119073A (en) 1984-11-15 1984-11-15 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59241004A JPS61119073A (en) 1984-11-15 1984-11-15 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS61119073A true JPS61119073A (en) 1986-06-06

Family

ID=17067896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59241004A Pending JPS61119073A (en) 1984-11-15 1984-11-15 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS61119073A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6269660A (en) * 1985-09-24 1987-03-30 Toshiba Corp Electrostatic protective circuit
EP0675543A2 (en) * 1994-03-31 1995-10-04 Seiko Instruments Inc. Semiconductor device including protection means and manufacturing method thereof
US7233466B2 (en) 2002-08-02 2007-06-19 Nec Electronics Corporation Input protection circuit
JP2008008604A (en) * 2006-06-02 2008-01-17 Daikin Ind Ltd Refrigerant piping structure and air conditioner

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6269660A (en) * 1985-09-24 1987-03-30 Toshiba Corp Electrostatic protective circuit
JPH0347743B2 (en) * 1985-09-24 1991-07-22 Tokyo Shibaura Electric Co
EP0675543A2 (en) * 1994-03-31 1995-10-04 Seiko Instruments Inc. Semiconductor device including protection means and manufacturing method thereof
EP0675543A3 (en) * 1994-03-31 1996-10-16 Seiko Instr Inc Semiconductor device including protection means and manufacturing method thereof.
US7233466B2 (en) 2002-08-02 2007-06-19 Nec Electronics Corporation Input protection circuit
JP2008008604A (en) * 2006-06-02 2008-01-17 Daikin Ind Ltd Refrigerant piping structure and air conditioner

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