JPS61117832A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61117832A JPS61117832A JP59238565A JP23856584A JPS61117832A JP S61117832 A JPS61117832 A JP S61117832A JP 59238565 A JP59238565 A JP 59238565A JP 23856584 A JP23856584 A JP 23856584A JP S61117832 A JPS61117832 A JP S61117832A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- etched
- film
- photolithography
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000000206 photolithography Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分母）
この発明は、半導体装置製造のホトリソグラフィ工程数
のα１４減とＬＳｌｌｉｌ造における歩留りの向上を期
するようにした半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Denominator) The present invention relates to a method for manufacturing a semiconductor device that is intended to reduce the number of photolithography steps in semiconductor device manufacturing by α14 and to improve the yield in LSllil manufacturing.
（従来の技術）
従来、ＬＳＩＩＩ造の分野で、ホトリソゲラブイおよび
エツチング技術を駆吏し、微細な回路パターンを作成す
る。つまり半導体基板（Ｓｉ基板など）上に黴細な回路
パターンを工程順に遂時作成し、重ね合わせていく。そ
の際、通常１回のホトリソグラフィ工程に１枚のガラス
マスクを使用し、工程を進めていく。(Prior Art) Conventionally, in the field of LSIII manufacturing, fine circuit patterns are created using photolithography and etching techniques. In other words, a fine circuit pattern is created on a semiconductor substrate (such as a Si substrate) in the order of steps and then superimposed. At that time, one glass mask is usually used for one photolithography process to proceed with the process.
（発明が解決しようとする問題点）
現在ＬＳＩのｍｓ度が急激に向上し、回路パターンの微
細化が要求されているが、それに伴ない、ホトリソグラ
フィ工程数も増加する傾向にある。(Problems to be Solved by the Invention) Currently, the ms of LSI is rapidly increasing, and there is a demand for finer circuit patterns, but the number of photolithography steps also tends to increase accordingly.
しかし、ホトリソグラフィ工程数の増加は、塵埃などに
よる回路欠陥の原因となる。However, an increase in the number of photolithography steps causes circuit defects due to dust and the like.
さらＣζ、各マスクパターンの相互の璽ね合わせ（アラ
イメーント）の回数が増加し、各重ね合わせずれ（アラ
イメントエラー）により、ＬＳＩ良品の出現率（歩留り
）の低下をもたらしていた。Furthermore, Cζ, the number of mutual alignments of each mask pattern increases, and each misalignment (alignment error) causes a decrease in the appearance rate (yield) of non-defective LSI products.
この発明は、前記従来技術がもっている欠点のうちホト
リソ工程数の多い点および歩留りの低下を来たす点につ
いて解決した半導体装置の製造方法を提供するものであ
る。The present invention provides a method for manufacturing a semiconductor device that solves the disadvantages of the prior art in that it requires a large number of photolithography steps and that it causes a decrease in yield.
（問題点を解決するための手１９）
この発明は半導体装置の製造方法において、ホトリソグ
ラフィ工程で回路パターンを作成する際通常の回路パタ
ーンとは別に光学的に解像不可能な微細パターンで構成
された回路パターンとを有するマスクを用いて露光およ
び現像処理工程を導入するようにしたものである。(Measures for Solving Problems 19) This invention is a semiconductor device manufacturing method, in which a circuit pattern is created in a photolithography process by using a fine pattern that is not optically resolvable, in addition to a normal circuit pattern. In this method, exposure and development processing steps are introduced using a mask having a printed circuit pattern.
（作 用）
この発明によれば、以上のように半導体装置の製造方法
に露光および現像処理工程を導入したので、１回のホト
リソグラフィ工程を経て、通常の回路パターンと、解像
不可能な微細回路パターンとを段階的に露光および現像
処理し、現像後通常の回路パターニングされる部分と解
像不可能な微細回路パターニングされろ部分を同時に作
成する。(Function) According to the present invention, since the exposure and development processing steps are introduced into the semiconductor device manufacturing method as described above, a normal circuit pattern and an unresolvable pattern can be formed through one photolithography step. The fine circuit pattern is exposed and developed in stages, and after development, a portion to be subjected to normal circuit patterning and a portion to be subjected to unresolvable fine circuit patterning are simultaneously created.
（実施例）
以下、この発明の半導体装置の製造方法の一実施例につ
いて図面に基づき説明する。第１図（ａｌ〜第１図（ｄ
ｉはその一実施例の工程説明図である。まず、この工程
の説明に入る前に、この発明の理解を容易にするために
、この発明に適用され縮小投影露光装置に使用する縮小
投影露光用のマスク（レチクル）について説明する。(Example) An example of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. Figure 1 (al~Figure 1 (d)
i is a process explanatory diagram of one embodiment. First, before entering into a description of this step, in order to facilitate understanding of the present invention, a mask (reticle) for reduction projection exposure applied to the present invention and used in a reduction projection exposure apparatus will be described.
第３図（ａｌはこの縮小投影露光用のマスク（レチクル
と言う）１を示している。２は解像可能な従来のパター
ンであり、３は光学的に解像不可能な非常に微細なパタ
ーン（０，３または０４μｒ１１程度のラインアンドス
ペースパターンなど）で構成された微細パターンを示し
ている。Figure 3 (al) shows a mask (called a reticle) 1 for this reduction projection exposure. 2 is a resolvable conventional pattern, and 3 is a very fine pattern that cannot be optically resolved. It shows a fine pattern composed of a pattern (such as a line and space pattern of about 0, 3 or 04 μr11).
また、第３図（ｂｌば１０倍もしくは５倍の縮小レンズ
４であり、第３図ｔｃ＋はレチクル１がウェハ５上転写
されたレジストパターン１ａを示している。Further, FIG. 3 (bl is a 10x or 5x reduction lens 4, and FIG. 3 tc+ shows a resist pattern 1a on which the reticle 1 is transferred onto the wafer 5.
このレジストパターン１ａはし゛チクル１のレジストパ
ターンであり、さらに、２＆は解像可能な従来のパター
ン２のレジストパターンであり、３１は光学的に解像不
可能な非常に微細なパターン３のレジストパターンであ
る。This resist pattern 1a is a resist pattern of a particle 1, 2& is a resist pattern of a conventional pattern 2 which can be resolved, and 31 is a resist pattern of a very fine pattern 3 which cannot be optically resolved. It is.
次に、第１図により、この発明の詳細な説明に移行する
。第１図＋０１は第２図（Ｃ１におけるＡ−Ａ綿の部分
の断面図である。この第１図＋０１において、２１は下
地層であｌ）、２２，２３は被エツチング膜、２４はホ
トリソグラフィで現像処理後のレジストであり、２５は
第３図［０１に示す解像可能なレノストパターン２ａの
部分であり、被エツチング膜２３上のレジスト膜２４は
除去され、被エツチング膜２３は露出している。Next, referring to FIG. 1, a detailed explanation of the present invention will be given. Figure 1 +01 is a cross-sectional view of the A-A cotton part in Figure 2 (C1. In this Figure 1 +01, 21 is the base layer), 22 and 23 are the films to be etched, and 24 is the photosensitive layer. 25 is a portion of the resolvable Renost pattern 2a shown in FIG. exposed.
また、２６は第３図（ｃｌに示す解像不可能なパターン
３ａの部分であり、被エツチング膜２３上のレジストＷ
４２４は微小ではあるが残され、被エツチング膜２３は
覆われている。26 is a portion of the unresolvable pattern 3a shown in FIG.
Although the portion 424 is minute, it remains, and the film to be etched 23 is covered.
このパターン２６に示す部分の残されたレジスト膜２４
の厚さＢは、主に解像不可能な微細パターンの寸法で変
化させることが可能である。Resist film 24 remaining in the portion shown in this pattern 26
The thickness B can be changed mainly depending on the dimensions of the fine pattern that cannot be resolved.
次に、第１図＋０１に示すようにレジスト膜２４をマス
クにして被エツチング膜２３のエツチングを施こす。こ
の被エツチング膜２３上のレジストパターン２４は解像
不可能な微細パターン２６で構成された部分では、やは
り微小な厚さＢａが残される。Next, as shown in FIG. 1+01, the film to be etched 23 is etched using the resist film 24 as a mask. The resist pattern 24 on the film to be etched 23 still leaves a very small thickness Ba in the portion where the resist pattern 24 is composed of the fine pattern 26 which cannot be resolved.
次に、第１図＋０１に示すように、さらにレジスト膜２
４０表面を全面的に酸素プラズマなどで、微小量除去し
、第１図（ｂｌにおいて、わずかに残されたパターン２
６の部分のレジスト膜２４を除去し、その部分の被エツ
チング膜２３を露出させろ。Next, as shown in FIG.
A very small amount of the 40 surface was removed using oxygen plasma, etc., and the pattern 2 that remained slightly in Figure 1 (bl) was removed.
Remove the resist film 24 at the portion 6 and expose the film 23 to be etched at that portion.
さらに、第１図ｆｄｌに示すようζＣ１被エツチング膜
２２．２３に対して同時にエツチングを施こす。Furthermore, as shown in FIG. 1fdl, the ζC1 etched films 22 and 23 are simultaneously etched.
通常、この被エツチング４％２２．２３がゲート材料や
配線材料に用いられろ３０００人〜５０００人程度形成
リシリコン膜である場合、下地Ｎｉ２１と被エツチング
膜２２としてのポリシリコンの間、または被エツチング
膜２２と２３としての二つの層のポリシリコンとの間に
２００〜１０００人程度のＳｉＯ形成などの絶縁層が加
わるが、その場合でも、第１図＋０１、第１図（Ｃ１に
示す工程間に、または第１図ｆｄｌに示す工程後に絶縁
層の除去工程を加えることで適応可能である。Normally, this 4% to be etched film 22.23 is used as a gate material or wiring material.When a silicon film is formed by about 3,000 to 5,000 people, there is a gap between the base Ni 21 and the polysilicon as the film to be etched 22, or between the base Ni 21 and polysilicon as the film to be etched. An insulating layer of approximately 200 to 1,000 SiO layers is added between the two layers of polysilicon as the films 22 and 23, but even in that case, the process steps shown in Figure 1+01 and Figure 1 (C1) are added. This can be applied by adding an insulating layer removal step after the step shown in FIG. 1 or after the step shown in FIG.
以上説明したように、上記実施例では、ホトリソグラフ
ィ工程の現像後の状態で、第１図（ａｌに示１ようにレ
ノストｐｌＡ２４のパターンに、通常に、パターニング
されたレチクル１０のパターン２の部分のパターン２５
と微小にレジスト膜を残してバターニングされるパター
ン２６の部分を同時に作成するものであり、それにより
、従来２回のホトリソグラフィ工程を１回で済ますこと
が可能になる。As explained above, in the above embodiment, the pattern 2 portion of the reticle 10 that is normally patterned in the pattern of the Renost PLA 24 as shown in FIG. pattern 25
The pattern 26 portion to be patterned is simultaneously created while leaving a minute resist film, thereby making it possible to complete the photolithography process in one step instead of the conventional two.
この発明はＬＳＩ製造の際、ホトリソグラブイ工程数を
少なくすると同時に、非常に大きな段差を有する部分に
コンタクトホールなどのパターンを同時に作成する場合
にも効果的に応用することができる。第２図にその実施
例を示し、工程順に説明する。The present invention can be effectively applied to reduce the number of photolithography steps during LSI manufacturing and simultaneously create patterns such as contact holes in areas with very large steps. An example thereof is shown in FIG. 2, and the steps will be explained in order.
まず、第２図ｔａ＋はこの発明によるホトリソグラフィ
工程の現像後の状態を示すものであり、図中の３１は下
地層、３２は段差部分を構成する下地層、３３は被エツ
チング膜、３４はレジスト膜であり、３５は第３図ｔｅ
ｌに示す解像可能なレジストパターン２ａの部分であり
、コンタクトホールパターンであり、被エツチング膜３
３上のレジストパターン３４は除去されている。First, FIG. 2 ta+ shows the state after development in the photolithography process according to the present invention. In the figure, 31 is a base layer, 32 is a base layer constituting a stepped portion, 33 is a film to be etched, and 34 is a base layer. 35 is a resist film, and 35 is a resist film.
This is the part of the resist pattern 2a that can be resolved as shown in FIG.
The resist pattern 34 above 3 has been removed.
また、３６は第３図［０１に示す解像不可能なパターン
で構成されたパターン３ａの部分であり、被エツチング
３３上のレジスト膜３４は微小な厚さＣだけ残されてい
る。Further, 36 is a portion of the pattern 3a consisting of an unresolvable pattern shown in FIG.
この第２図［ａｌに示すように、段差の下に作成すべき
フンタクトホールパターン３５は、通常の解像可能なパ
ターンで作成し、段差の上には、この発明による解像不
可能なパターンで構成されたパターンを配置する。この
実施例で示す工程も、第１図で示した実施例と同様に説
明すると、ある程度被エツチング膜３３のエツチングを
胞こすと、第２図（ｂｌに示す状態となる。As shown in this FIG. Arrange a pattern made up of patterns. The process shown in this embodiment will be explained in the same manner as the embodiment shown in FIG. 1. After the etching of the film 33 to be etched is removed to some extent, the state shown in FIG. 2 (bl) is obtained.
次に、第２図（ｂｌに示すように、酸素プラズマなどで
、レジスト膜３４の表面を除去し、解像不可能なパター
ン３ａで構成された解像不可能なパターンの部分３６の
被エツチング３３上のレジスト膜３４をわずかに残るよ
うに除去させる。Next, as shown in FIG. 2 (bl), the surface of the resist film 34 is removed using oxygen plasma or the like, and the unresolvable pattern portion 36 composed of the unresolvable pattern 3a is etched. The resist film 34 on the resist film 33 is removed so that a small amount remains.
さらに、第２図［ｃｌに示すように、解像不可能なパタ
ーンの部分３６における被エツチング膜３３上のレジス
トＭ３４を除去して、この被エツチングｖ！Ａ３３を露
出させる。Furthermore, as shown in FIG. 2 [cl], the resist M34 on the etched film 33 in the unresolvable pattern portion 36 is removed, and this etched v! Expose A33.
次に、第２図ｔｄｌに示すように、解像不可能なパター
ンの部分３６に対応する被エツチング膜３３のエツチン
グを終了させる。Next, as shown in FIG. 2 tdl, the etching of the film to be etched 33 corresponding to the unresolvable pattern portion 36 is completed.
通常、大きな段差を有する下地上でのホトリソ、エツチ
ング工程では段差の上部と下部では被エツチングｙ４３
３の膜厚が異なり、ホトリソグラフィの現像後のレジス
ト３４パターンの寸法およびエツチング時間などの条件
設定が非常に困難になるが、第２図に示すこの発明の実
施例による製造工程を応用することにより、従来と比較
し、容易にホトリソグラフィおよびエツチングを行うこ
とが可能になる。Usually, in the photolithography and etching process on a substrate with a large step, the upper and lower parts of the step are etched y43.
The film thicknesses of the resists 3 and 3 are different, making it very difficult to set conditions such as the dimensions of the resist 34 pattern after photolithographic development and the etching time. However, it is possible to apply the manufacturing process according to the embodiment of the present invention shown in FIG. This makes it possible to perform photolithography and etching more easily than in the past.
（発明の効果）
以上詳細に説明したように、この発明によれば、ホトリ
ソグラフィ工程で解像可能なパターンで構成された回路
パターンと光学的に解像不可能な微細なパターンで構成
された回路のパターンとを有するマスクを用いて露光お
よび現像処理を行うようにしたので、ホトリソグラフィ
の工程数を削減でき、マスク合わせ回数の減少にともな
うＬＳＩの製造歩留りの向上が期待されるなどの効果を
要する。(Effects of the Invention) As explained in detail above, according to the present invention, a circuit pattern is formed of a pattern that can be resolved by a photolithography process and a fine pattern that cannot be resolved optically. Since the exposure and development processes are performed using a mask with a circuit pattern, the number of photolithography steps can be reduced, and LSI manufacturing yields are expected to improve due to the reduction in the number of mask alignments. It takes.
第１図Ｔａｌないし第１図ｔｄｌはこの発明の半導体装
置の製造方法の一実施例の工程説明図、第２図ｆｉｌな
いし第２図（ｄｉはそれぞれこの発明の半導体装置の製
造方法の他の実施例の工程説明図、第３図ｔ１１はこの
発明の半導体装置の製造方法に適用される縮小投影露光
装置に使用されるレチクルのｌ！ｉＩ視図、第３図（ｂ
ｌは同上縮小投影露光装置に使用されろ縮小レンズの斜
視図、第３図ｔＣ１は第３図［ａｌのレチクルを転写し
たレジストパターンを有するウェハを示す図である。
２１．３１．３２・・・下地層、２２，２３．３３・・
・被エツチング層、２４．３４・レジスト膜、２５ ・
解像可能な回路のパターンの部分、２６゜３５・コンタ
クトホールパターン、３６ 光学的に解像不可能な微細
な回路のパターンの部分。
第１ｖ！Ｊ
第２ｆｌｌ１
３４ニジレスト月鈍
３５二フシ？７トが１−ルｌｆ’？−’。1 Tal to 1 tdl are process explanatory diagrams of one embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 fil to FIG. FIG. 3 (t11) is a process explanatory diagram of the embodiment, and FIG.
1 is a perspective view of a reduction lens used in the reduction projection exposure apparatus as described above, and FIG. 3 tC1 is a diagram showing a wafer having a resist pattern onto which the reticle of FIG. 21.31.32...base layer, 22,23.33...
・Etched layer, 24. 34 ・Resist film, 25 ・
Part of a circuit pattern that can be resolved, 26°35・Contact hole pattern, 36 Part of a fine circuit pattern that cannot be optically resolved. 1st v! J 2nd flll1 34 Niji Rest Moon Blunt 35 Nifushi? 7g is 1-le lf'? -'.
Claims (1)
程において、解像可能な回路パターンと光学的に解像不
可能な微細なパターンで構成された回路パターンを有す
るガラスマスクを用いて露光、現像処理を施こし、上記
解像可能な回路のパターンは被エッチング膜を露出させ
上記解像不可能な回路のパターンは被エッチング膜上に
他の未露光部分と比べごく薄いレジスト膜を残し、その
後のエッチング処理を選択的に行なうことを特徴とする
半導体装置の製造方法。In the photolithography process in the manufacturing process of semiconductor devices, exposure and development are performed using a glass mask having a circuit pattern consisting of a resolvable circuit pattern and a fine pattern that cannot be optically resolved. The above resolvable circuit pattern exposes the film to be etched, and the above non-resolvable circuit pattern leaves a very thin resist film on the etched film compared to other unexposed areas, and the subsequent etching process is selected. 1. A method of manufacturing a semiconductor device, characterized in that the manufacturing method is carried out according to a method of manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238565A JPS61117832A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238565A JPS61117832A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61117832A true JPS61117832A (en) | 1986-06-05 |
| JPH0235448B2 JPH0235448B2 (en) | 1990-08-10 |
Family
ID=17032112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59238565A Granted JPS61117832A (en) | 1984-11-14 | 1984-11-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61117832A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725872B2 (en) | 2002-07-26 | 2010-05-25 | Asml Masktools, B.V. | Orientation dependent shielding for use with dipole illumination techniques |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5312793A (en) * | 1976-07-23 | 1978-02-04 | Midori Anzen Kogyo | Oxygen generating apparatus |
| JPS5558534A (en) * | 1978-10-24 | 1980-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5626450A (en) * | 1979-08-13 | 1981-03-14 | Hitachi Ltd | Manufacture of semiconductor device |
-
1984
- 1984-11-14 JP JP59238565A patent/JPS61117832A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5312793A (en) * | 1976-07-23 | 1978-02-04 | Midori Anzen Kogyo | Oxygen generating apparatus |
| JPS5558534A (en) * | 1978-10-24 | 1980-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5626450A (en) * | 1979-08-13 | 1981-03-14 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725872B2 (en) | 2002-07-26 | 2010-05-25 | Asml Masktools, B.V. | Orientation dependent shielding for use with dipole illumination techniques |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235448B2 (en) | 1990-08-10 |
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