JPS61111232U - - Google Patents

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Publication number
JPS61111232U
JPS61111232U JP19590784U JP19590784U JPS61111232U JP S61111232 U JPS61111232 U JP S61111232U JP 19590784 U JP19590784 U JP 19590784U JP 19590784 U JP19590784 U JP 19590784U JP S61111232 U JPS61111232 U JP S61111232U
Authority
JP
Japan
Prior art keywords
integrated circuit
mos
mos integrated
emitter
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19590784U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19590784U priority Critical patent/JPS61111232U/ja
Publication of JPS61111232U publication Critical patent/JPS61111232U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るインターフエイス回路の
回路図、第2図は従来のインターフエイス回路の
回路図である。 1,2……MOS、IC,3,13……MOS
FET、4,14……コントロール端子、9,1
6……データ読込み端子、5,12……I/O端
子、11……抵抗、10……トランジスタ。
FIG. 1 is a circuit diagram of an interface circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional interface circuit. 1, 2...MOS, IC, 3, 13...MOS
FET, 4, 14...Control terminal, 9, 1
6...Data reading terminal, 5, 12...I/O terminal, 11...Resistor, 10...Transistor.

Claims (1)

【実用新案登録請求の範囲】 オン時の抵抗の小さいMOS FETで構成さ
れた第1のMOS集積回路と、 オン時の抵抗の大きいMOS FETで構成さ
れた第2のMOS集積回路と、 前記第1のMOS集積回路の入/出力端子とア
ース点間にエミツタ・コレクタ路が接続され、前
記第2のMOS集積回路の入/出力端子にベース
が接続され、エミツタとベース間に抵抗が介挿接
続されるトランジスタとを具備したことを特徴と
するインターフエイス回路。
[Claims for Utility Model Registration] A first MOS integrated circuit configured with a MOS FET with low resistance when turned on; a second MOS integrated circuit configured with a MOS FET with high resistance when turned on; An emitter-collector path is connected between the input/output terminal of the first MOS integrated circuit and the ground point, a base is connected to the input/output terminal of the second MOS integrated circuit, and a resistor is inserted between the emitter and the base. An interface circuit characterized by comprising a transistor to be connected.
JP19590784U 1984-12-26 1984-12-26 Pending JPS61111232U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19590784U JPS61111232U (en) 1984-12-26 1984-12-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19590784U JPS61111232U (en) 1984-12-26 1984-12-26

Publications (1)

Publication Number Publication Date
JPS61111232U true JPS61111232U (en) 1986-07-14

Family

ID=30753526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19590784U Pending JPS61111232U (en) 1984-12-26 1984-12-26

Country Status (1)

Country Link
JP (1) JPS61111232U (en)

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