JPS61111015A - Pll frequency synthesizer type tv receiver - Google Patents

Abstract

PURPOSE:To confirm simply the AFT operation by providing a means changing forcibly the frequency dividing ratio of a programmable counter for confirming the operation of an AFT circuit. CONSTITUTION:When the test mode is transmitted to an N-value offset data generator 13, the generator 13 gives a signal to a channel data setting device 4 so that the frequency division ratio of a programmable counter 6 is 1/N frequency division offset to the standard channel data. Thus, the output frequency of a VCO7 is an offset frequency to the frequency of the standard channel. When a TV signal of the standard frequency is received in this state, an IF signal deviated by the offset frequency's share is obtained. Thus, the AFT circuit 1 is operated, the frequency division ratio of the counter 6 is changed, the output frequency of the VCO7 is moved and the PLL loop is operated so that the IF frequency is a correct frequency.

Description

【発明の詳細な説明】 （技術分野） 本発明は、電子チューナ局部発振器にＰＬＬシンセサイ
ザを用いたＰＬＬシンセサイザ方式ＴＶ受像機に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a PLL synthesizer type TV receiver that uses a PLL synthesizer as an electronic tuner local oscillator.

（従来技術） 第２図に示す従来のＰＬＬシンセサイザ方式テレビ受像
機のチューナ部のＰＬＬ回路において、１はＡＦＴ回路
、２はＡ／Ｄ変換器、３は判定回路、４はチャンネルデ
ータ設定回路、５は演算処理装Ｍ（ＣＰＵ＞、６は可変
分周器（プログラマプルカランタン、７は電圧制御発振
器（ＶＣＯ）、８はローパス・フィルタ、９は位相比較
器、１０は基準周波数発振器である。(Prior Art) In the PLL circuit of the tuner section of the conventional PLL synthesizer television receiver shown in FIG. 2, 1 is an AFT circuit, 2 is an A/D converter, 3 is a determination circuit, 4 is a channel data setting circuit, 5 is an arithmetic processing unit M (CPU>), 6 is a variable frequency divider (programmable carentan), 7 is a voltage controlled oscillator (VCO), 8 is a low-pass filter, 9 is a phase comparator, and 10 is a reference frequency oscillator.

かかる構成において、電圧制御発振器（ｖｃｏニアの出
力はプログラマブルカウンタ６で分周され。In this configuration, the output of the voltage controlled oscillator (vconia) is frequency-divided by a programmable counter 6.

その出力と基準周波数１０とが位相比較器９により位相
比較される。以上の様にＰＬＬループが構成されるが、
チャンネルデータ設定器４は受信チャンネルに応じたデ
ータがプログラマブルカウンタ６に出力され、受信チャ
ンネル周波数に対応した電圧制御発振器７の出力、つま
り電子チューナの局部発振周波数が得られる。さらに受
信チャンネル周波数に対してその上下にオフセットされ
ている信号を受信する為に、ＡＦＴ回路１が設けられ、
その出力はＡ／Ｄ変換変換４料２ て、プログラマブルカウンタ６の分周比を変化させ、Ａ
ＦＴに応じた局部発振周波数が得られ、周波数がオフセ
ットされた信号を受信可能にしている。The output and the reference frequency 10 are phase-compared by a phase comparator 9. The PLL loop is configured as above, but
The channel data setter 4 outputs data corresponding to the reception channel to the programmable counter 6, and obtains the output of the voltage controlled oscillator 7 corresponding to the reception channel frequency, that is, the local oscillation frequency of the electronic tuner. Furthermore, an AFT circuit 1 is provided to receive signals that are offset above and below the reception channel frequency,
The output is converted into an A/D conversion signal by changing the frequency division ratio of the programmable counter 6.
A local oscillation frequency corresponding to the FT is obtained, making it possible to receive signals whose frequencies are offset.

Claims (1)

【特許請求の範囲】[Claims] 電子チューナの局部発振器をＰＬＬ周波数シンセサイザ
で構成したＰＬＬシンセサイザ方式ＴＶ受像機に於いて
、ＡＦＴ回路の動作確認の為、プログラマブル・カウン
タの分周比を強制的に変化させる手段とを備えたことを
特徴とするＰＬＬシンセサイザ方式ＴＶ受像機。In a PLL synthesizer type TV receiver in which the local oscillator of an electronic tuner is configured with a PLL frequency synthesizer, it is provided with means for forcibly changing the frequency division ratio of a programmable counter in order to check the operation of the AFT circuit. Features a PLL synthesizer type TV receiver.