JPS61111015A - Pll frequency synthesizer type tv receiver - Google Patents
Pll frequency synthesizer type tv receiverInfo
- Publication number
- JPS61111015A JPS61111015A JP23213384A JP23213384A JPS61111015A JP S61111015 A JPS61111015 A JP S61111015A JP 23213384 A JP23213384 A JP 23213384A JP 23213384 A JP23213384 A JP 23213384A JP S61111015 A JPS61111015 A JP S61111015A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- offset
- receiver
- signal
- aft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は、電子チューナ局部発振器にPLLシンセサイ
ザを用いたPLLシンセサイザ方式TV受像機に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a PLL synthesizer type TV receiver that uses a PLL synthesizer as an electronic tuner local oscillator.
(従来技術)
第2図に示す従来のPLLシンセサイザ方式テレビ受像
機のチューナ部のPLL回路において、1はAFT回路
、2はA/D変換器、3は判定回路、4はチャンネルデ
ータ設定回路、5は演算処理装M(CPU>、6は可変
分周器(プログラマプルカランタン、7は電圧制御発振
器(VCO)、8はローパス・フィルタ、9は位相比較
器、10は基準周波数発振器である。(Prior Art) In the PLL circuit of the tuner section of the conventional PLL synthesizer television receiver shown in FIG. 2, 1 is an AFT circuit, 2 is an A/D converter, 3 is a determination circuit, 4 is a channel data setting circuit, 5 is an arithmetic processing unit M (CPU>), 6 is a variable frequency divider (programmable carentan), 7 is a voltage controlled oscillator (VCO), 8 is a low-pass filter, 9 is a phase comparator, and 10 is a reference frequency oscillator.
かかる構成において、電圧制御発振器(vcoニアの出
力はプログラマブルカウンタ6で分周され。In this configuration, the output of the voltage controlled oscillator (vconia) is frequency-divided by a programmable counter 6.
その出力と基準周波数10とが位相比較器9により位相
比較される。以上の様にPLLループが構成されるが、
チャンネルデータ設定器4は受信チャンネルに応じたデ
ータがプログラマブルカウンタ6に出力され、受信チャ
ンネル周波数に対応した電圧制御発振器7の出力、つま
り電子チューナの局部発振周波数が得られる。さらに受
信チャンネル周波数に対してその上下にオフセットされ
ている信号を受信する為に、AFT回路1が設けられ、
その出力はA/D変換変換4料2
て、プログラマブルカウンタ6の分周比を変化させ、A
FTに応じた局部発振周波数が得られ、周波数がオフセ
ットされた信号を受信可能にしている。The output and the reference frequency 10 are phase-compared by a phase comparator 9. The PLL loop is configured as above, but
The channel data setter 4 outputs data corresponding to the reception channel to the programmable counter 6, and obtains the output of the voltage controlled oscillator 7 corresponding to the reception channel frequency, that is, the local oscillation frequency of the electronic tuner. Furthermore, an AFT circuit 1 is provided to receive signals that are offset above and below the reception channel frequency,
The output is converted into an A/D conversion signal by changing the frequency division ratio of the programmable counter 6.
A local oscillation frequency corresponding to the FT is obtained, making it possible to receive signals whose frequencies are offset.
Claims (1)
で構成したPLLシンセサイザ方式TV受像機に於いて
、AFT回路の動作確認の為、プログラマブル・カウン
タの分周比を強制的に変化させる手段とを備えたことを
特徴とするPLLシンセサイザ方式TV受像機。In a PLL synthesizer type TV receiver in which the local oscillator of an electronic tuner is configured with a PLL frequency synthesizer, it is provided with means for forcibly changing the frequency division ratio of a programmable counter in order to check the operation of the AFT circuit. Features a PLL synthesizer type TV receiver.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23213384A JPS61111015A (en) | 1984-11-02 | 1984-11-02 | Pll frequency synthesizer type tv receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23213384A JPS61111015A (en) | 1984-11-02 | 1984-11-02 | Pll frequency synthesizer type tv receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61111015A true JPS61111015A (en) | 1986-05-29 |
Family
ID=16934511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23213384A Pending JPS61111015A (en) | 1984-11-02 | 1984-11-02 | Pll frequency synthesizer type tv receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61111015A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54133379A (en) * | 1978-04-07 | 1979-10-17 | Citizen Watch Co Ltd | Electronic watch |
-
1984
- 1984-11-02 JP JP23213384A patent/JPS61111015A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54133379A (en) * | 1978-04-07 | 1979-10-17 | Citizen Watch Co Ltd | Electronic watch |
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