JPS6077512A - Aft circuit of pll synthesizer system television receiver - Google Patents
Aft circuit of pll synthesizer system television receiverInfo
- Publication number
- JPS6077512A JPS6077512A JP58186246A JP18624683A JPS6077512A JP S6077512 A JPS6077512 A JP S6077512A JP 58186246 A JP58186246 A JP 58186246A JP 18624683 A JP18624683 A JP 18624683A JP S6077512 A JPS6077512 A JP S6077512A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- counter
- aft
- range
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/02—Automatic frequency control
- H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
- H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
- H03J7/065—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers the counter or frequency divider being used in a phase locked loop
Landscapes
- Television Receiver Circuits (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は1〕シしシンセサイflJ式テレビ受像機のΔ
「゛1−回路に関するちのであり、八F「電1Fが77
’れ(も、放送43号を確実に受信できるようにし/S
ものぐある。DETAILED DESCRIPTION OF THE INVENTION The present invention provides (1) Δ
``゛1-It is related to the circuit, and the 1st floor of the 8th floor is 77
'Re(Also, make sure to receive Broadcast No. 43/S
There are things.
第゛1図は本発明の実施例を示し、Δ1:]゛回路の制
御信号によりプログラマブルカウンタが標準放送チャン
ネル周波数に対して所定の範囲の」−下にΔFT動作が
可能なPLLシンヒリ゛イザのA F T部及びPLL
郡である。FIG. 1 shows an embodiment of the present invention, in which the control signal of the circuit causes the programmable counter to operate within a predetermined range with respect to the standard broadcast channel frequency. AFT section and PLL
It is a county.
放送を受信する動作はCP LJ 5からチャンネルデ
ータ設定器4に特定の放送チャンネルのデータが入力し
、プログラマブルカウンタ6の1/Nilを設定する。In the operation of receiving a broadcast, data of a specific broadcast channel is input from the CP LJ 5 to the channel data setter 4, and 1/Nil is set in the programmable counter 6.
プログラマブルカウンタ6は電fチューブ内の局部発信
器である電圧制御l1発振器(VCO)8の発信周波数
をプリスケーラ7で1/Mされたものをさらに1/Nに
分周し、位相比較器10に送る。位相比較器10は前記
プログラマブルカウンタ6の出力信号と13 Ql−周
波数梵振器11の出力どを位相比較し、出力j’fft
;C雷J[は[I−パスフィルタ9を通って電11制
御I光振器8を制御づる。A programmable counter 6 divides the oscillation frequency of a voltage-controlled l1 oscillator (VCO) 8, which is a local oscillator in the electric f-tube, by 1/M by a prescaler 7, and then divides the frequency by 1/N, and sends the frequency to a phase comparator 10. send. A phase comparator 10 compares the phases of the output signal of the programmable counter 6 and the output of the Ql-frequency oscillator 11, and outputs j'fft.
;C lightning J[ passes through I-pass filter 9 to control electricity 11 and I-optical oscillator 8.
△に−I!IJJ作は映像中間周波数(+) I E
)のA[二T回路1からのSカーブ電圧をΔ/[)変換
回路2及び判定回路3によりブ1コグラマ1ルカウンタ
6を放送周波数の標準値に対して上下に動かりこと(゛
周波数を可変できる。△ni-I! IJJ works have video intermediate frequency (+) I E
) of the S curve voltage from the two-T circuit 1 by Δ/[) conversion circuit 2 and judgment circuit 3 to move the block diagram counter 6 up and down with respect to the standard value of the broadcasting frequency. Can be changed.
フレビ受像機のPIF部AF王回路1で得られるSカー
)電圧は第2図に示づように、映像キャリj′と音声キ
ャリアの2波のため、中間周波数の1−側の範囲が狭く
、下側の範囲が広い。その周波数は+側800 K l
−1z 、下側2 M HZぐらいである。As shown in Figure 2, the S voltage obtained in the AF circuit 1 of the PIF section of the Frevi receiver is two waves, the video carrier j' and the audio carrier, so the range on the 1- side of the intermediate frequency is narrow. , the lower range is wide. Its frequency is + side 800K l
-1z, the lower side is about 2 MHz.
本発明の要旨はA F ’l−動作を含むヂューナシス
jムのうlう、l]lLシンセ1ノ゛イザ方式での、A
F[電JFの11?ブヂI7−レンジ(第2図のA F
T’ 13心周波数に対して斜線の範囲)内に、プロ
グラマゾルカウンタの分周比の可変範囲の最大値を設定
りることである。本来PLLシンレ1少イザ方式は電子
チー1−ノの局部発信周波数のドリフ1〜がない1、:
め、Δ1:1−機能は必要ないが、V 1− Rやブレ
ビゲーム等の[<[:出力が、標準デーIンネル周波数
に24 L、 (す“れCいる場合には、テレビ受像機
のA Fl−により追従しCやる必要があるためf]加
Jる必要がある。そこで、かかる設定を行なうことによ
り、プログラマ1ルカウンタ6のAF l’動作範囲を
AFTキ17プヂヤーレンジ内にすることにより大幅に
改善できる。つまり、無信号(無放送) Ik’7や伯
の放送のスプリアス等によりAFT電圧がずれて受信周
波数がfれでしまっても、そのずれがAFTギャブヂ1
7−レンジ内にあるため、放送信号をつかまえることが
できるものである。The gist of the present invention is that the A F'l-operation is included in the syntax, and the A
F [Electric JF's 11? Buji I7-Range (A F in Fig. 2)
The maximum value of the variable range of the frequency division ratio of the programmer sol counter is set within the shaded range relative to T'13 heart frequency. Originally, the PLL synchronization system eliminates the drift of the local oscillation frequency of the electronic chip.
Therefore, the Δ1:1-function is not necessary, but if the output is 24L, Since it is necessary to follow up with A Fl- of A and perform C, it is necessary to add f]. Therefore, by making such settings, the AF l' operating range of programmer 1 counter 6 can be brought within the AFT key 17 pressure range. In other words, even if the AFT voltage deviates due to no signal (non-broadcasting) Ik'7 or spurious broadcasting, etc. and the receiving frequency becomes f, the deviation will be
Since it is within the 7-range, it can catch broadcast signals.
以上のように本発明によれば、放送局の送信が始まる前
にヂレンネルを設定しC放送の始まるのを待つ持受り受
信の時、スプリアス等が存在し、AFT電圧がずれ−C
しまって受信周波数がずれいても確実に放送信号をキュ
ッヂすることができる。As described above, according to the present invention, when a broadcast station sets the de-channel before the broadcast station starts transmitting and waits for the start of the C broadcast, spurious etc. exist and the AFT voltage deviates -C.
Even if the reception frequency is shifted due to storage, the broadcast signal can be reliably received.
第1図は本発明に係る実施例を示づ図、第2図は第1図
Δ]−1回路の電HE特性を示す図である。
1・・・・・・ΔF]−回路
2・・・・・・Δ/1)変換回路
3・・・・・・判定回路
1・・・・・・チャンネルデータ設定器5・・・・・・
CP U
6・・・・・・ブUグラマプルカウンタ7・・・・・・
プリスケーラ
8・・・・・・電1(制御発振器
[)・・・・・・ローパスフィルタ
10・・・・・・位相比較器
11・・・・・・基準周波数発振器
特許出願人
バイAニア株式会FIG. 1 is a diagram showing an embodiment according to the present invention, and FIG. 2 is a diagram showing the electric HE characteristics of the Δ]-1 circuit shown in FIG. 1...ΔF]-circuit 2...Δ/1) Conversion circuit 3...Judgment circuit 1...Channel data setter 5...・
CPU 6...Bugram pull counter 7...
Prescaler 8...Electric 1 (controlled oscillator [)...Low pass filter 10...Phase comparator 11...Reference frequency oscillator Patent applicant Buy A Near Stock Association
Claims (1)
、所定の放送ヂVンネルを受信するだめの局部発振周波
数を1iノると共に、前記放送チャンネルの標準周波数
に対してAI=T回路からの制御信号にJ:り受信周波
数を土トに可変可能なプログラマブルカウンタを有し、
AFT回路のキャプチV−レンジ内にaハノる中心周波
数より狭い側の範囲に前記ブ■グラマブルノJウンタの
可変範囲の最大値を設定しlこことを特徴とりるP L
Lシンレリイ’f 7’5式テレビ受像機のA P
I−回路。1) 1” - Shin L7 Nizer system TV reception! In the & machine, the local oscillation frequency for receiving a predetermined broadcasting channel is multiplied by 1i, and the receiving frequency is set to It has a programmable counter that can be changed to
The maximum value of the variable range of the programmable counter is set to a range narrower than the center frequency within the capture V range of the AFT circuit.
L Shinrely'f 7' Type 5 TV receiver A P
I-Circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58186246A JPS6077512A (en) | 1983-10-05 | 1983-10-05 | Aft circuit of pll synthesizer system television receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58186246A JPS6077512A (en) | 1983-10-05 | 1983-10-05 | Aft circuit of pll synthesizer system television receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6077512A true JPS6077512A (en) | 1985-05-02 |
Family
ID=16184903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58186246A Pending JPS6077512A (en) | 1983-10-05 | 1983-10-05 | Aft circuit of pll synthesizer system television receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6077512A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0257552A2 (en) * | 1986-08-20 | 1988-03-02 | Mitsubishi Denki Kabushiki Kaisha | Television signal selection device |
-
1983
- 1983-10-05 JP JP58186246A patent/JPS6077512A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0257552A2 (en) * | 1986-08-20 | 1988-03-02 | Mitsubishi Denki Kabushiki Kaisha | Television signal selection device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5079525A (en) | Audio-video modulator system on ic chip | |
JP2003506952A (en) | Clock synchronization system and method | |
US4021752A (en) | Phase locked loop for use with local oscillator | |
JP2001177779A (en) | Video intermediate frequency processor | |
JPS6077512A (en) | Aft circuit of pll synthesizer system television receiver | |
US6433830B1 (en) | Off-air phase lock technique | |
JP3053838B2 (en) | Video intermediate frequency circuit | |
JPS642294B2 (en) | ||
JP3314722B2 (en) | TV signal channel selection device | |
JPS6089155A (en) | Phase locked loop system | |
JPS61135227A (en) | Phase locked loop oscillator | |
JPS5814632A (en) | Signal receiving device | |
JPH06152457A (en) | Pll tuner | |
AU603216B2 (en) | Tweet elimination, or reduction, in superheterodyne receivers | |
JPS58177036A (en) | Am radio receiver | |
JPS61111015A (en) | Pll frequency synthesizer type tv receiver | |
JPS5881341A (en) | Receiver | |
JPH06152458A (en) | Pll tuner | |
JPH05252470A (en) | Intermediate frequency processing device | |
JPH0865651A (en) | Catv head-end device | |
JPS6363136B2 (en) | ||
JPH08195918A (en) | Digital/analog compatible receiver | |
JPS5857878A (en) | Modulator for catv screen | |
JPS58200635A (en) | Synthesizer system superheterodyne receiver | |
JPS63228818A (en) | Automatic frequency control circuit |