JPS6095958A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6095958A
JPS6095958A JP20431283A JP20431283A JPS6095958A JP S6095958 A JPS6095958 A JP S6095958A JP 20431283 A JP20431283 A JP 20431283A JP 20431283 A JP20431283 A JP 20431283A JP S6095958 A JPS6095958 A JP S6095958A
Authority
JP
Japan
Prior art keywords
semiconductor chips
semiconductor
islands
external leads
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20431283A
Other languages
Japanese (ja)
Inventor
Koichi Yajima
興一 矢嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20431283A priority Critical patent/JPS6095958A/en
Publication of JPS6095958A publication Critical patent/JPS6095958A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor memory storage capable of mounting with high density by sticking surfaces not mounted in two base body sections, on which semiconductor chips are mounted and to which wires are connected in a predetermined manner, together by a double-side adhesive tape and sealing the whole with a resin while leading out an external lead. CONSTITUTION:Semiconductor chips 11 and 11' are each fixed to the surfaces and backs of islands 15 and 15' for fastening the semiconductor chips in two base body sections, and each semiconductor chip is connected to external leads 12 and 12' by using wires 13 and 13'. Surfaces not mounted of the islands 15 and 15' are bonded with adhesives 21, and external leads 12 and 12' positioned on the outsides of the islands are unified by polyimide group both-side adhesive tapes 17 and 17'. The whole is sealed with a resin 22 while the external leads 12 and 12' are exposed to the outside. Accordingly, twice as many semiconductor chips as conventional devices can be mounted in the same area, and operation can be continued by the other chip even when one chip gets trouble.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は高密度実装が可能な半導体記憶装置に門する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor memory device that can be mounted at high density.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来の半導体装置なｍ／図に示す。この半導体装置は、
アイランドＳ上に半導体チップｌをグイボンディングし
、次にワイヤ３にて半導体デツプ／上のポンディングパ
ッドと内部リード６とを接続し、その後樹脂ダにてモー
ルドし、成形して完成する。近年高密度実装への要求は
ますます厳しくなってきている。従来の半導体装置で高
密度実装をするために、■外部リードの巾を細くしたり
、間隙を狭くしたりして半導体装置全体を小さくする、
■半導体チップ自体の集積度をあげてサイズを小さくす
る、■半導体装置の実装間隔を小さくする、等の対策が
とられている。しかしながらこれらの対策によっても要
求に応えるような高密度実装は困難であった。A conventional semiconductor device is shown in the figure. This semiconductor device is
The semiconductor chip 1 is strongly bonded onto the island S, and then the bonding pads on the semiconductor depth/above are connected to the internal leads 6 using wires 3, and then molded with resin and molded to complete the molding. In recent years, requirements for high-density packaging have become increasingly strict. In order to achieve high-density packaging with conventional semiconductor devices, it is necessary to reduce the overall size of the semiconductor device by reducing the width of the external leads and narrowing the gap.
Countermeasures are being taken, such as: (1) increasing the degree of integration of the semiconductor chip itself to reduce its size; (2) reducing the mounting interval of semiconductor devices. However, even with these measures, it has been difficult to achieve high-density packaging that meets the requirements.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情を考慮してなされたもので飛Ｐ的な高
密度実装が可能な半導体装１＾を提供することを目的と
する。The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device 1^ that can be mounted in a high-density manner.

〔発明の概要〕[Summary of the invention]

この目的を達成するために本発明による半導体装置は、
半導体チップがマウントされ電気的配置ｔ！ｉ！された
第１および第２の基体部を備え、これら第１および第一
の基体部の非マウント面を貼り合わせて封止成型したこ
とを／ｒ！１′徴と−３る。To achieve this objective, the semiconductor device according to the present invention includes:
The semiconductor chip is mounted and electrically arranged t! i! /r! that the non-mounting surfaces of the first and second base parts were bonded together and sealed and molded. 1' sign and -3.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例による半導体装置を第２図に示す。第
１の基体部は、テープ／７上のリードフレームのアイラ
ンド１３に半導体チップｌ／をダイボンディングし、次
にワイヤ１３により内部リード１６と半導体チップｌ１
間を配線して形成する。同様に第コの基体部はテープ／
７’上のリードフレームのアイランド１５’に半導体チ
ップ／／’をダイボンディングし、次にワイヤ７３′に
より内部リード７６′と半導体チップ／／’間を配線し
て形成する。そしてこれら第１および第コの基体部の非
マウント面を接着剤−／で貼り合せ、その後、樹脂刀で
モールドし、外部リード／、２．／、２′を切断して成
型する。第１および第コの基体部を貼り合せるための接
着剤としてはエポキシ系接着剤、ポリイミド系接着剤、
シリコン系接着剤が望ましいが、ポリイミド系両面テー
プにより貼り合せてもよい。またテープ／７゜７７′は
内部リード／Ａ、／Ａ’の範囲までであったが、外部リ
ード／２．／λ′下にまで設けるようにしてもよい。ま
た外部リードｌコ、ｌコ′は電気的に接触しても、しな
くともよいが、それに応じて半導体チップ１１゜／／’
の股引を変える必要がある。さらに外部リード／、２．
／：１’を曲げないフラットパッケージタイプにしても
よい。A semiconductor device according to an embodiment of the present invention is shown in FIG. The first base part is formed by die bonding the semiconductor chip l/ to the island 13 of the lead frame on the tape /7, and then using the wire 13 to connect the internal lead 16 to the semiconductor chip l1.
It is formed by wiring between the two. Similarly, the second base part is made of tape/
The semiconductor chip //' is die-bonded to the island 15' of the lead frame on the lead frame 7', and then the internal leads 76' and the semiconductor chip //' are interconnected using wires 73'. Then, the non-mounting surfaces of the first and second base portions are bonded together with an adhesive, and then molded with a resin blade, and the external leads are formed. /, 2' are cut and molded. Adhesives for bonding the first and second base parts include epoxy adhesive, polyimide adhesive,
A silicon adhesive is preferable, but a polyimide double-sided tape may be used for bonding. Also, tape /7°77' was up to the range of internal leads /A, /A', but external leads /2. /λ' may be provided. Also, the external leads L and L' may or may not be in electrical contact, but the semiconductor chip 11°//' may or may not be in electrical contact.
It is necessary to change the crotch pull. Furthermore, external leads/,2.
/:1' may be a flat package type that does not bend.

また、先の実施例では樹脂モールドしたが、セラミック
パッケージやサーディッグタイプのパッケージ等の他の
封止手段でもよい。また電気的配線方法はワイヤポンデ
ィング法に限らずフリップチップ方等のワイヤレスポン
ディング法でもよい。Further, although resin molding was used in the previous embodiment, other sealing means such as a ceramic package or a Cerdig type package may be used. Further, the electrical wiring method is not limited to the wire bonding method, but may also be a wireless bonding method such as a flip chip method.

〔発明の効果〕〔Effect of the invention〕

以上の通り本発明によれば同一面積に２倍の半導体チッ
プを実装することができ、飛躍的な高密度実装が可能で
ある。また一方の基体部の半導体チップが不良となって
も、他方の基体部の半導体チップにより動作が可能であ
り、実質的に故障Ｗ率を低下することができる。As described above, according to the present invention, twice as many semiconductor chips can be mounted on the same area, and dramatically high-density mounting is possible. Furthermore, even if the semiconductor chip in one base part becomes defective, the semiconductor chip in the other base part can operate, and the failure W rate can be substantially reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａｌ　ｌ　（ｂ）は従来の半シ！１体装αのｌ
！、Ｉ面図および平面図、第１図は本発明の一実施例１
・こよる゛１パ導体装置の断面図である。 ハ・・半導体チップ、コ用外部リード、３・・・ワイヤ
、ダ・・・樹脂、！・・・アイランド、６・・・内部リ
ード、／／、／／’・・・半導体チップ、／コ、／Ｊ’
・・・外部リード、／、３．　／３’−１フィーＹ、　
／に、　／！ｒ’−，，アイランド、／４　、　／Ａ　
’　・−・内部リード、コト・・接着剤、２２・・・樹
脂。 出願人代理人　猪　股　清 ？ｌ　図 朽　２　図Figure 1 (al l (b) shows the conventional half-shi!1 body α l
! , I side view and plan view, FIG. 1 is an embodiment 1 of the present invention.
・This is a sectional view of a single-pass conductor device. C...Semiconductor chip, external lead for C, 3...Wire, D...Resin,! ...Island, 6...Internal lead, //, //'...Semiconductor chip, /K, /J'
...external lead, /, 3. /3'-1 fee Y,
/ to, /! r'-,, island, /4, /A
' - Internal lead, adhesive, 22... resin. Applicant's agent Kiyoshi Inomata? l Diagram 2 Diagram

Claims (1)

【特許請求の範囲】[Claims] 半導体チップがマウントされ電気的配線された第１およ
び第２の基体部を備え、これら第１および第一の基体部
の非マウント面を貼り合せて封止成型したことを特徴と
する半増体装餞。A semi-expanded body comprising first and second base parts on which a semiconductor chip is mounted and electrically wired, and the non-mounted surfaces of the first and first base parts are bonded together and sealed. Loading.
JP20431283A 1983-10-31 1983-10-31 Semiconductor device Pending JPS6095958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20431283A JPS6095958A (en) 1983-10-31 1983-10-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20431283A JPS6095958A (en) 1983-10-31 1983-10-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6095958A true JPS6095958A (en) 1985-05-29

Family

ID=16488396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20431283A Pending JPS6095958A (en) 1983-10-31 1983-10-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6095958A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463253A (en) * 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US6069025A (en) * 1994-11-15 2000-05-30 Lg Semicon Co., Ltd. Method for packaging a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463253A (en) * 1990-03-15 1995-10-31 Fujitsu Limited Semiconductor device having a plurality of chips
US5479051A (en) * 1992-10-09 1995-12-26 Fujitsu Limited Semiconductor device having a plurality of semiconductor chips
US6069025A (en) * 1994-11-15 2000-05-30 Lg Semicon Co., Ltd. Method for packaging a semiconductor device

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