JPS6091646A - Plasma vapor growth - Google Patents

Plasma vapor growth

Info

Publication number
JPS6091646A
JPS6091646A JP19951283A JP19951283A JPS6091646A JP S6091646 A JPS6091646 A JP S6091646A JP 19951283 A JP19951283 A JP 19951283A JP 19951283 A JP19951283 A JP 19951283A JP S6091646 A JPS6091646 A JP S6091646A
Authority
JP
Japan
Prior art keywords
sample
bias voltage
film
plasma vapor
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19951283A
Other languages
Japanese (ja)
Inventor
Hidekazu Okabayashi
岡林　秀和
Mitsutaka Morimoto
光孝 森本
Toru Mogami
徹 最上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP19951283A priority Critical patent/JPS6091646A/en
Publication of JPS6091646A publication Critical patent/JPS6091646A/en
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/517—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)

Abstract

PURPOSE:To enable to control the film properties of an oxide film by a method wherein a plasma vapor growth is performed while bias voltage is being impressed on a sample or the sample holder. CONSTITUTION:Bias voltage is impressed 28 on a sample stand 26, SiH4, O2 and Ar are introduced 23 in a reaction chamber 21, high-frequency power 25 is supplied to an electrode 24, and SiO2 is deposited on a sample 17. According to this constitution, the depositing conditions of the SiO2 film can be controlled by changing the bias voltage, separatedly from impressed power for discharge plasma generation. Accordingly, the film properties of the SiO2 film can be controlled. For example, an SiO2 film, whose etching speed by hydrofluoric acid is smaller and whose coating at a step difference is also favorable, compared to an SiO2 film formed without impressing bias voltage, can be formed.

Description

【発明の詳細な説明】 本発明は、プラズマ気相成長忙よって薄膜を堆積する方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of depositing thin films by plasma vapor deposition.

従来のプラズマ気相成長（あるいはプラズマＣＶＤ　）
による薄膜の堆積法は、第１図に示した様な基本構成の
装置を用いて、反応室１１を真空排気系１２によりて排
気した後９反応ガス供給系１３より所定流量の反応ガス
を導入し、電極１４に電力供給機構１５より電力を供給
して反応室】１内に放電プラズマを発生せしめることに
より試料台１６上に置かれた試料１７０表面に薄膜を堆
積するというものである。この際、試料台１６は電気的
に接地して行われているので、試料１７表面の電位の制
御が行われていない。この様な状況でプラズマ気相成長
を行さと、放電プラズマを発生させるために電極１４に
供給される電力（あるいは電圧や電流）と反応室１１内
の真空度とは独立な関係にはないので、膜堆積の自由度
が少なく制御性が悪い。又、堆積された膜の緻密性や段
差部での被覆性等、膜質も充分ではないという問題があ
った。Conventional plasma vapor deposition (or plasma CVD)
The thin film deposition method uses an apparatus having the basic configuration as shown in FIG. Then, a thin film is deposited on the surface of a sample 170 placed on a sample stage 16 by supplying electric power to the electrode 14 from a power supply mechanism 15 to generate discharge plasma in the reaction chamber 1. At this time, since the sample stage 16 is electrically grounded, the potential on the surface of the sample 17 is not controlled. When performing plasma vapor phase growth under such conditions, there is no independent relationship between the power (or voltage or current) supplied to the electrode 14 to generate discharge plasma and the degree of vacuum in the reaction chamber 11. , the degree of freedom in film deposition is low and controllability is poor. Further, there was a problem that the film quality, such as the density of the deposited film and the ability to cover stepped portions, was not sufficient.

本発明の目的は、上記従来のプラズマ気相成長法におけ
る問題点を解決し得る新規なプラズマ気相成長法を提供
することである。An object of the present invention is to provide a novel plasma vapor phase epitaxy method that can solve the problems of the conventional plasma vapor phase epitaxy methods.

本発明による方法は、試料又は試料ホルダにバイアス電
圧を印加しながらプラズマ気相成長を行うことを特徴と
するものである。The method according to the present invention is characterized in that plasma vapor phase growth is performed while applying a bias voltage to the sample or sample holder.

本発明による方法によれば、試料又は試料台にバイアス
を印加しながらプラズマ気相成長が行われるので、放電
プラス１発生用の印加電力とは独立にバイアス気圧を変
えることにより膜の堆積条件を制御することができる、
従って膜特性の制御ができるという効果が生じる。バイ
アス電圧は、導電性薄膜の堆積忙対しては直流バイアス
を印加することもできるが、高周波バイアスは、導電性
薄膜の堆積に対しても絶縁性薄膜の堆積に対しても用い
ることができる。為周波バイアスを印加すると試料表面
には実効的に負の直流バイアスが発生する。この直流バ
イアスの効果により試料表面は正イオン衝撃を受けるの
で、本発明による方法においては、試料はイオン衝撃を
受けながらプラズマ気相成長により膜の堆積が行われる
。従って適切なバイアス条件を選ぶことにより緻密性の
向上や段差部での被覆性の向上を達成することができる
。According to the method of the present invention, plasma vapor phase growth is performed while applying a bias to the sample or sample stage, so the film deposition conditions can be adjusted by changing the bias pressure independently of the applied power for generating a discharge plus one. can be controlled,
Therefore, there is an effect that the film properties can be controlled. The bias voltage can be applied as a direct current bias for the deposition of conductive thin films, while the radio frequency bias can be used for both conductive thin film deposition and insulating thin film deposition. Therefore, when a frequency bias is applied, an effective negative DC bias is generated on the sample surface. Since the sample surface is bombarded with positive ions due to the effect of this DC bias, in the method according to the present invention, a film is deposited by plasma vapor deposition while the sample is bombarded with ions. Therefore, by selecting appropriate bias conditions, it is possible to improve the density and the coverage of stepped portions.

次に、図を用いて本発明による方法の実施例を説明する
。第２図は本発明の方法の実施例において用いたプラズ
マ気相成長装置の構成図である。Next, an embodiment of the method according to the present invention will be explained using the figures. FIG. 2 is a block diagram of a plasma vapor phase growth apparatus used in an embodiment of the method of the present invention.

従来の方法において用いられていたｉ１図に示した構成
との違いは、試料台２６が接地されていすバイアス電圧
印加機構２８によってバイアス電圧が印加されているこ
とである。実施例においては、ガス導入系２３よりシラ
ン（Ｓ　ｉＨ４）ガス、酸素ガス及びアルゴンガスを導
入し、電極２４に電力印加機構２５より高周波電力を供
給することによりシラシガス、酸素ガス及びアルゴンガ
スの放電プラズマを発生せしめ、かつバイアス印加機製
８により試料台２６に高周波バイアスを印加しながら酸
化シリコン膜を試料２７表面に堆積した。この際放電プ
ラズマ発生用の高周波電力は約２００Ｗで反応室２１内
の真空度は約８０　Ｐａであった。The difference from the configuration shown in FIG. i1 used in the conventional method is that the sample stage 26 is grounded and a bias voltage is applied by a chair bias voltage application mechanism 28. In the embodiment, silane (SiH4) gas, oxygen gas, and argon gas are introduced from the gas introduction system 23, and high-frequency power is supplied to the electrode 24 from the power application mechanism 25 to discharge the silane gas, oxygen gas, and argon gas. A silicon oxide film was deposited on the surface of the sample 27 while generating plasma and applying a high frequency bias to the sample stage 26 using a bias application device 8. At this time, the high frequency power for generating discharge plasma was about 200 W, and the degree of vacuum in the reaction chamber 21 was about 80 Pa.

又、高周波バイアろＫよって誘起された試料台２６の直
流バイアスは約−５０ｖであった。上記実施例において
堆積した酸化シリコン膜は、従来方法によってバイアス
を印加しないで行ったものに比してフッ酸によるエツチ
ング速度が小さくかつ段差部での被覆性も良好であった
。Further, the DC bias of the sample stage 26 induced by the high frequency via filter K was about -50V. The silicon oxide film deposited in the above example had a lower etching rate with hydrofluoric acid and better coverage at stepped portions than that deposited by the conventional method without applying a bias.

なお、上記実施例においては、放電プラズマ発生用の電
極が、反応室内に配置された構成を用いたが、反応室外
壁に放電プラズマ発生用のコイル又は電極を取付けた構
成に対しても本発明による方法が有効であることは明ら
かである。In the above embodiment, the electrode for generating discharge plasma was arranged inside the reaction chamber, but the present invention can also be applied to a configuration in which the coil or electrode for generating discharge plasma is attached to the outer wall of the reaction chamber. It is clear that the method described above is effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のプラズマ気相成長法において用いられて
いる装置の構成図。第２図は本発明による方法の実施例
において用いた装置の構成図。 １１．２１・・・・・・反応室、１２．２２・・・・・
・真空排気系、１３．２３・・・・・・ガス導入系、１
４．２４・・・・・・放電用電極、１５．２５・・・・
・・放電用電力供給機構、１６．２６・・・・・・試料
台、１７．２７・・・・・・試料、２８・・・・・・バ
イアス電圧印加機構。 ７１図 ４ Ｉｒ２図 ４FIG. 1 is a configuration diagram of an apparatus used in a conventional plasma vapor phase epitaxy method. FIG. 2 is a block diagram of an apparatus used in an embodiment of the method according to the present invention. 11.21...Reaction chamber, 12.22...
・Vacuum exhaust system, 13.23...Gas introduction system, 1
4.24... Electrode for discharge, 15.25...
...discharge power supply mechanism, 16.26...sample stage, 17.27...sample, 28...bias voltage application mechanism. 71Figure 4 Ir2Figure 4

Claims (1)

【特許請求の範囲】[Claims] 試料又は試料ホルダにバイアス電圧を印加しながらプラ
ズマ気相成長によりて試料に薄膜を堆積することを特徴
とするプラズマ気相成長法。A plasma vapor phase epitaxy method characterized by depositing a thin film on a sample by plasma vapor phase epitaxy while applying a bias voltage to the sample or sample holder.
JP19951283A 1983-10-25 1983-10-25 Plasma vapor growth Pending JPS6091646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19951283A JPS6091646A (en) 1983-10-25 1983-10-25 Plasma vapor growth

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19951283A JPS6091646A (en) 1983-10-25 1983-10-25 Plasma vapor growth

Publications (1)

Publication Number Publication Date
JPS6091646A true JPS6091646A (en) 1985-05-23

Family

ID=16409048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19951283A Pending JPS6091646A (en) 1983-10-25 1983-10-25 Plasma vapor growth

Country Status (1)

Country Link
JP (1) JPS6091646A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729897A (en) * 1993-06-25 1995-01-31 Nec Corp Manufacture of semiconductor device
KR20030072648A (en) * 2002-03-06 2003-09-19 김용구 Supplementary feed for stock breeding and producing method of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368171A (en) * 1976-11-30 1978-06-17 Hitachi Ltd Method and apparatus for plasma treatment
JPS58124223A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Plasma treating device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368171A (en) * 1976-11-30 1978-06-17 Hitachi Ltd Method and apparatus for plasma treatment
JPS58124223A (en) * 1982-01-20 1983-07-23 Hitachi Ltd Plasma treating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729897A (en) * 1993-06-25 1995-01-31 Nec Corp Manufacture of semiconductor device
KR20030072648A (en) * 2002-03-06 2003-09-19 김용구 Supplementary feed for stock breeding and producing method of the same

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