JPS6086934A - Multi-frame transmission system - Google Patents

Multi-frame transmission system

Info

Publication number
JPS6086934A
JPS6086934A JP19430383A JP19430383A JPS6086934A JP S6086934 A JPS6086934 A JP S6086934A JP 19430383 A JP19430383 A JP 19430383A JP 19430383 A JP19430383 A JP 19430383A JP S6086934 A JPS6086934 A JP S6086934A
Authority
JP
Japan
Prior art keywords
frame
data
signal
signals
transmission system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19430383A
Other languages
Japanese (ja)
Inventor
Tatsuo Yoshie
吉江　達夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19430383A priority Critical patent/JPS6086934A/en
Publication of JPS6086934A publication Critical patent/JPS6086934A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To increase the data transmisson speed and to reduce the hardware needed for frame pull-in by changing the bit length of a frame signal and therefore discriminating easily each frame. CONSTITUTION:A transmission system is formed with frame, clock and data signals. The bit length is set at an amount equivalent to two bits for the 1st and 2nd frame signals respectively, and data A1-D and A2-D contained in said frame signals are discriminated respectively. Then the transmission time of data is shortened and the data signal within each frame is discriminated. Thus the hardware for frame pull-in is reduced.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、データ、フレーム、クロックの各信号を用い
たマルチフレーム伝送方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multi-frame transmission system using data, frame, and clock signals.

〔発明の背景〕[Background of the invention]

従来のマルチフレーム伝送方式を、第１図及び第２図を
用いて説明する。A conventional multi-frame transmission system will be explained using FIGS. 1 and 2.

第１図は、データ信号、データ信号列の先頭を示すビッ
ト長１（クロック１周期分）のフレーム信号、データ信
号に同期したクロック信号の各信号を個別にかつ連続的
に伝送する方式を例に採ったものであり、１フレームに
Ａ−Ｄの４ビツトの情報を伝送していることを示してい
る。Figure 1 shows an example of a method for individually and continuously transmitting each signal: a data signal, a frame signal with a bit length of 1 (one clock period) indicating the beginning of a data signal string, and a clock signal synchronized with the data signal. This figure was taken in 1 frame, indicating that 4 bits of information A to D are transmitted in one frame.

第２図は、第１図において、Ａのデータ位置を用いて従
来方式により２つの信号Ａ、とＡ、を伝送するマルチフ
レーム伝送方式を示している。FIG. 2 shows a multi-frame transmission system in which two signals A and A are transmitted in a conventional manner using the data position of A in FIG.

即チ、　Ａｙというマルチフレーム内の先頭を示す信号
（以下マルチフレーム信号という）を用いてＡ、とＡ２
の２つの信号を伝送する方式であり。That is, A, and A2 using the signal Ay indicating the beginning of the multiframe (hereinafter referred to as multiframe signal).
This is a method of transmitting two signals.

Ａ、としては、２値信号の１と０を交互に繰り返スハタ
ーンが一般に用いられている。As A, a shatern is generally used in which a binary signal of 1 and 0 is alternately repeated.

しかしながら、この伝送方式では。However, with this transmission method.

（１）データ信号の組合せによっては、擬似的にマルチ
フレーム信号が検出され、誤った位置でマルチフレーム
同期がとられてしまう。(1) Depending on the combination of data signals, a multi-frame signal may be detected in a pseudo manner, and multi-frame synchronization may be achieved at an incorrect position.

（２）　マルチフレーム信号Ａｐ　カ必要なため、マル
チフレーム内のデータ送度が遅くなる。(2) Since the multi-frame signal Ap is required, the data transmission rate within the multi-frame becomes slow.

（５）　マルチフレーム信号Ａ、を探し出すための７１
−ド箪、及び引込時間が犬となる。(5) 71 to find multi-frame signal A.
- The closing time and withdrawal time become a dog.

等の欠点があった。There were drawbacks such as.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記従来技術の欠点をなくし、簡単な
構成のマルチフレーム伝送方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a multi-frame transmission system with a simple configuration.

〔発明の概要〕[Summary of the invention]

本発明ではこの目的を実現するために、データ信号の中
に組み込まれていたマルチフレーム信号を取り除き、フ
レーム信号のビット長によりマルチフレーム信号を表現
した。In order to achieve this objective, the present invention removes the multi-frame signal incorporated in the data signal and expresses the multi-frame signal using the bit length of the frame signal.

〔発明の実施例〕[Embodiments of the invention]

以下１本発明の一実施例を第６図により説明する。 An embodiment of the present invention will be described below with reference to FIG.

第３図は、第２図に示した従来技術によるマルチフレー
ム伝送を５本発明による方式で伝送した場合の一例を示
すものである。FIG. 3 shows an example in which the multi-frame transmission according to the prior art shown in FIG. 2 is transmitted using the method according to the present invention.

即チ、第１フレームのフレーム信号のビット長を２ビッ
ト分とることにより、そのフレームが第１フレームであ
ることを示し、そのフレームにあるデータがＡ１である
ことを識別させるようにしたものである。In other words, by taking the bit length of the frame signal of the first frame to 2 bits, it is indicated that the frame is the first frame, and the data in that frame is identified as A1. be.

上記実施例の説明では、フレーム信号のビット長を２ビ
ット分として、又マルチフレームで伝送される信号がＡ
、とＡ２の２つとして説明したが１本発明はこれに限定
されるものではなく。In the explanation of the above embodiment, the bit length of the frame signal is assumed to be 2 bits, and the signal transmitted in multi-frame is A.
, and A2, but the present invention is not limited thereto.

フレーム信号のビット長を５ビット以上、或は複数のビ
ット長の組合せよりなるマルチフレーム構成を採ること
も可能であり、又５つ以上の信号を伝送すること、バー
スト的な信号の伝送に適用可能であることは２本実施例
の説明から容易に理解されるところである。It is also possible to adopt a multi-frame configuration in which the bit length of the frame signal is 5 bits or more, or a combination of multiple bit lengths, and it is also applicable to transmitting 5 or more signals and transmitting burst signals. That this is possible will be easily understood from the description of the two embodiments.

〔発明の効果〕〔Effect of the invention〕

以上体へたように１本発明によれば、従来のようにデー
タ信号の組合せにより擬似的にマルチフレーム同期がと
れてしまうこともなく、また、マルチフレーム信号がデ
ータ信号に入っていないためマルチフレーム内のデータ
の伝送速度が遅くなるということもなく、さらにマルチ
フレーム同期引込みのためのハード量が小さく。In summary, according to the present invention, pseudo multi-frame synchronization is not achieved due to the combination of data signals as in the past, and since the multi-frame signal is not included in the data signal, The transmission speed of data within a frame does not slow down, and the amount of hardware needed to pull in multi-frame synchronization is small.

時間が短くなるという効果がある。This has the effect of shortening the time.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、データ、フレーム、クロックの各信号を個別
に連続的に伝送する方式の説明図。 第２図は、従来技術によるマルチフレーム伝送方式の説
明図、第６図は１本発明によるマルチフレーム伝送方式
の一実施例の説明図である。 代理人弁理士　高　橋　明　夫 第７　図 第２　図FIG. 1 is an explanatory diagram of a method for individually and continuously transmitting data, frame, and clock signals. FIG. 2 is an explanatory diagram of a multi-frame transmission system according to the prior art, and FIG. 6 is an explanatory diagram of an embodiment of the multi-frame transmission system according to the present invention. Representative Patent Attorney Akio Takahashi Figure 7 Figure 2

Claims (1)

【特許請求の範囲】[Claims] １、　データ、フレーム、クロックの各信号を用いた伝
送方式において、フレーム信号のビット長を変化させる
ことにより、各フレームを識別することを特徴とするマ
ルチフレーム伝送方式。1. A multi-frame transmission method that uses data, frame, and clock signals and is characterized in that each frame is identified by changing the bit length of the frame signal.
JP19430383A 1983-10-19 1983-10-19 Multi-frame transmission system Pending JPS6086934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19430383A JPS6086934A (en) 1983-10-19 1983-10-19 Multi-frame transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19430383A JPS6086934A (en) 1983-10-19 1983-10-19 Multi-frame transmission system

Publications (1)

Publication Number Publication Date
JPS6086934A true JPS6086934A (en) 1985-05-16

Family

ID=16322355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19430383A Pending JPS6086934A (en) 1983-10-19 1983-10-19 Multi-frame transmission system

Country Status (1)

Country Link
JP (1) JPS6086934A (en)

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