JPS6471232A - Transmission system for frame synchronizing information - Google Patents

Transmission system for frame synchronizing information

Info

Publication number
JPS6471232A
JPS6471232A JP62227918A JP22791887A JPS6471232A JP S6471232 A JPS6471232 A JP S6471232A JP 62227918 A JP62227918 A JP 62227918A JP 22791887 A JP22791887 A JP 22791887A JP S6471232 A JPS6471232 A JP S6471232A
Authority
JP
Japan
Prior art keywords
bit
frame
violation
main
transmission system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227918A
Other languages
Japanese (ja)
Inventor
Koichi Niihori
Akito Oyamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62227918A priority Critical patent/JPS6471232A/en
Publication of JPS6471232A publication Critical patent/JPS6471232A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To establish the synchronization in a short time by forming >= one synchronizing signal among m-set of signals by code rule violation so as to superimpose the signal to a prescribed location in a frame in sending N-bit of data while it is divided into m-set of main frames each comprising M-bit. CONSTITUTION:The main frame M (bit 1024) is sent while being formed as a multi-frame of collection of m (=48)-set. A head bit F of 1st, 9th-41th main frames is formed by a bit of code rule violation V and the frame number of the relevant frame is superimposed by the code rule violation V onto the 2nd-7th bit data of each main frame. In allocating 2<0> to the 7th bit, 2<1> to the 6th bit -2<5> to the 2nd bit, the presence of the violation rule represents 1 and the absence of it shows 0. For example, in the case shown in figure, for example, the result is 1X2<0>+1(X)2<3>+1X2<5> and the number of the 41st main frame is detected easily to reduce the time of frame synchronization.
JP62227918A 1987-09-11 1987-09-11 Transmission system for frame synchronizing information Pending JPS6471232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227918A JPS6471232A (en) 1987-09-11 1987-09-11 Transmission system for frame synchronizing information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227918A JPS6471232A (en) 1987-09-11 1987-09-11 Transmission system for frame synchronizing information

Publications (1)

Publication Number Publication Date
JPS6471232A true JPS6471232A (en) 1989-03-16

Family

ID=16868338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227918A Pending JPS6471232A (en) 1987-09-11 1987-09-11 Transmission system for frame synchronizing information

Country Status (1)

Country Link
JP (1) JPS6471232A (en)

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