JPS6079817A - Window comparator - Google Patents
Window comparatorInfo
- Publication number
- JPS6079817A JPS6079817A JP18724583A JP18724583A JPS6079817A JP S6079817 A JPS6079817 A JP S6079817A JP 18724583 A JP18724583 A JP 18724583A JP 18724583 A JP18724583 A JP 18724583A JP S6079817 A JPS6079817 A JP S6079817A
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- window
- collector
- width
- input voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
く技術分野〉
本発明は複数個のウィンドウを有するウィンドウコンパ
レータに閃するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention is directed to a window comparator having a plurality of windows.
〈従来技術〉
第１図に従来の一路例を示す。図は２回路分で、非常に
多くの素子を要している。また、ウィンドウの幅は簡単
には変更できない。<Prior Art> Fig. 1 shows a conventional one-way example. The figure shows two circuits, which require a large number of elements. Also, the width of the window cannot be easily changed.
〈発明の目的〉
本発明は、複数個のウィンドウを持つウィンドウコンパ
レータを少ない素子数で実現でき、更にウィンドウの幅
を定電流源の電流の値の比を変えることにより自由に設
定できるようにしたものである。<Object of the Invention> The present invention enables a window comparator having multiple windows to be realized with a small number of elements, and further allows the width of the window to be freely set by changing the ratio of the current values of the constant current source. It is something.
〈実施例〉
以下第２図〜第７図に従って本発明の一実施例を説明す
る。<Example> An example of the present invention will be described below with reference to FIGS. 2 to 7.
第２図は一実施例を示す回路図である。図は３回路分を
示している。Ｃ８１，Ｃ８２，Ｃ８３は定電流源で、そ
れぞれの電流値は１１．Ｉ２．Ｉ３である。FIG. 2 is a circuit diagram showing one embodiment. The figure shows three circuits. C81, C82, and C83 are constant current sources, each with a current value of 11. I2. It is I3.
Ｑｌ、ＱＲはベースにそれぞれ入力電圧Ｖ Ｉ Ｎ ％
比較電圧ｖＲが印加されるトランジスタで、各エミッタ
を定電流源Ｃ８２に共通接続している。なお、各対（ｎ
、ｎ＋１．ｎ＋２を何して示す）において、Ｑ＋のベー
スには共通の入力電圧ＶＩＮが印加されるが、ＱＲのベ
ースにはそれぞれ異なる比較電段の対におけるＱｌのコ
レクタが同じ定電流源Ｃ５Ｉに接続される。Ｑｏは出力
用トランジスタで、コレクタに定電流源Ｃ８３を接続す
るとともに、ベースをＱｒ＜のコレクタおよび前段Ｑ■
のコレクタと定電流源Ｃ８１との接続点に接続してい′
る。定電流源ｃｓ２．ｃｓ３の他端は電源ＶＣＣに、定
電流源Ｃ８１、トランジスタＱｏのエミッタはＧＮＤ（
グランド）に接続される。Ql and QR are input voltage V I N % at the base respectively.
These are transistors to which a comparison voltage vR is applied, and each emitter is commonly connected to a constant current source C82. Note that each pair (n
, n+1. n+2), a common input voltage VIN is applied to the base of Q+, but the collectors of Ql in each pair of different comparison stages are connected to the same constant current source C5I to the base of QR. Ru. Qo is an output transistor whose collector is connected to a constant current source C83, and whose base is connected to the collector of Qr< and the previous stage Q■
Connected to the connection point between the collector and constant current source C81.
Ru. Constant current source cs2. The other end of cs3 is connected to the power supply VCC, the constant current source C81 is connected, and the emitter of the transistor Qo is connected to GND (
ground).
第３図は入力電圧ＶＩＮに対するＱｌ（。）とＱＲ（ｎ
）のコレクタ電流、第４図は同Ｑｌ（。＋１）とＱＲ（
。＋１）のコレクタ電流を示すものである。Ｑｌ（□）
とＱＲ（。）の対は比較電圧ＶＲ（ｎ）、ＱＩ（ｎ＋１
）とＱＲ（。＋１）は比較電圧ｖＲ（。＋１）近辺で変
化する。入力電圧ＶＩＮが比較電圧ＶＲ（ｎ）（又はＶ
Ｒ（ｎ＋１））より低いとき、Ｑｌ（□）（又はＱｌ（
ｎ＋１））側のコレクタ電流が１２で、高くなればＱＲ
（ｎ）（又はＱＲ（ｎ＋１））側のコレクタ電流がＩ２
となる。なお両コレクタ電流の和は定電流源Ｃ８２で定
められＩ２である。Figure 3 shows Ql(.) and QR(n
), Figure 4 shows the collector current of Ql(.+1) and QR(
. +1) collector current. Ql (□)
The pair of and QR(.) is the comparison voltage VR(n), QI(n+1
) and QR(.+1) change around the comparison voltage vR(.+1). The input voltage VIN is the comparison voltage VR(n) (or V
When lower than R(n+1)), Ql(□)(or Ql(
The collector current on the n+1)) side is 12, and if it becomes higher, QR
(n) (or QR(n+1)) side collector current is I2
becomes. Note that the sum of both collector currents is determined by the constant current source C82 and is I2.
第３図のＱｌ（ｎ）のコレクタ電流と第４図のＱＲ（ｎ
＋１）１のコレクタ電流だけを抜き出すと第５図（ａ）
のようになる。ＱＩ（。）とＱＲ（ｎ＋１）のコレクタ
は、前述したように、そのコレクタ同志を接続してかつ
定電流源ｃｓ１に接続される。Ｑｌ（ｎ）とＱＲ（ｎ＋
１）のいずれのコレクタ電流も１１の電流値を下まわっ
ている範囲Ｗでは、トランジスタＱｏ（ｎ＋１）にベー
ス電流が供給されず、従ってＱＯ（。＋１）はオフ状態
となり出力（電流でも可）Ｏｎ＋ｔはＨｌとなる。Ｗは
ウィンドウの幅に相当して、第５図（ａ）（ｂ）に図示
のように１１の電流値を小さくするほどＷは小さくなる
ことが分る。Collector current of Ql(n) in Figure 3 and QR(n) in Figure 4
If only the collector current of +1)1 is extracted, Figure 5 (a)
become that way. As described above, the collectors of QI(.) and QR(n+1) are connected together and connected to the constant current source cs1. Ql(n) and QR(n+
In range W where all collector currents in 1) are below the current value in 11, no base current is supplied to transistor Qo(n+1), and therefore QO(.+1) is in an off state and output (can be current). On+t becomes Hl. W corresponds to the width of the window, and as shown in FIGS. 5(a) and 5(b), it can be seen that the smaller the current value of 11, the smaller W becomes.
第６図に本実施例の入出力特性を示す。出力０（ｎ）は
入力電圧ＶＲ（ｎ−１）〜Ｖ Ｒ（ｎ ）間−１０（ｎ
＋１）はＶＲ（ｎ）〜ＶＲ（ｆｉ＋１）間Ｘ０（ｎ＋２
）はＶＲ（ｆｉ＋１）〜ｖＲ（ｎ＋２）間の幅Ｗの範囲
でそれぞれＨｉを出力する。FIG. 6 shows the input/output characteristics of this embodiment. The output 0(n) is -10(n) between the input voltage VR(n-1) and VR(n)
+1) is X0(n+2) between VR(n) and VR(fi+1)
) outputs Hi in the range of width W between VR(fi+1) and vR(n+2).
第７図は具体的な実現例−を示すものである。FIG. 7 shows a concrete implementation example.
上述のように本例によれば、例えば従来の２回路分以上
の素子数で３回路分を構成でき、ウィンドｒ＞、、、？
幅は定電流源Ｃ８１・Ｃ８２の電流の値の比Ｉ２／′１
１を変えることにより自由に設定できる。As described above, according to this example, for example, three circuits can be configured with the number of elements equal to or more than the conventional two circuits, and the window r>,...?
The width is the ratio of the current values of constant current sources C81 and C82, I2/'1
It can be set freely by changing 1.
ご１
１２と１１の比はどちらか一方を固定として他方を変化
させればよい。1 The ratio between 12 and 11 can be fixed by fixing one and changing the other.
本例において、ＰＮＰ ）ランジスタとＮＰＮ ）ラン
ジスタを逆にした構成も同様に可能であることは明らか
である。In this example, it is clear that a configuration in which the PNP) transistor and the NPN) transistor are reversed is also possible.
〈発明の効果〉
以−１−のように本発明は、素子数を少なくして複数個
のウィンドウを持つものを構成でき、またウィンドウの
幅の設定もきわめて容易であり、実用価値の高い有益な
ウィンドウコンパレータが提供できる。<Effects of the Invention> As described in -1- below, the present invention can reduce the number of elements and configure a device with a plurality of windows, and it is also extremely easy to set the width of the window, which is useful and has high practical value. window comparator can be provided.
第１図は従来例を示す回路図・第２図は本発明の一実施
例を示す回路図、第３図〜第６図は入力電圧に対する要
部電流又は出方の様子を示す特性図、第７図は具体的実
現例を示す回路図である。
Ｃ５，・Ｃ８２定電流源、ＱＩ・ＱＲ・・・トランジス
タ、ＱＯ出力トランジスタ、ＶＩＮ・・−人力電圧、ｖ
Ｒ−比較電圧、０・・出力。
九。
■、φ）
代理人 弁理士 福 士 愛 彦（他２名）第 Ｉ 図
第 ３ 図
第 ４ 図
１Fig. 1 is a circuit diagram showing a conventional example, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Figs. FIG. 7 is a circuit diagram showing a specific implementation example. C5, C82 constant current source, QI/QR...transistor, QO output transistor, VIN...-human power voltage, v
R-comparison voltage, 0...output. Nine. ■、φ) Agent Patent attorney Aihiko Fukushi (and 2 others) Figure I Figure 3 Figure 4 Figure 1
Claims (1)
び比較電圧を印加した複数対のトランジスタを設け、比
較電圧を印加したトランジスタの他端と、前段対の入力
電圧を印加したトランジスタの他端とをもう一つの定電
流源に接続し、上記各定電流源の電流の値によりウィン
ドウの幅を設定してなることを特徴とするウィンドウコ
ンパレータ。1. A plurality of pairs of transistors connected to a constant current source and having an input voltage and a comparison voltage applied to their respective bases are provided, and the other end of the transistor to which the comparison voltage is applied is connected to the other end of the transistor to which the input voltage of the previous pair is applied. is connected to another constant current source, and the width of the window is set according to the current value of each of the constant current sources.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18724583A JPS6079817A (en) | 1983-10-06 | 1983-10-06 | Window comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18724583A JPS6079817A (en) | 1983-10-06 | 1983-10-06 | Window comparator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6079817A true JPS6079817A (en) | 1985-05-07 |
Family
ID=16202584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18724583A Pending JPS6079817A (en) | 1983-10-06 | 1983-10-06 | Window comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079817A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56168168A (en) * | 1980-05-29 | 1981-12-24 | Toshiba Corp | Window comparator circuit |
-
1983
- 1983-10-06 JP JP18724583A patent/JPS6079817A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56168168A (en) * | 1980-05-29 | 1981-12-24 | Toshiba Corp | Window comparator circuit |
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