JPS607771A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS607771A JPS607771A JP11512483A JP11512483A JPS607771A JP S607771 A JPS607771 A JP S607771A JP 11512483 A JP11512483 A JP 11512483A JP 11512483 A JP11512483 A JP 11512483A JP S607771 A JPS607771 A JP S607771A
- Authority
- JP
- Japan
- Prior art keywords
- region
- base
- layer
- collector
- type gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003321 amplification Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置に係り、特にへテロバイポーラトラ
ンジスタの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to the structure of a heterobipolar transistor.
ヘテロバイポーラトランジスタ（以下ＨＢＴという）は
バンドギャップの異なる２種の半導体により形成される
ヘテロ接合をバイポーラトランジスタのエミッタ・ベー
ス接合として用いる。その一般的な構造としては、バン
ドギャップエネルギの大きなＮ型半導体でエミッタを形
成し、バンドギャップエネルギの小さなＰ型、Ｎ型半導
体でベース、コレクタを形成している。A hetero-bipolar transistor (hereinafter referred to as HBT) uses a heterojunction formed by two types of semiconductors with different band gaps as an emitter-base junction of the bipolar transistor. In its general structure, the emitter is formed of an N-type semiconductor with a large band gap energy, and the base and collector are formed with P-type and N-type semiconductors with a small band gap energy.
このような構造を有するＨＢＴでは、エミッタからベー
スには電子は容易に注入され得るが、ベース中の正孔は
、バンドギャップエネルギの違いのためにエミッタ・ベ
ース間に生じているエネルギ障壁にさえぎられてほとん
どエミッタへ注入されず、従って大きなエミッタ注入効
果が実現でき、電流増幅率の大きなトランジスタが得ら
れる。さらにこの事はホモバイポーラトランジスタのよ
うにエミッタとベースのキャリア濃度比を大きくとらな
くても十分大きな電流増幅率が得られることにつながり
、高濃度のベースを採用し、ベース抵抗を小さくするこ
とが可能となる。In an HBT with such a structure, electrons can be easily injected from the emitter to the base, but holes in the base are blocked by the energy barrier created between the emitter and base due to the difference in band gap energy. Therefore, a large emitter injection effect can be realized, and a transistor with a large current amplification factor can be obtained. Furthermore, this means that a sufficiently large current amplification factor can be obtained without having a large carrier concentration ratio between the emitter and the base as in a homo-bipolar transistor, and it is possible to use a highly concentrated base and reduce the base resistance. It becomes possible.
次にＨＢＴとして最も一般的なＡｌＧａＡｓ−ＧａＡｓ
系ＨＢＴの構造を第１図で説明する。Next, AlGaAs-GaAs is the most common HBT.
The structure of the system HBT will be explained with reference to FIG.
即ち、コレクタ電極（１）となる高濃度Ｎ型ＧａＡｓ基
板にコレクタ領域（２）となるＮ型ＧａＡｓエピタキシ
ャル層、ベース領域（３）となるＰ型ＧａＡｓ層、エミ
ッタ領域（４）となるＮ型ＡｌＧａＡｓ層、キャップ層
（５）と呼ばれるＮ型ＧａＡｓ層からなり、ベース領域
（３）となるＰ型ＧａＡｓ層はキャリア濃度が例えば１
０１８〜１０１９ｃｍ−３、厚さは０．１〜０．２μｍ
、エミッタ領域（４）となるＮ型ＡｌＧａＡｓ層はキャ
リア濃度が例えば１〜５×１０１６ｃｍ−３、厚さは０
．２〜１．０μｍで２０〜５０モル％のＡｌＡｓを含ん
でおりキャップ層（５）となるＮ型ＧａＡｓ層（５）は
エミッタ領域（４）のＡｌが酸化することを防止するた
め設けられているものであり、１〜３×１０１８のキャ
リア濃度を有している。そしてコレクタ（ｃ）はコレク
タ電極（１）に、ベース（Ｂ）はベース領域（３）に、
またエミッタ（Ｅ）は、キャップ層（５）にそれぞれ形
成された斜線で示す導電層に接続されている。That is, a highly doped N-type GaAs substrate becomes the collector electrode (1), an N-type GaAs epitaxial layer becomes the collector region (2), a P-type GaAs layer becomes the base region (3), and an N-type becomes the emitter region (4). It consists of an AlGaAs layer and an N-type GaAs layer called a cap layer (5), and the P-type GaAs layer that becomes the base region (3) has a carrier concentration of, for example, 1.
018~1019cm-3, thickness 0.1~0.2μm
, the N-type AlGaAs layer serving as the emitter region (4) has a carrier concentration of, for example, 1 to 5 x 1016 cm-3 and a thickness of 0.
．． An N-type GaAs layer (5) having a diameter of 2 to 1.0 μm and containing 20 to 50 mol % of AlAs and serving as a cap layer (5) is provided to prevent Al in the emitter region (4) from oxidizing. It has a carrier concentration of 1 to 3×10 18 . The collector (c) is connected to the collector electrode (1), the base (B) is connected to the base region (3),
Further, the emitters (E) are connected to conductive layers shown by diagonal lines formed on the cap layer (5).
このようなＨＢＴはシリコントランジスタに比較し次の
ようなメリットを有する。Such an HBT has the following advantages compared to a silicon transistor.
（１）エミッタ１濃度が低いためにエミッタ・ベース間
容量が同一形状で比較すれば小さくなる。(1) Since the emitter 1 concentration is low, the capacitance between the emitter and the base becomes smaller when compared with the same shape.
（２）ベース濃度が高いためにベース抵抗が小さくなる
。(2) Since the base concentration is high, the base resistance becomes small.
（３）高い電流増幅率が得られる。(3) A high current amplification factor can be obtained.
これらメリットはトランジスタの高速化あるいは低雑音
化にとって非常に有利であるが、実際にはシリコントラ
ンジスタに比較して性能のすぐれたＨＢＴは出現してい
ない。Although these advantages are very advantageous for increasing the speed and reducing noise of transistors, in reality, no HBT with superior performance compared to silicon transistors has appeared.
これは従来のＨＢＴの構造がメサ構造であり、シリコン
トランジスタで実現されているような微細な構造が出来
にくいのが主な理由である。更に具体的に説明すると、
ベース・コレクタ間接合面積を小さくすることが出来に
くいために、接合容量を小さくすることが出来ない。こ
のコレクタ容量は本発明で扱う狭いベースを有するトラ
ンジスタにおいてはスイッチング速度に比例的に影響す
るため第１図に示すようなＨＢＴではスイッチング速度
を高めるのは困難であった。The main reason for this is that the structure of a conventional HBT is a mesa structure, which makes it difficult to create a fine structure like that achieved with silicon transistors. To be more specific,
Since it is difficult to reduce the base-collector junction area, it is impossible to reduce the junction capacitance. Since this collector capacitance proportionally affects the switching speed in a transistor having a narrow base, which is used in the present invention, it has been difficult to increase the switching speed in an HBT as shown in FIG.
本発明は前述した問題点に鑑みなされたものであり、絶
縁性または半絶縁性の半導体基板を用いたベース・コレ
クタ間の接合容量の小さいＨＢＴとしての半導体装置を
提供することを目的とする。The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor device as an HBT that uses an insulating or semi-insulating semiconductor substrate and has a small base-collector junction capacitance.
本発明は絶縁性あるいは半絶縁性の半導体基板の表面部
に設けられた第１導電型の領域と、半導体基板の表面上
部あるいは表面部に設けられ、第２導電型の領域と、第
１導電型の領域及び第２導電型の領域の上部に設けられ
、かつ半導体基板よりも大きなバンドギャップエネルギ
を有する第１導電型の半導体領域とを具備する半導体装
置において、第２導電型の領域の一部のみが第１導電型
の領域と整流性接合を形成し、他の第２導電型の領域は
半導体基板の表面上部あるいは表面部に設けられている
ことを特徴とする半導体装置であり、この構造の特徴は
、絶縁性あるいは半絶縁性の半導体基板の表面にコレク
タ領域を設け、ベース領域はこのコレクタ領域と一部分
でのみ接合を形成し、他のベース領域すなわち外部ベー
ス領域のほとんどが半導体基板上に設けられていること
である。The present invention includes a first conductivity type region provided on the surface of an insulating or semi-insulating semiconductor substrate, a second conductivity type region provided on the top or surface of the semiconductor substrate, and a first conductivity type region provided on the top or surface of the semiconductor substrate. In a semiconductor device comprising a mold region and a first conductivity type semiconductor region provided above the second conductivity type region and having a larger bandgap energy than the semiconductor substrate, one of the second conductivity type regions is provided. This is a semiconductor device characterized in that only a portion of the semiconductor substrate forms a rectifying junction with a region of the first conductivity type, and the other region of the second conductivity type is provided on the upper surface or the surface portion of the semiconductor substrate. The feature of the structure is that a collector region is provided on the surface of an insulating or semi-insulating semiconductor substrate, the base region forms a junction with this collector region only in a part, and most of the other base region, that is, the external base region, is connected to the semiconductor substrate. It is provided above.
次に本発明の半導体装置の一実施例を第２図により説明
する。Next, an embodiment of the semiconductor device of the present invention will be described with reference to FIG.
即ち絶縁性ＧａＡｓ基板（１１）の表面部にはコレクタ
領域（１４）としてのＮ型ＧａＡｓ領域が形成されてい
る。That is, an N-type GaAs region as a collector region (14) is formed on the surface of the insulating GaAs substrate (11).
このコレクタ領域（１４）は例えばキャリア濃度が１０
１６ｃｍ−３厚みが０．５μｍである。コレクタ領域（
１４）の表面上部から絶縁性ＧａＡｓ基板（１１）の表
面上部にかけてはベース領域（１５）としてのＰ型Ｇａ
Ａｓ層が形成されている。このベース領域（１５）は例
えばキャリア濃度が４×１０１８ｃｍ−３、厚みが０．
２μｍである。This collector region (14) has a carrier concentration of, for example, 10
16 cm-3 thickness is 0.5 μm. Collector area (
14) to the upper surface of the insulating GaAs substrate (11) is a P-type Ga base region (15).
An As layer is formed. This base region (15) has, for example, a carrier concentration of 4 x 1018 cm-3 and a thickness of 0.
It is 2 μm.
このベース領域（１５）は後述するエミッタ領域（１６
）付近では絶縁性ＧａＡｓ基板（１１）上に設けられて
いるコレクタ領域（１４）と接合するがその他のベース
領域（１５）は絶縁性ＧａＡｓ基板（１１）上に設けら
れている。このコレクタ領域（１４）ベース領域（１５
）を介してエミッタ領域（１６）としてのＮ型ＡｌＧａ
Ａｓ層が設けられており、このエミッタ領域（１６）は
キャリア濃度が５×１０１６ｃｍ−３、厚みが０．５μ
ｍである。このエミッタ領域（１６）上には０．２μｍ
厚のＮ型ＧａＡｓ層からなるキャップ層（１７）が設け
られ、ＨＢＴとしての半導体装置が完成される。This base region (15) is an emitter region (16) which will be described later.
) is connected to the collector region (14) provided on the insulating GaAs substrate (11), but the other base region (15) is provided on the insulating GaAs substrate (11). This collector area (14) and base area (15
) via N-type AlGa as emitter region (16)
An As layer is provided, and this emitter region (16) has a carrier concentration of 5 x 1016 cm-3 and a thickness of 0.5 μ.
It is m. 0.2 μm on this emitter region (16)
A cap layer (17) made of a thick N-type GaAs layer is provided, and a semiconductor device as an HBT is completed.
次に第３図により本実施例の製造工程を説明し、本実施
例の構成と効果を明らかにする。Next, the manufacturing process of this embodiment will be explained with reference to FIG. 3, and the structure and effects of this embodiment will be clarified.
先ず第３図（ａ）に示すようにアンドープ絶縁性ＧａＡ
ｓ基板（１１）上にＳｉＯ２膜（１２）をＣＶＤ法によ
り被着したのち、通常の光蝕刻技術を用いてフォトレジ
ストパターン（１３）を形成し、Ｓｉ＋をイオン注入す
る。First, as shown in FIG. 3(a), undoped insulating GaA
After a SiO2 film (12) is deposited on the s-substrate (11) by CVD, a photoresist pattern (13) is formed using ordinary photoetching technology, and Si+ ions are implanted.
この注入条件はＧａＡｓ基板（１１）表面近くにピーク
濃度がくるようにする。The implantation conditions are such that the peak concentration is near the surface of the GaAs substrate (11).
引き続いてフォトレジスト（１３）をマスクにしてＳｉ
Ｏ２膜（１２）をエッチングした後、再びＳｉ＋をイオ
ン注入して基板表面部（深さ０．５μｍ）にＳｉ＋イオ
ン注入層を形成する。ついで第３図（ｂ）に示すように
フォトレジスト（１３）、ＳｉＯ２膜（１２）をすべて
除去し、８００℃のＡｓＨ３Ｈ２雰囲気でアニールする
ことにより、キャリア濃度〜１０１６ｃｍ−３、深さ〜
０．５μｍのコレクタ領域（１４）としてのＮ型ＧａＡ
ｓ領域が形成される。Subsequently, using the photoresist (13) as a mask, Si
After etching the O2 film (12), Si+ ions are again implanted to form a Si+ ion-implanted layer on the surface of the substrate (depth 0.5 μm). Next, as shown in FIG. 3(b), the photoresist (13) and the SiO2 film (12) are all removed and annealed in an AsH3H2 atmosphere at 800°C, resulting in a carrier concentration of ~1016 cm-3 and a depth of ~
N-type GaA as collector region (14) of 0.5 μm
An s region is formed.
次に第３図（ｃ）に示すようにキャリア濃度４×１０１
８ｃｍ−３のベース領域用としてのＰ型ＧａＡｓ層（１
５１）を例えばＢｅをドーパントとし、分子線エピタキ
シ法（ＭＢＥ法）により厚さ０．２μｍ程、形成し、更
にＳｉをドーパントとしてキャリア濃度５×１０１６ｃ
ｍ−３のエミッタ領域用としてのＮ型ＡｌＧａＡｓ層（
１６１）を同じくＭＢＥ法により、厚さ０．５μｍ形成
する。またキャップ層用としてのＮ型ＧａＡｓ層（１７
１）をＳｉをドーパントとして０．２μｍ形成する。Next, as shown in FIG. 3(c), the carrier concentration is 4×101
P-type GaAs layer (1
51) is formed to a thickness of about 0.2 μm using, for example, Be as a dopant by molecular beam epitaxy (MBE method), and then Si is used as a dopant to form a carrier concentration of 5×10 16 c.
N-type AlGaAs layer for emitter region of m-3 (
161) is also formed to a thickness of 0.5 μm by the MBE method. In addition, an N-type GaAs layer (17
1) is formed to a thickness of 0.2 μm using Si as a dopant.
次に通常の光蝕刻法を用いて第３図（ｄ）に示すように
ＡｌＧａＡｓ層（１６１）及びＮ型ＧａＡｓ層（１７１
）をそれぞれエミッタ領域（１６）、キャップ層（１７
）を残してエッチング除去する。Next, using a normal photoetching method, an AlGaAs layer (161) and an N-type GaAs layer (171) are formed as shown in FIG. 3(d).
) are respectively emitter region (16) and cap layer (17).
) is removed by etching.
更に通常の光蝕刻法を用いて第３図（ｅ）に示すように
Ｐ型ＧａＡｓ層（１５１）をベース領域（１５）を残し
てエッチング除去し、本実施例のＨＢＴが得られる。Furthermore, the P-type GaAs layer (151) is etched away using a conventional photoetching method, leaving the base region (15), as shown in FIG. 3(e), to obtain the HBT of this example.
勿論キャップ層（１７）上、ベース領域（１５）上、コ
レクタ領域（１４）上にはＡｕＧｅ系のオーミック電極
などが形成される。Of course, AuGe-based ohmic electrodes and the like are formed on the cap layer (17), the base region (15), and the collector region (14).
以上の工程及び構造からわかるように本実施例のＨＢＴ
においては、ベース・コレクタ接合はエミッタのある領
域のごく近傍のみにあり、いわゆる外部ベース例えば電
極をとるためのベース領域（１５）は絶縁性ＧａＡｓ基
板（１１）上にあるためコレクタ容量は極めて小さくな
っている。従って従来大きなコレクタ容量のために制限
されていたスイッチングスピード、即ち、ＨＢＴの高速
性は本実施例によって大きく改善できる。また、集積回
路を構成するに当っては本実施例は絶縁性基板を用いて
いるため素子分離が容易という特徴も有している。As can be seen from the above steps and structure, the HBT of this example
In this case, the base-collector junction is only in the vicinity of the emitter region, and the so-called external base, for example, the base region (15) for taking the electrode, is on the insulating GaAs substrate (11), so the collector capacitance is extremely small. It has become. Therefore, the switching speed, that is, the high speed performance of the HBT, which was conventionally limited due to the large collector capacitance, can be greatly improved by this embodiment. Further, in constructing an integrated circuit, this embodiment uses an insulating substrate, so it has the feature that element isolation is easy.
なお前述した実施例ではベース領域をＭＢＥ法により形
成したが、これに限定されるものではなく、インプラな
どの手段により基板表面部にコレクタ領域形成と同様に
形成してもよい。Although the base region was formed by the MBE method in the above-described embodiment, the base region is not limited to this, and may be formed on the surface of the substrate by means such as implantation in the same manner as the collector region is formed.
更に第４図に示すようにベース領域（１５）（１８）を
イオン注入とＭＢＥの併用により形成すれば更にベース
抵抗の低いＨＢＴを実現でき、よりスイッチングスピー
ドを改善できる。Furthermore, as shown in FIG. 4, if the base regions (15) and (18) are formed by a combination of ion implantation and MBE, an HBT with even lower base resistance can be realized and the switching speed can be further improved.
上述のように本発明の半導体装置としてのＨＢＴは、ベ
ースコレクタ間の接合容量が小さい、スイッチングスピ
ードが早い効果がある。As described above, the HBT as a semiconductor device of the present invention has the advantage of having a small base-collector junction capacitance and a fast switching speed.
第１図は従来の半導体装置の一例を示す説明用断面図、
第２図は本発明の半導体装置の一実施例を示す説明用断
面図、第３図は本発明の半導体装置の一実施例の製造工
程を順に示す説明用断面図、第４図は本発明の半導体装
置の他の実施例を示す説明用断面図である。
１、１１・・・絶縁性ＧａＡｓ基板
４、１４・・・コレクタ領域 ５、１５、１８・・・ベ
ース領域６、１６・・・エミッタ領域 ７、１７・・・
キャップ層代理人 弁理士 井 上 一 男
第 Ｉ Ｖ
（ｄ）
（Ｃ）
（ｅ）
第２図
（ｂ）
ム
ｔｄ）
７
特許１長は若杉和夫殿
■、ル件の表示
昭和５８年峙許顛ｉ１！ １１５１２４号２、発明の名
称
半導体装置
：３、補正音する箭
事件との関係 ｌ寺ａ′：「出＋ｒＫｉ人（３０７）東
京芝浦電気株式会社
４、代理人
〒１４４
東京都太田区Ｍ１７田４丁目４１番１１号第−小野田ビ
ル
弁上特許事務所内
゛電話 ７３６−３５５８
（，３２５７）弁理士弁上−男
補正命令の日付
昭和５８年９月７日（発送日 １ｉＦ３Ｌ０５８年９月
２７日）６、補正の対象
図 面
７、補正の内容
原図１ＴＩを添付図面のように訂正する。
以上
第 １ 図
〆 ウ
＜ り
（り）
（Ｃン
Ｃｅ）
富２図
＋−ニーＪｌ
ｒｂ）
ム
（ｄ、）
７
、；Ｉ ダ １゛乙
３FIG. 1 is an explanatory cross-sectional view showing an example of a conventional semiconductor device;
FIG. 2 is an explanatory cross-sectional view showing one embodiment of the semiconductor device of the present invention, FIG. 3 is an explanatory cross-sectional view sequentially showing the manufacturing process of one embodiment of the semiconductor device of the present invention, and FIG. FIG. 3 is an explanatory cross-sectional view showing another embodiment of the semiconductor device of FIG. 1, 11... Insulating GaAs substrate 4, 14... Collector region 5, 15, 18... Base region 6, 16... Emitter region 7, 17...
Cap layer agent Patent attorney Kazuo Inoue IV (d) (C) (e) Figure 2 (b) Mtd) 7 The first patent owner is Mr. Kazuo Wakasugi, and the patent was issued in 1988. Part i1! 115124 No. 2, Name of the invention Semiconductor device: 3, Relationship with the correction sound case No. 41-11 - Onoda Building Benjo Patent Office Telephone: 736-3558 (,3257) Patent Attorney Benjo - Date of amendment order: September 7, 1982 (Delivery date: September 27, 1982) 6. Drawings subject to correction 7. Contents of correction Original drawing 1TI is corrected as shown in the attached drawing. d,) 7,;I da 1゛Otsu3
Claims (1)
に設けられた第１導電型の領域と、前記半導体基板の表
面上部あるいは表面部に設けられた第２導電型の領域と
、前記第１導電型の領域及び前記第２導電型の領域の上
部に設けられ、かつ前記半導体基板よりも大きなバンド
ギャップエネルギを有する第１導電型の半導体領域とを
具備する半導体装置において、前記第２導電型の領域の
一部のみが前記第１導電型の領域と整流性接合を形成し
、他の第２導電型の領域は前記半導体基板の表面上部あ
るいは表面部に設けられていることを特徴とする半導体
装置。a first conductivity type region selectively provided on the surface of an insulating or semi-insulating semiconductor substrate; a second conductivity type region provided on the top or surface of the semiconductor substrate; A semiconductor device comprising a first conductivity type region and a first conductivity type semiconductor region provided above the second conductivity type region and having a larger bandgap energy than the semiconductor substrate. Only a part of the region of the mold forms a rectifying junction with the region of the first conductivity type, and the other region of the second conductivity type is provided on the upper surface or the surface portion of the semiconductor substrate. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11512483A JPS607771A (en) | 1983-06-28 | 1983-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11512483A JPS607771A (en) | 1983-06-28 | 1983-06-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS607771A true JPS607771A (en) | 1985-01-16 |
Family
ID=14654854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11512483A Pending JPS607771A (en) | 1983-06-28 | 1983-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS607771A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268061A (en) * | 1985-05-23 | 1986-11-27 | Agency Of Ind Science & Technol | Hot-electron-transistor and manufacture thereof |
| JPS6249658A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249656A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249657A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249660A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6281759A (en) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | Structure of heterojunction type bipolar transistor |
| JPS62295459A (en) * | 1986-06-16 | 1987-12-22 | Hitachi Ltd | Semiconductor device |
| JPS63318778A (en) * | 1987-06-22 | 1988-12-27 | Nec Corp | Heterojunction bipolar transistor and manufacture |
| US5147775A (en) * | 1987-07-24 | 1992-09-15 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a high-frequency bipolar transistor |
| US5252841A (en) * | 1991-05-09 | 1993-10-12 | Hughes Aircraft Company | Heterojunction bipolar transistor structure having low base-collector capacitance, and method of fabricating the same |
-
1983
- 1983-06-28 JP JP11512483A patent/JPS607771A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61268061A (en) * | 1985-05-23 | 1986-11-27 | Agency Of Ind Science & Technol | Hot-electron-transistor and manufacture thereof |
| JPH0422341B2 (en) * | 1985-05-23 | 1992-04-16 | Kogyo Gijutsuin | |
| JPS6249658A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249656A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249657A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6249660A (en) * | 1985-08-29 | 1987-03-04 | Matsushita Electric Ind Co Ltd | Heterojunction bipolar transistor and manufacture thereof |
| JPS6281759A (en) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | Structure of heterojunction type bipolar transistor |
| JPS62295459A (en) * | 1986-06-16 | 1987-12-22 | Hitachi Ltd | Semiconductor device |
| JPS63318778A (en) * | 1987-06-22 | 1988-12-27 | Nec Corp | Heterojunction bipolar transistor and manufacture |
| US5147775A (en) * | 1987-07-24 | 1992-09-15 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a high-frequency bipolar transistor |
| US5252841A (en) * | 1991-05-09 | 1993-10-12 | Hughes Aircraft Company | Heterojunction bipolar transistor structure having low base-collector capacitance, and method of fabricating the same |
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