JPS6074682A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6074682A JPS6074682A JP18271583A JP18271583A JPS6074682A JP S6074682 A JPS6074682 A JP S6074682A JP 18271583 A JP18271583 A JP 18271583A JP 18271583 A JP18271583 A JP 18271583A JP S6074682 A JPS6074682 A JP S6074682A
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- semiconductor
- semiconductor device
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 229910000714 At alloy Inorganic materials 0.000 claims 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に電極形成工
程を改良した半導体装置の製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which an electrode forming process is improved.
従来、ＭＯ８型半導体装置は次のような方法により製造
されている。Conventionally, MO8 type semiconductor devices have been manufactured by the following method.
まず、側えばｐ型シリコン基板１の素子分離領域予定部
を選択的に除去し、この除去部にＳ ｔ ０２等の絶縁
物を埋め込んで素子分離領域２を形成する。つづいて、
素子分離領域２で分離された基板１の島状領域に熱酸化
膜を形成し、該熱酸化膜上に多結晶シリコンからなるｒ
−計電極３を形成した後、該電極３をマスクとして熱酸
化膜を選択的にエツチングしてダート酸化膜４を形成す
る。ひきつづき、ダート電極３及び素子分離領域２をマ
スクとしてｎ型不純物、例えば砒素を基板１にドーピン
グしてｎ型のソース、ドレイン領域５，６を形成する。First, a portion of the p-type silicon substrate 1 where the element isolation region is to be formed is selectively removed, and an insulator such as S t 02 is buried in the removed portion to form the element isolation region 2 . Continuing,
A thermal oxide film is formed on the island-like region of the substrate 1 separated by the element isolation region 2, and a layer made of polycrystalline silicon is formed on the thermal oxide film.
- After forming the meter electrode 3, the thermal oxide film is selectively etched using the electrode 3 as a mask to form a dirt oxide film 4. Subsequently, using the dirt electrode 3 and the element isolation region 2 as a mask, the substrate 1 is doped with an n-type impurity, such as arsenic, to form n-type source and drain regions 5 and 6.
次いで、全面に５１０２膜７を堆積し、コンタクトホー
ル８・・・を開孔した後、全面にＡｔ膜を蒸着し、ｉ４
ターニングして前記ソース、ドレイン領域５，６とコン
タクトホール８，８を介して接続したＡｔ取出し電極９
，１０を形成し、ＭＯ８型半導体装置を製造する（第１
図図示）。こうした方法によれば、ｆ−）電極３とソー
ス、ドレイン領域５，６との合せ余裕が不粟となるため
、高集積化が可能となる。Next, after depositing a 5102 film 7 on the entire surface and opening contact holes 8..., an At film is deposited on the entire surface, and an i4
At extraction electrodes 9 are turned and connected to the source and drain regions 5 and 6 through contact holes 8 and 8.
, 10 to manufacture an MO8 type semiconductor device (first
(Illustrated) According to this method, the alignment margin between the f-) electrode 3 and the source and drain regions 5 and 6 is reduced, so that high integration is possible.
しかしながら、上述した従来法にあってはソース、ドレ
イン領域５，６とＡｔ取出し電極９゜１０との接続を図
るためのコンタクトホールの形成に際し、マスク合せが
必要となり、十分な合せ余裕が必要となる。このため、
素子の微細化が進行すると、合せ余裕が十分にとれなく
なるので、コンタクトホールがソース領域とダート電極
とに亘って形成されたりしてソース、ダート間短絡を招
く。したがって、フォトエツチング技術を使用してのソ
ース、ドレインのＡｔ取出し電極の形成が困難となる。However, in the conventional method described above, mask alignment is required when forming contact holes for connecting the source and drain regions 5 and 6 to the At extraction electrodes 9 and 10, and sufficient alignment margin is required. Become. For this reason,
As device miniaturization progresses, sufficient alignment margins are no longer available, and a contact hole may be formed across the source region and the dirt electrode, resulting in a short circuit between the source and the dirt. Therefore, it becomes difficult to form At extraction electrodes for the source and drain using photoetching technology.
本発明はセルファラインでダート電極と、ソース、ドレ
イン電極を形成することにより、サラミクロンの電極形
成が可能な高集積度の半導体装置を製造し得る方法を提
供しようとするものである。The present invention aims to provide a method for manufacturing a highly integrated semiconductor device capable of forming Saramicron electrodes by forming dirt electrodes, source and drain electrodes using Selfa lines.
本発明は第１導電型の半導体基板もしくは半導体層に素
子分離領域を形成する工程と、この素子分離領域で分離
された半導体基板もしくは半導体層の島状領域にダート
絶縁膜を介して両端が素子分離領域上に延びる被膜ノ９
ターンを選択的に形成する工程と、この被膜・奢ターン
の側面のみに該パターンに対して選択エツチング性を有
する壁体を形成した後、該ｉ９ターン及び壁体をマスク
として第２導電型の不純物を半導体基板もしくは半導体
層にドーピングして第２導電型の半導体領域を形成する
工程と、前記被膜・母ターン及び露出した半導体領域の
一部をエツチング除去して半導体基板もしくは半導体層
に溝部を形成すると共に、前記壁体を残存させる工程と
、全面に金属膜もしくは金属シリサイド５−
膜を堆積した後、残存壁体を除去してその上の金属又は
金属シリサイドをリフトオフすることにより電極を形成
する工程とを具備したことを特徴とするものである。こ
うした本発明によれば、ダート電極と上面に溝部が作ら
れたソース、ドレイン領域とをセルファラインで形成で
きると共に、ｆ−計電極とソース、ドレイン電極とをセ
ルファラインで形成でき、高集積度の半導体装置を簡単
に製造できる。The present invention includes a step of forming an element isolation region in a semiconductor substrate or a semiconductor layer of a first conductivity type, and an island-like region of the semiconductor substrate or semiconductor layer separated by the element isolation region, with a dirt insulating film interposed between both ends of the element. Coating 9 extending over the separation area
After the step of selectively forming turns and forming a wall having selective etching properties with respect to the pattern only on the side surface of this film/detailed turn, a second conductivity type is etched using the i9 turn and wall as a mask. A step of doping the semiconductor substrate or semiconductor layer with an impurity to form a second conductivity type semiconductor region, and etching away the film/mother turn and a part of the exposed semiconductor region to form a groove in the semiconductor substrate or semiconductor layer. At the same time, a step of leaving the wall remains, and after depositing a metal film or metal silicide film on the entire surface, removing the remaining wall and lifting off the metal or metal silicide thereon, forming an electrode. The method is characterized by comprising a step of: According to the present invention, the dirt electrode and the source and drain regions with grooves formed on the upper surface can be formed using the Selfa line, and the f-meter electrode and the source and drain electrodes can be formed using the Selfa line, allowing for high integration. semiconductor devices can be easily manufactured.
次に、本発明をｎチャンネルＭＯ８）ランジスタの製造
に適用した側について第２図（、）〜（ｅ）を参照して
説明する。Next, the application of the present invention to the manufacture of an n-channel MO8) transistor will be explained with reference to FIGS. 2(a) to 2(e).
■ まず、ｐ型シリコン基板１ノの素子分離領域予定部
を選択的にエツチング除去した後、除去部に５ｔＯ２を
埋め込んで素子分離領域１２を形成した。つづいて、熱
酸化処理を施して素子分離領域１２で分離された基板１
１の島状領域に熱酸化膜を成長させた後、全面に多結晶
シリコン膜を堆積した。ひきつづき、多結晶シリコ６−
ン膜をダート予定部に写真蝕刻法によりレジストパター
ン（図示せず）を形成した後、該レジストパターンをマ
スクとして多結晶シリコン膜及び熱酸化膜をリアクティ
ブイオンエツチング（ＲＩＥ ）によシ選択的に除去し
て前記島状領域にダート酸化膜１３を介して両端が前記
素子分離領域１２上に延びる多結晶シリコンパターン１
４を形成した。この後レジスト・！ターンを除去し、更
に全面にＣＶＤ法により厚さａｏｏｏｌの８１０□膜１
５を堆積した（第２図（＆）図示）。(2) First, a portion of the p-type silicon substrate 1 where an element isolation region was to be formed was selectively removed by etching, and then 5tO2 was filled in the removed portion to form an element isolation region 12. Next, the substrate 1 is separated by the element isolation region 12 by thermal oxidation treatment.
After growing a thermal oxide film on the island-like region 1, a polycrystalline silicon film was deposited on the entire surface. Subsequently, a resist pattern (not shown) is formed in the area where the polycrystalline silicon film is to be darted by photolithography, and then the polycrystalline silicon film and the thermal oxide film are subjected to reactive ion etching (reactive ion etching) using the resist pattern as a mask. A polycrystalline silicon pattern 1 is selectively removed by RIE) to form a polycrystalline silicon pattern 1 in the island region with both ends extending above the element isolation region 12 via a dirt oxide film 13.
4 was formed. After this, resist! After removing the turns, an 810□ film 1 with a thickness of aooool is formed on the entire surface by CVD method.
5 was deposited (as shown in FIG. 2).
（１１）次いで、ＲＩＥにより５１０２膜１５をエツチ
ングして多結晶シリコンミ９ターン１４及びダート酸化
膜１３の側面のみに５１０２からなる壁体１６を形成し
た。つづいて、素子分離領域１２、多結晶クリコンパタ
ーン１４及び壁体１６をマスクとしてｎ型不純物、例え
ば砒素を基板１１の露出した島状領域にイオン注入した
後、熱処理を施してｎ型の拡散領域１７．ＩＩＩを形成
した（第２図（ｂ）図示）。(11) Next, the 5102 film 15 was etched by RIE to form a wall 16 made of 5102 only on the side surfaces of the polycrystalline silicon mi9 turns 14 and the dirt oxide film 13. Next, using the element isolation region 12, the polycrystalline crystal pattern 14, and the wall 16 as masks, an n-type impurity, such as arsenic, is ion-implanted into the exposed island region of the substrate 11, and then heat treatment is performed to form an n-type diffusion region. 17. III was formed (as shown in FIG. 2(b)).
（ｉｉｉ ）次いで、ＲＩＥにより多結晶シリコンパタ
ーン１４がなくなるまでエツチングした。この時、露出
したｎ型拡散領域１７．１８の表面がエツチングされて
溝部１９１，１９２が形成されると共に、残存したｎ型
拡散領域によりソース、ドレイン領域２０．２１が形成
された。同時に塀状に突出した壁体１６が残存した（第
２図（ｃ）図示）。(iii) Next, etching was performed by RIE until the polycrystalline silicon pattern 14 disappeared. At this time, the surfaces of the exposed n-type diffusion regions 17 and 18 were etched to form grooves 191 and 192, and the remaining n-type diffusion regions formed source and drain regions 20 and 21. At the same time, a wall 16 projecting like a wall remained (as shown in FIG. 2(c)).
（ｉＶ） 次いで、全面にＡｔ膜を蒸着した。この時、
第２図（ｄ）に示す如く、Ａｔ膜２２は突出した壁体１
６上にも蒸着され、該壁体１６を境に溝部１９、．１９
２上のＡｔ膜２２とダート酸化膜１３上のｋｌ膜２２と
が分離された。つづいて、壁体１６を除去してその壁体
１６，１６上のＡ／−膜をリフトオフすることにより、
壁体１６゜１６を境にしてＡｔ膜を分離した後、分離さ
れたＡ／＝膜をノＪ？ターニングしてダート酸化膜１３
上を横切るＡ／１．ダート電極２３．ソース領域２０と
接続したソース取出しＡｔ電極２４及びドレイン領域２
１と接続したドレイン取出しＡｔ電極２５を形成した。(iv) Next, an At film was deposited on the entire surface. At this time,
As shown in FIG. 2(d), the At film 22 is attached to the protruding wall 1.
6, and grooves 19, . 19
The At film 22 on the dirt oxide film 13 and the KL film 22 on the dirt oxide film 13 were separated. Subsequently, by removing the wall 16 and lifting off the A/- film on the wall 16, 16,
After separating the At film along the wall 16°16, the separated A/=film is Turning and dirt oxide film 13
A/1 across the top. Dart electrode 23. Source extraction At electrode 24 and drain region 2 connected to source region 20
A drain lead-out At electrode 25 connected to 1 was formed.
この後、全面にＳｉ３Ｎ４から々るパッシベーション膜
２６を堆積してｎチャンネルＭＯ８）ランジスタを形成
した（第２図（、）図示）。Thereafter, a passivation film 26 made of Si3N4 was deposited on the entire surface to form an n-channel MO8 transistor (as shown in FIG. 2(a)).
しかして、本発明によればダート電極予定部に位置する
多結晶シリコン・ぐターン１４及び壁体１６をマスクと
して砒素のイオン注入を行なうことにより、その後に多
結晶シリコンパターン１４を含む領域にｒ−）電極２３
を形成した場合、該ダート電極２３とｎ型のソース、ド
レイン領域２０．２１とをセルファラインで形成できる
。また、ダート電極予定部の両側に残存させた壁体１６
．１６をリフトオフ材として利用してＡｔ膜２２を分離
するため、ソース、ドレインの取出しＡｔ電極２４．２
５とＡｔダート電極２３とをセルファラインで形成でき
る。この場合、Ａｔダート電極２３と取出しＡｔ電極２
４゜２５の間の距離を壁体ｉｅ、ｉｅの幅でコントロー
ルできるため、Ａｔゲート電極２３とソースドレインの
コンタクトホールの距離を数千久と短縮できる。したが
って、高集積度のｎチャンネルＭＯ８）ランジスタを製
造できる。According to the present invention, by implanting arsenic ions using the polycrystalline silicon pattern 14 and wall body 16 located in the planned dirt electrode portion as a mask, the region including the polycrystalline silicon pattern 14 is then irradiated. -) Electrode 23
In this case, the dirt electrode 23 and the n-type source and drain regions 20.21 can be formed by self-alignment. In addition, the wall bodies 16 left on both sides of the planned dirt electrode part
．． 16 as a lift-off material to separate the At film 22, the source and drain At electrodes 24.2
5 and the At dirt electrode 23 can be formed by self-alignment. In this case, the At dirt electrode 23 and the extraction At electrode 2
Since the distance between 4.degree. Therefore, a highly integrated n-channel MO8) transistor can be manufactured.
９−
また、第２図（ｂ） 、 （ｅ）に示す如く多結晶シリ
コンノ’？ターン１４、壁体１６．１６をマスクとして
シリコン基板１１にｎ型拡散領域１７，１Ｂを形成した
後、その拡散領域１７．１８ｆ表面をエツチングして上
面に溝部１９１．１９２を有するソース、ドレイン領域
２０．２１を形成するため、Ａｔ取出し電極２４．２５
とソース、ドレイン領域２０．２１との接触面積を大き
くでき、ひいてはソース、ドレイン領域を微細化して高
集積化を図る場合でも、良好な接続が可能となる。9- Also, as shown in FIGS. 2(b) and (e), polycrystalline silicon? After forming n-type diffusion regions 17 and 1B in the silicon substrate 11 using the turn 14 and the walls 16 and 16 as masks, the surfaces of the diffusion regions 17 and 18f are etched to form source and drain regions having grooves 191 and 192 on the upper surface. 20.21, At extraction electrodes 24.25
The contact area between the source and drain regions 20 and 21 can be increased, and even when the source and drain regions are miniaturized to achieve high integration, good connection is possible.
なお、上記実施例において素子分離領域の形成前に該領
域に対応する箇所に基板と同導電型の不純物をドーピン
グして反転防止層を形成してもよい。Note that in the above embodiment, before forming the element isolation region, an inversion prevention layer may be formed by doping an impurity of the same conductivity type as the substrate at a location corresponding to the region.
上記実施例ではダート電極予定部に多結晶シリコン・ン
ターンを形成したが、これに代って非晶質シリコンパタ
ーン等壁体に対して選択エツチング性を有する材料のパ
ターンならいかなるものを用いてもよい。In the above embodiment, a polycrystalline silicon pattern was formed in the dirt electrode planned portion, but any pattern made of a material that has selective etching properties with respect to the wall body, such as an amorphous silicon pattern, may be used instead. good.
１０−
上記実施例では電極としてＡｔを用いたが、これに代っ
てＡｔ −Ｓｔ 、 Ａｔ−Ｃｕ 、 Ａｔ−８１−Ｃ
ｕなどのＡ／＝合金やＴｉ ｌＷ ｒ Ｍｏ ＋ Ｔａ
などの高融点金属、モリブデンシリサイド、タングステ
ンシリサイド、タンタルシリサイドなどの高融点金属シ
リサイドを用いてもよい。10- In the above examples, At was used as the electrode, but instead of At-St, At-Cu, At-81-C
A/= alloy such as u or TiW r Mo + Ta
High melting point metals such as molybdenum silicide, tungsten silicide, tantalum silicide, and other high melting point metal silicides may also be used.
本発明は上記実施例の如きｎ−チャンネルＭＯ８）ラン
ジスタの製造のみに限らず、ｐチャンネルＭＯ８）ラン
ジスタ、０ＭＯ８等の製造にも同様に適用できる。また
、ノマルクシリコン上にＭＯＳ ）ランジスタを製造す
る場合に限らず、ＳＯ８等の半導体膜上にＭＯＳ ）ラ
ンジスタを製造してもよい。The present invention is applicable not only to the manufacture of n-channel MO8) transistors as in the above embodiments, but also to the manufacture of p-channel MO8) transistors, 0MO8 transistors, etc. Furthermore, the present invention is not limited to manufacturing a MOS transistor on normal silicon, but may also be manufactured on a semiconductor film such as SO8.
以上詳述した如く、本発明はダート電極とソース、ドレ
イン領域とをセルファラインで形成できると共に、ダー
ト電極とソース、ドレイン電極をセルファラインで形成
できることによシサブミクロンの電極形成が可能な高集
積度の半導体装置を製造し得る方法を提供できる。As described in detail above, the present invention has a high degree of integration that allows formation of submicron electrodes by forming dirt electrodes and source and drain regions using self-aligned lines, and by forming dirt electrodes and source and drain electrodes using self-aligned lines. A method for manufacturing a semiconductor device can be provided.
第１図は従来法により製造されたｎチャンネルＭＯ８）
ランジスタの断面図、第２図（、）〜（、）は本発明の
実施例におけるｎチャンネルＭＯ８）ランジスタの製造
工程を示す断面図である。
１１・・・ｐ型シリコン基板、１２・・・素子分離領域
、１３・・・ダート酸化膜、１４・・・多結晶シリコン
パターン、１６・・・壁体、１７．１８・・・ｎ型拡散
領域、１９１．１９．・・・溝部、２０・・・ｎ＋型ソ
ースｉ域、２１・・・層型ドレイン領域、２３・・・Ａ
ｔダート電極、２４．２５・・・取出しＡｔ電極。Figure 1 shows an n-channel MO8 manufactured by the conventional method)
Cross-sectional views of transistors FIGS. 2(,) to (,) are cross-sectional views showing the manufacturing process of an n-channel MO8) transistor in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Element isolation region, 13... Dirt oxide film, 14... Polycrystalline silicon pattern, 16... Wall body, 17.18... N-type diffusion Area, 191.19. ...Groove portion, 20...N+ type source i region, 21...Layered drain region, 23...A
t dirt electrode, 24.25... take-out At electrode.
Claims (5)
分離領域を形成する工程と、この素子分離領域で分離さ
れた半導体基板もしくは半導体層の島状領域にダート絶
縁膜を介して両端が素子分離領域上に延びる被膜パター
ンを選択的に形成する工程と、この被膜ノ４ターンの側
面のみに該ノｆターンに対して選択エツチング性を有す
る壁体を形成した後、該パターン及び壁体をマスクとし
て第２導電型の不純物を半導体基板もしくは半導体層に
ドーピングして第２導電の半導体領域を形成する工程と
、前記被膜パターン及び露出した半導体領域の一部をエ
ツチング除去して半導体基板もしくは半導体層に溝部を
形成すると共に、前記壁体を残存させる工程と、全面に
金属膜又は金属シリサイド膜を堆積した後、残存壁体を
除去してその上の金属又は金属シリサイドをリフトオン
することにより電極の形成を行なう工程とを具備したこ
とを特徴とする半導体装置の製造方法。(1) A step of forming an element isolation region in a semiconductor substrate or a semiconductor layer of a first conductivity type, and an island-shaped region of the semiconductor substrate or semiconductor layer separated by this element isolation region is connected to an element at both ends via a dirt insulating film. After selectively forming a film pattern extending over the separation region and forming a wall body having selective etching properties with respect to the f-turns only on the side faces of the fourth turn of the film, the pattern and the wall body are A step of doping a semiconductor substrate or a semiconductor layer with a second conductivity type impurity as a mask to form a second conductivity semiconductor region, and etching away a portion of the film pattern and the exposed semiconductor region to form a semiconductor substrate or semiconductor layer. The electrode is formed by forming a groove in the layer and leaving the wall, and after depositing a metal film or metal silicide film on the entire surface, removing the remaining wall and lifting the metal or metal silicide thereon. 1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device.
ターンであることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the non-monocrystalline silicon pattern is a polycrystalline silicon pattern.
なることを特徴とする特許請求の範囲第１項記載の半導
体装置の製造方法。(3) Wall strength The method for manufacturing a semiconductor device according to claim 1, characterized in that it is made of CvD-8iO2, Si, or N4.
項記載の半導体装置の製造方法。(4) The metal film is a Ti film, Mo film, W film, or Ta film. Claim 1 characterized in that it is an At alloy film.
A method for manufacturing a semiconductor device according to section 1.
タンタルシリサイド膜であることを特徴とする特許請求
の範囲第１項記載の半導体装置の製造方法。(5) The metal silicide film is a titanium silicide film. Molybdenum silicide film, tungsten silicide film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a tantalum silicide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18271583A JPS6074682A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18271583A JPS6074682A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6074682A true JPS6074682A (en) | 1985-04-26 |
| JPH056345B2 JPH056345B2 (en) | 1993-01-26 |
Family
ID=16123166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18271583A Granted JPS6074682A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074682A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61292678A (en) * | 1985-06-21 | 1986-12-23 | 株式会社日立製作所 | Display controller |
| US5051805A (en) * | 1987-07-15 | 1991-09-24 | Rockwell International Corporation | Sub-micron bipolar devices with sub-micron contacts |
| JPH04278385A (en) * | 1991-03-07 | 1992-10-02 | Oji Paper Co Ltd | Thermal recording material |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5379378A (en) * | 1976-12-23 | 1978-07-13 | Matsushita Electric Ind Co Ltd | Semoconductor davice and its production |
| JPS58130569A (en) * | 1982-01-28 | 1983-08-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58158972A (en) * | 1982-03-16 | 1983-09-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58162064A (en) * | 1982-03-23 | 1983-09-26 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
-
1983
- 1983-09-30 JP JP18271583A patent/JPS6074682A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5379378A (en) * | 1976-12-23 | 1978-07-13 | Matsushita Electric Ind Co Ltd | Semoconductor davice and its production |
| JPS58130569A (en) * | 1982-01-28 | 1983-08-04 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58158972A (en) * | 1982-03-16 | 1983-09-21 | Toshiba Corp | Manufacture of semiconductor device |
| JPS58162064A (en) * | 1982-03-23 | 1983-09-26 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61292678A (en) * | 1985-06-21 | 1986-12-23 | 株式会社日立製作所 | Display controller |
| US5051805A (en) * | 1987-07-15 | 1991-09-24 | Rockwell International Corporation | Sub-micron bipolar devices with sub-micron contacts |
| JPH04278385A (en) * | 1991-03-07 | 1992-10-02 | Oji Paper Co Ltd | Thermal recording material |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH056345B2 (en) | 1993-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2804539B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH05206451A (en) | Mosfet and its manufacture | |
| JP2675713B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3450262B2 (en) | Circuit manufacturing method and circuit device | |
| JPH04348077A (en) | Thin-film transistor | |
| JPS5846193B2 (en) | semiconductor equipment | |
| JPS6074682A (en) | Manufacture of semiconductor device | |
| JPH06333944A (en) | Semiconductor device | |
| JPS59195870A (en) | Semiconductor device | |
| JPH10144918A (en) | Semiconductor device and its manufacturing method | |
| JP2971085B2 (en) | Method for manufacturing semiconductor device | |
| JPH08181223A (en) | Manufacture of semiconductor device | |
| JP3037100B2 (en) | Method for manufacturing semiconductor device | |
| JPH05218439A (en) | Semiconductor device and manufacture thereof | |
| JP2870131B2 (en) | Method for manufacturing semiconductor device | |
| JPH06132292A (en) | Semiconductor device and manufacture thereof | |
| JPH10284438A (en) | Semiconductor integrated circuit and its manufacture | |
| JPS60120570A (en) | Manufacture of semiconductor device | |
| JPH0290569A (en) | Manufacture of semiconductor device | |
| JPH0113230B2 (en) | ||
| JPS5975653A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH02201932A (en) | Mos field-effect transistor with high withstand voltage | |
| JPH03175676A (en) | Semiconductor device | |
| JPS61185974A (en) | Manufacture of semiconductor device | |
| JPS5810857A (en) | Complementary type mos semiconductor device |