JPS6041229A - Manufacture of semiconductor device and manufacturing equipment thereof - Google Patents
Manufacture of semiconductor device and manufacturing equipment thereofInfo
- Publication number
- JPS6041229A JPS6041229A JP14923783A JP14923783A JPS6041229A JP S6041229 A JPS6041229 A JP S6041229A JP 14923783 A JP14923783 A JP 14923783A JP 14923783 A JP14923783 A JP 14923783A JP S6041229 A JPS6041229 A JP S6041229A
- Authority
- JP
- Japan
- Prior art keywords
- etched
- etching
- substrate
- reaction chamber
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、被膜のエソチング工程に改良を加えた半導体
装置の製造方法及びその製造装置に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and an apparatus for manufacturing the same, in which a film ethoching process is improved.
従来技術と問題点
一般に、半導体装置を製造するにばウェハ上に形成した
所定の被膜の不要箇所を除去するエソヂング工程が必す
存在している。Prior Art and Problems In general, when manufacturing semiconductor devices, an etching process is necessary to remove unnecessary portions of a predetermined film formed on a wafer.
そのエソチング工程には、半導体素子の微細化に伴ない
、ドライ・エツチング法が適用されるようになった。そ
して、そのドライ・エツチング法の中でも、特にエツチ
ング形状に異方性を示し、且つ、エツチング物質とその
下地物質との間でエツチング速度の比、即ち、選択比を
大きく採ることができる反応性イオン・エツチング法が
重要視されている。With the miniaturization of semiconductor elements, dry etching has come to be applied to the etching process. Among the dry etching methods, reactive ions are used which exhibit anisotropy in the etching shape and can increase the etching rate ratio, that is, the selectivity, between the etching material and the underlying material.・Etching method is considered important.
この反応性イオン・エツチング法は、高周波に依り所定
エツチング・ガスをプラズマ状態にして分解し、その一
部を被エツチング物質と化学的に反応させてエツチング
を行ない、他の一部を物理的なスパツタリングに利用し
てエツチングをしているものであり、このように化学的
な過程と、物理的な過程を含んでいるごとに依り、その
エツチングは異方性を示し、また、大きな選択比が得ら
れているのである。This reactive ion etching method uses radio frequency waves to turn a specified etching gas into a plasma state and decompose it, and a part of it is chemically reacted with the material to be etched to perform etching, while the other part is physically etched. Etching is used for sputtering, and because it involves both chemical and physical processes, the etching exhibits anisotropy and has a large selectivity. It is obtained.
ところで、ごの反応性イオン・エツチング法に於いては
、エツチング進行中の成る時期には、電界に依って加速
されたイオン或いは電子が下地物ＷＦを直撃するので、
それに依る［１ｊ傷は回避することができない。By the way, in the reactive ion etching method described above, ions or electrons accelerated by the electric field directly hit the underlying material WF during the etching process.
It depends on [1j] Wounds cannot be avoided.
若し、前記下地物質が半導体装置の能動領域、例えばバ
イポーラ・トランジスタのエミッタ領域であって、その
エミソクｆｉｆｌ域の」二の被膜をエツチングする場合
等は問題である。A problem arises when the underlying material is an active region of a semiconductor device, for example, an emitter region of a bipolar transistor, and the second layer of the emitter region is to be etched.
このような反応（Ｉ＋イオン・エツチング法の欠点を解
消しようとし′６光化学反応を利用したエツチング法、
所謂、光エツチング法が開発された。In an attempt to overcome the drawbacks of such a reaction (I+ ion etching method), an etching method using a photochemical reaction,
A so-called photoetching method was developed.
この光エツチング法は、エツチング・ガスを解離してエ
ノチャンＩ・を生成する為に光エネルギを利用するもの
であり、このエネルギの大きさは、光ｍ子１個当り次式
で表される。This optical etching method utilizes optical energy to dissociate etching gas and generate enochan I. The magnitude of this energy per m photon is expressed by the following equation.
イ ・・・・ （１）
１）ニブランク定数 ６．（ｉ２６ Ｘ Ｉｎ−’ （
Ｊ Ｓ）Ｃ：光速 ２．９９８ Ｘ １１０８（Ｓ ’
）λ：光の波長
式（１）に於いて、ｈ及びＣは定数である為、光の波長
λが短いほど光量子１個当りが有するエネルギは大きい
ことになる。A... (1) 1) Ni blank constant 6. (i26 X In-' (
J S) C: Speed of light 2.998 x 1108 (S'
) λ: wavelength of light In equation (1), h and C are constants, so the shorter the wavelength λ of light, the greater the energy possessed by one photon.
従って、充分に波長が短い紫外光を用いれば、ガス分子
は解８１１され、エツチングに有用な分子、原子、ラジ
カル等のエッチャントが生成される。Therefore, if ultraviolet light with a sufficiently short wavelength is used, gas molecules will be decomposed and etchants such as molecules, atoms, and radicals useful for etching will be produced.
このように、光エツチング法では、エツチングに寄与す
る原子、ラジカル等のエッチャントを光エネルギに依っ
て生成しζいる為、電界に依って加速されたイオン或し
料Ｊ電子などは存在せず、従って、下地物質のｍ ｆＫ
Ｌ：ｊ生じない。In this way, in the photo-etching method, etchants such as atoms and radicals that contribute to etching are generated using light energy, so there are no ions or electrons accelerated by the electric field. Therefore, m fK of the underlying material
L:j does not occur.
前記したように、光エツチング法は下地物質を損傷しな
い旨の大きな利点を有しているが、未だ解決されない問
題を包含している。As mentioned above, although the photoetching method has the great advantage of not damaging the underlying material, it still includes unresolved problems.
例えば、塩素（Ｃ７りガスに依り多結晶シリコン層をエ
ツチングする場合には次の式に見られる反応を生ずる。For example, when a polycrystalline silicon layer is etched using chlorine (C7 gas), a reaction occurs as shown in the following equation.
紫り１光
↓
この時、多結晶シリ５コン層表面に付着しζいるＣｌ１
２が光化学反応に依り分解してＣＸ原子が形成されてＳ
ｉがエソートソグされる場合（前者）及び多結晶シリコ
ン層表面でなく、気相中でｃ７！ｂ子が形成されて拡ｔ
ｉｔに依り多結晶シリコン層表面に到達してＳｉと反応
する場合（後者）の二つの過程が存在する。Purple 1 light ↓ At this time, Cl1 attached to the surface of the polycrystalline silicon 5 layer
2 is decomposed by a photochemical reaction to form CX atoms and S
When i is sorted (former) and c7! is not on the surface of the polycrystalline silicon layer, but in the gas phase! A child is formed and expands.
There are two processes in which it reaches the surface of the polycrystalline silicon layer and reacts with Si (the latter).
そごで、前者の反応が支配的であれば、光を多結晶シリ
コン層に垂直に入射させることに依り、光の直進性を利
用した異方性エツチングが可能である。If the former reaction is dominant, it is possible to perform anisotropic etching by making the light perpendicularly incident on the polycrystalline silicon layer, taking advantage of the straightness of the light.
第１１３２１は前記異方性エツチングが行なわれたこと
を表わす半導体装置の要部切断側面し１である。No. 11321 is a side view 1 of a main part of the semiconductor device showing that the anisotropic etching has been performed.
図に於いて、１ばシリコン半導体基板、２は二酸化シリ
コン（Ｓｉ０２）欣、３は多結晶シリコン層、４はマス
クである５１０２膜をそれぞれ示している。In the figure, 1 is a silicon semiconductor substrate, 2 is a silicon dioxide (Si02) layer, 3 is a polycrystalline silicon layer, and 4 is a mask 5102 film.
図から判るように、マスクであるＳ ｉ Ｏ２膜４の形
状がそのまま多結晶シリコン層３に転写されている。As can be seen from the figure, the shape of the SiO2 film 4 serving as a mask is directly transferred to the polycrystalline silicon layer 3.
また、後者の反応が支配的であれば、解離したＣ７１原
子がランダムな速度成分を有して多結晶シリコン層に到
達する為、エツチングは異方性とはならずに等方性にな
る。If the latter reaction is dominant, the dissociated C71 atoms will reach the polycrystalline silicon layer with a random velocity component, so that the etching will not be anisotropic but isotropic.
第２図は前記等方性エツチングが行なわれたことを表わ
す半導体装置の要部切断側面図であり、第１図に関して
説明した部分と同部分は同記号で［汁示しである。FIG. 2 is a cross-sectional side view of essential parts of a semiconductor device showing that the isotropic etching has been performed, and the same parts as those described in connection with FIG. 1 are designated by the same symbols.
図から判るように、マスクである５ｉＯｚ膜４の下部に
在る多結晶シリコン層３もエツチングされてしまい、設
計値寸法通りの素子形成番才困難になる。As can be seen from the figure, the polycrystalline silicon layer 3 under the 5iOz film 4 serving as a mask is also etched, making it difficult to form elements according to the designed dimensions.
発明の目的
本発明４才、光エツチング法を実施するに際し、被エツ
チング物質！−（或いは基板）表面に付着しているエツ
チング・ガスを光化学反応で分解してエッチャントを生
成することに依り被エツチング物質Ｉ！４（或いＬ４基
板）がエツチングされる現象を支配的とするように制御
し、當に異方性エツチングがなされて微細１１つ絹布な
バターニングが可能である半導体装置の製造方法及びそ
れを実施する装置を提供する。Purpose of the Invention The present invention is four years old.When carrying out the photoetching method, the material to be etched! - The material to be etched (I) is etched by decomposing the etching gas adhering to the surface (or the substrate) through a photochemical reaction to generate an etchant. A method for manufacturing a semiconductor device in which the phenomenon of etching of L4 (or L4 substrate) is controlled to be dominant, and anisotropic etching is performed, thereby making it possible to perform fine 11 pattern patterning. Provide equipment for implementation.
発明の構成
一般に、ガス分子の固体表面への吸着に関しては、吸着
に要するエネルギが小さい場合、吸着速度Ｒａｄｓば次
の民で表わされる。Structure of the Invention In general, regarding the adsorption of gas molecules onto a solid surface, when the energy required for adsorption is small, the adsorption rate Rads is expressed by the following number.
ｐ：反応室内圧力
Ｔ：固体温度
Ｃ：定数
この式（３）から明らかなように、被エツチング物質層
（固体）温度を低−トさせることに依り、吸着速度Ｒａ
ｄ５を一定に維持したままで反応室内圧力を低下さ−ｌ
るごとかできる。p: Reaction chamber pressure T: Solid temperature C: Constant As is clear from this equation (3), by lowering the temperature of the material layer (solid) to be etched, the adsorption rate Ra
The pressure in the reaction chamber is lowered while keeping d5 constant.
I can do everything.
光化学反応にｔｈリエソチング・ガスの分解を行ない所
定物質をエツチングする場合、前記現象を利用し、被エ
ツチング物質層を冷却すれば、エツチング・ガス分子の
被エツチング物質層への付着速度を大きくすることがで
き、従って、反応室内のエツチング・ガス圧力を低下さ
せても被エツチング物質層表面には充分なエツチング・
ガス分子が付着されることになり、しかも、前記した光
照射に依る気相中でのエツチング・ガスの解離を低減す
ることが可能となり、被エツチング物質層表面に付着し
たエツチング・ガス分子への光照射に依る解離反応を支
配的にすることができ、第１図に見られるようなマスク
通りの微細加工が実現される。When a predetermined material is etched by decomposing the th resooching gas in a photochemical reaction, by utilizing the above phenomenon and cooling the layer of the material to be etched, the speed at which the etching gas molecules attach to the layer of the material to be etched can be increased. Therefore, even if the etching gas pressure in the reaction chamber is reduced, sufficient etching and etching will not occur on the surface of the material layer to be etched.
In addition, it becomes possible to reduce the dissociation of the etching gas in the gas phase caused by the above-mentioned light irradiation, and the etching gas molecules attached to the surface of the material layer to be etched can be attached to the etching gas molecules. The dissociation reaction caused by light irradiation can be made dominant, and microfabrication according to the mask as shown in FIG. 1 can be realized.
そこで、本発明は、反応室内に被エツチング物質層（或
いは基板）を配置し、次いで、該被工・７チング物質層
（或Ｇ料Ｊ°基板）を冷却し、次いで、前記反応室内に
エツチング・ガスを導入してから該エツチング・ガスを
光化学反応で解離することに依り得られるエッチャント
で前記被エツチング層（或いは基板）のエツチングを行
なう工程を採ることを特徴とし、また、その工程を実施
する装置として、ガス供給管及び排気管を有する反応室
、該反応室内に露出されて光が照射され得る位置に配置
され目、つ載置された被エツチング物質Ｎ（或いは基板
）を冷却する冷却器を備えるなることを特徴としている
。Therefore, in the present invention, a material layer to be etched (or a substrate) is placed in a reaction chamber, the material layer to be etched (or a substrate) is cooled, and then an etching material layer (or a substrate) is placed in the reaction chamber.・It is characterized by adopting a step of etching the layer to be etched (or the substrate) with an etchant obtained by introducing a gas and dissociating the etching gas by a photochemical reaction, and carrying out the step. The apparatus includes a reaction chamber having a gas supply pipe and an exhaust pipe, an eye placed in a position exposed in the reaction chamber where it can be irradiated with light, and a cooling device for cooling the material to be etched (or the substrate) placed thereon. It is characterized by having a container.
発明の実施例
第３図は本発明に於りる半導体装置の製造方法の一例を
実施する本発明に依る半導体装置の製造装置を説明する
要部説明図である。Embodiment of the Invention FIG. 3 is a diagram illustrating a main part of a semiconductor device manufacturing apparatus according to the present invention, which implements an example of the semiconductor device manufacturing method according to the present invention.
図に於いて、１１はエキシマ・レーザ光発生器、１２は
ミラー、１３は集光用レンズ、１４ば反応室、Ｉ５は紫
外光透過窓、１６はエツチング・ガス供給管、１７ば排
気管、１８はＸ−Ｙステージ、１９は冷却器、２（Ｈ：
ｌ被エツチング物質基板をそれぞれ示し“ζいる。In the figure, 11 is an excimer laser beam generator, 12 is a mirror, 13 is a condensing lens, 14 is a reaction chamber, I5 is an ultraviolet light transmission window, 16 is an etching gas supply pipe, 17 is an exhaust pipe, 18 is an X-Y stage, 19 is a cooler, 2 (H:
The material substrates to be etched are each shown as "ζ".
この一実施例の製造装置を用いて製造方法の一例を実施
する場合を説明する。A case will be described in which an example of a manufacturing method is implemented using the manufacturing apparatus of this embodiment.
最初、被エツチング物質基板２０を反応室１４内に露出
されている冷却器１９−ヒにセットする。First, the material substrate 20 to be etched is set in the cooler 19-hi exposed within the reaction chamber 14.
次いで、残留ガスの影響を低減させる為に約ＩＸ １０
−６（Ｔｏ ｒ ｒ）程度まで真空排気する。Then about IX 10 to reduce the effects of residual gas.
Evacuate to about -6 (Torr).
次いで、被エツチング物質基板２０の冷却を開始する。Next, cooling of the material substrate 20 to be etched is started.
ここで、エツチング時の反応室１４内に於ける圧力を被
エツチング物質基板２０の冷却をしない場合の１７１０
に低下させようとすると、前記式（３）から次の関係が
得られる。Here, the pressure in the reaction chamber 14 during etching is set to 1710 when the substrate 20 to be etched is not cooled.
When trying to reduce the value to , the following relationship is obtained from the above equation (3).
Ｔ２＝ＴＩ／４．６４ ・・・・ （４）Ｔ、：冷却な
しの場合の基板温度
室温を２０〔℃〕とすると
Ｔ１は２９３（Ｋ）
Ｔ２：冷却ありの場合の基板温度
従って、式（４）の関係から、ＴＩを室温と劣えるとＴ
２は６３（Ｋ）となる。そこで、被エツチング物質基板
２０の温度を６３（Ｋ）まで低下させる。T2=TI/4.64 (4) T: Substrate temperature without cooling If the room temperature is 20 [℃], T1 is 293 (K) T2: Substrate temperature with cooling Therefore, the formula From the relationship (4), if TI is inferior to room temperature, T
2 becomes 63 (K). Therefore, the temperature of the material substrate 20 to be etched is lowered to 63 (K).
次いで、エツチング・ガスである塩素を反応室１４中に
導入する。尚、その際の反応室１４中の圧力は５Ｘ］０
−３（Ｔｏｒｒ）とする。Chlorine, which is an etching gas, is then introduced into the reaction chamber 14. In addition, the pressure in the reaction chamber 14 at that time is 5X]0
−3 (Torr).
０
次いで、エキシマ・レーザ光発生器１１からの紫外光を
被エツチング物質基板２０に照射する。0 Next, the material substrate 20 to be etched is irradiated with ultraviolet light from the excimer laser light generator 11.
この場合の光源としては、紫外波長に於いて高１１１力
が得られるエキシマ・レーザ或いは水銀ランプを用いる
ことが好ましい。As the light source in this case, it is preferable to use an excimer laser or a mercury lamp that can provide a high 111 power in the ultraviolet wavelength.
前記説明した工程を経ることに依り、光照射された被エ
ツチング物質基板２０の表面では前記式（２）で示した
反応をη二じ、被エツチング物質、例えば多結晶シリコ
ンの異方性エツチングができる。尚、Ｘ−Ｙステージ１
８を駆動することに依り、被エツチング物質基板２０全
面での選択的エツチングが可能であることは云うまでも
ない。By going through the above-described steps, the surface of the substrate 20 of the material to be etched irradiated with light undergoes the reaction shown in equation (2) by η2, and the anisotropic etching of the material to be etched, for example, polycrystalline silicon. can. Furthermore, X-Y stage 1
Needless to say, by driving 8, selective etching of the entire surface of the substrate 20 of the material to be etched is possible.
発明の効果
本発明に依れば、ガス供給管及び排気管を有する反応室
内に露出されて光が照射され１ｉＩる位置に配置されて
いる冷却器上に被エツチング物質層（或いは乱扱）を配
置し、次いで、該被エツチング物質層（或い６才基板）
を冷却し、次いで、前記反応室内にエツチング・ガスを
導入してから該エツチング・ガスを光化学反応で解離す
ることに依り１
得られるエッチャントで前記被エツチング物質層（或い
は基板）をエツチングするようにしているので、エツチ
ング・ガス分子が被エツチング物質層へ付着する速度を
大きくすることができ、従って、反応室内のエツチング
・ガスの圧力を低下させることが可能になり、その結果
、光照射に依る気相中でのエツチング・ガスの解離を抑
制して、被エツチング物質層（或いは基板）表面に付着
したエツチング・ガス分子への光照射に依る解離反応を
支配的にすることができ、それに依り、エツチングは異
方性になり、微細パターンの形成に有効となるものであ
る。Effects of the Invention According to the present invention, a layer of material to be etched (or rough handling) is formed on a cooler placed at a position exposed and irradiated with light in a reaction chamber having a gas supply pipe and an exhaust pipe. and then the layer of the material to be etched (or the 6-year old substrate)
and then introducing an etching gas into the reaction chamber and dissociating the etching gas by a photochemical reaction. This increases the rate at which the etching gas molecules attach to the layer of the material to be etched, thus making it possible to reduce the pressure of the etching gas in the reaction chamber, thereby reducing the It is possible to suppress the dissociation of the etching gas in the gas phase and make the dissociation reaction caused by light irradiation on the etching gas molecules attached to the surface of the material layer to be etched (or the substrate) to be dominant. , the etching becomes anisotropic and effective in forming fine patterns.
第１図及び第２図は異方性エツチング及び等方性エツチ
ングを説明する為の半導体装置の要部切断側面図、第３
図は本発明一実施例である半導体装置の製造装置の要部
説明図である。
図に於いて、１はシリコン半導体基板、２は二酸化シリ
コン（Ｓｉ０２）膜、３は多結晶シリコン層、４はマス
クであるＳ ｉ Ｏ２膜、１１ばエキ２
シマ・レーデ光発生器、１２はミラー、１３は集光用レ
ンズ、１４は反応室、１５は紫外光透過窓、１６はエツ
チング・ガス供給管、１７は排気管、１８はＸ−Ｙステ
ージ、１つは冷却器、２ｏば被エツチング物質基板であ
る。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
３
１５１−
第１図
第 ２ 図1 and 2 are cutaway side views of essential parts of a semiconductor device for explaining anisotropic etching and isotropic etching, and 3.
The figure is an explanatory diagram of main parts of a semiconductor device manufacturing apparatus which is an embodiment of the present invention. In the figure, 1 is a silicon semiconductor substrate, 2 is a silicon dioxide (Si02) film, 3 is a polycrystalline silicon layer, 4 is a SiO2 film that is a mask, 11 is an excitation 2, and 12 is a sima-lede light generator. mirror, 13 is a condensing lens, 14 is a reaction chamber, 15 is an ultraviolet light transmission window, 16 is an etching gas supply pipe, 17 is an exhaust pipe, 18 is an X-Y stage, 1 is a cooler, 2o is a Etching material substrate. Patent Applicant: Fujitsu Ltd., Representative Patent Attorney: Shoji Aitani; Representative Patent Attorney: Hiroshi Watanabe - 3 151- Figure 1 Figure 2
Claims (2)
いで、前記反応室内にエツチング・カスを導入してから
該エツチング・ガスを光化学反応で解離することに依り
得られるエッチャントで前記被エツチング体のエツチン
グを行なう工程が含まれてなることを特徴とする半導体
装置の製造方法。(1) The object to be etched is placed in a reaction chamber and cooled, and then the object to be etched is etched with an etchant obtained by introducing etching gas into the reaction chamber and dissociating the etching gas by a photochemical reaction. A method for manufacturing a semiconductor device, comprising a step of etching the body.
内に露出されて光が照射され得る位置に配置され且つ載
置された被エツチング体を冷却する冷却器を備えてなる
ことを特徴とする半導体装置の製造装置。(2) It is characterized by comprising a reaction chamber having a gas supply pipe and an exhaust pipe, and a cooler for cooling the object to be etched placed and placed in a position exposed in the reaction chamber where it can be irradiated with light. Manufacturing equipment for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14923783A JPS6041229A (en) | 1983-08-17 | 1983-08-17 | Manufacture of semiconductor device and manufacturing equipment thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14923783A JPS6041229A (en) | 1983-08-17 | 1983-08-17 | Manufacture of semiconductor device and manufacturing equipment thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041229A true JPS6041229A (en) | 1985-03-04 |
| JPH0478005B2 JPH0478005B2 (en) | 1992-12-10 |
Family
ID=15470874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14923783A Granted JPS6041229A (en) | 1983-08-17 | 1983-08-17 | Manufacture of semiconductor device and manufacturing equipment thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041229A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61283129A (en) * | 1985-06-08 | 1986-12-13 | Sony Corp | Etching method |
| JPS62174969A (en) * | 1986-01-28 | 1987-07-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6365648A (en) * | 1986-09-05 | 1988-03-24 | Fujitsu Ltd | Manufacture of semiconductor substrate |
| JPS63110726A (en) * | 1986-10-29 | 1988-05-16 | Hitachi Ltd | Etching method |
| JPH01103836A (en) * | 1987-07-02 | 1989-04-20 | Toshiba Corp | Dry etching and apparatus therefor |
| JPH01295424A (en) * | 1988-01-14 | 1989-11-29 | Sanyo Electric Co Ltd | Photo-excited etching method |
| JPH02220438A (en) * | 1989-02-22 | 1990-09-03 | Hitachi Ltd | Method and apparatus for laser treatment |
| JPH0342825A (en) * | 1989-07-11 | 1991-02-25 | Tokyo Electron Ltd | Ashing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55149643A (en) * | 1979-05-07 | 1980-11-21 | Perkin Elmer Corp | Method and device for chemically treating material to be treated |
| JPS57202732A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Fine pattern formation |
| JPS5863136A (en) * | 1981-10-09 | 1983-04-14 | Seiko Epson Corp | Optical dry etching device |
-
1983
- 1983-08-17 JP JP14923783A patent/JPS6041229A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55149643A (en) * | 1979-05-07 | 1980-11-21 | Perkin Elmer Corp | Method and device for chemically treating material to be treated |
| JPS57202732A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Fine pattern formation |
| JPS5863136A (en) * | 1981-10-09 | 1983-04-14 | Seiko Epson Corp | Optical dry etching device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61283129A (en) * | 1985-06-08 | 1986-12-13 | Sony Corp | Etching method |
| JPS62174969A (en) * | 1986-01-28 | 1987-07-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6365648A (en) * | 1986-09-05 | 1988-03-24 | Fujitsu Ltd | Manufacture of semiconductor substrate |
| JPS63110726A (en) * | 1986-10-29 | 1988-05-16 | Hitachi Ltd | Etching method |
| JPH01103836A (en) * | 1987-07-02 | 1989-04-20 | Toshiba Corp | Dry etching and apparatus therefor |
| JPH01295424A (en) * | 1988-01-14 | 1989-11-29 | Sanyo Electric Co Ltd | Photo-excited etching method |
| JPH02220438A (en) * | 1989-02-22 | 1990-09-03 | Hitachi Ltd | Method and apparatus for laser treatment |
| JPH0342825A (en) * | 1989-07-11 | 1991-02-25 | Tokyo Electron Ltd | Ashing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0478005B2 (en) | 1992-12-10 |
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