JPS6040739B2 - semiconductor switch - Google Patents
semiconductor switchInfo
- Publication number
- JPS6040739B2 JPS6040739B2 JP12086179A JP12086179A JPS6040739B2 JP S6040739 B2 JPS6040739 B2 JP S6040739B2 JP 12086179 A JP12086179 A JP 12086179A JP 12086179 A JP12086179 A JP 12086179A JP S6040739 B2 JPS6040739 B2 JP S6040739B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- switch
- anode
- pnpn
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/73—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
Landscapes
- Thyristor Switches And Gates (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
本発明は、ＰＮＰＮスイッチを用い、そのｄｖ′ｄｔ耐
量を高める工夫を施した半導体スイッチに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor switch that uses a PNPN switch and is designed to increase its dv'dt withstand capability.
ＰＮＰＮスイッチは、正負に高い阻止耐圧が得られる事
と、自己保持作用によって小さな制御電力で大電力を制
御し得る特徴を有し、半導体スイッチとして有用な素子
である。A PNPN switch is a useful element as a semiconductor switch because it has the characteristics of being able to obtain high blocking voltage in both the positive and negative directions and controlling a large amount of power with a small amount of control power due to its self-holding action.
しかし、その反面、ＰＮＰＮスイッチのァノードとカソ
ード間に急激な日頃方向電圧上昇（雑音電圧）があると
、その電圧変化率ｄｖ／ｄｔによって誤点弧してしまう
欠点がある。そこでｄｖ／ｄｔ耐量を高めることが考え
られるが、それには充分な配慮が必要がある。通常はＰ
ＮＰＮスイッチのゲートーカソード間を低抵抗で短絡し
てｄｖ／ｄｔ耐量を高めているが、その方法では制御感
度が劣化する欠点を持つ。そこで、従釆技術においては
、第１図から第３図に示す如き回路構成をとっている。However, on the other hand, if there is a sudden daily voltage increase (noise voltage) between the anode and cathode of the PNPN switch, there is a drawback that the voltage change rate dv/dt may cause false firing. Therefore, it is possible to increase the dv/dt tolerance, but this requires sufficient consideration. Usually P
The gate and cathode of the NPN switch are short-circuited with a low resistance to increase the dv/dt tolerance, but this method has the disadvantage of deteriorating control sensitivity. Therefore, in the follow-up technology, circuit configurations as shown in FIGS. 1 to 3 are adopted.
すなわち、第１図の方法は、ＰＮＰＮスイッチ１のゲー
トＧ−力ソードＫ間にトランジスタ２のコレクタ、エミ
ッタを接続して、トランジスタ２のベースはコンデンサ
３を介してＰＮＰＮスィッチーのアノードＡと接続した
ものであり、ｄｖ／ｄｔ印加時には、コンデンンサ３の
充電電流でトランジスタ２を過渡的に動作させ、ゲート
Ｇ−カソードＫ間を短絡しようとするものである。通常
はトランジスタ２は動作していないので、ゲートＧから
の制御感度は何ら劣化しない。従って、第１図はｄｖ／
ｄ側寸量と制御感度を両立させる上で優れている。しか
し、コンデンサ３は半導体ＩＣの中では占有面積を多く
必要として集積化に不向きな回路である。そこで集積回
路化に有利な手法として、当出願人は第２図の如く、ト
ランジスタ２のベースとＰＮＰＮスィッチーのア／ード
Ａに隣接する層（アノードゲート）との間にダイオード
４を設け、ダイオード４の接合容量を充電する電流で第
１図と同様な過渡短絡を行なおうとする方法を提案して
いる。That is, in the method shown in FIG. 1, the collector and emitter of transistor 2 are connected between the gate G and power sword K of PNPN switch 1, and the base of transistor 2 is connected to the anode A of the PNPN switch via capacitor 3. When dv/dt is applied, the transistor 2 is operated transiently by the charging current of the capacitor 3 to short-circuit between the gate G and the cathode K. Normally, the transistor 2 is not operating, so the control sensitivity from the gate G does not deteriorate at all. Therefore, Figure 1 shows dv/
It is excellent in achieving both d-side size and control sensitivity. However, the capacitor 3 is a circuit that is not suitable for integration because it requires a large area in a semiconductor IC. Therefore, as a method advantageous for integrated circuit implementation, the present applicant provided a diode 4 between the base of the transistor 2 and the layer (anode gate) adjacent to the a/de A of the PNPN switch, as shown in FIG. A method is proposed in which a transient short circuit similar to that shown in FIG. 1 is created using a current that charges the junction capacitance of the diode 4.
しかし、この方法は、アノードＡに隣接したＮ層（アノ
ードゲート）からダイオード４の方向に微分電流が流れ
る事から、ァノードゲート駆動が加わった事にもなり、
ｄｖ′ｄｔ耐量は第１図の方法より若干劣化することが
考えられる。さらに、ァノードゲート駆動をなくしなが
ら、第１図を集積回路化する方法として、第３図の方法
も提案されている。However, in this method, a differential current flows from the N layer (anode gate) adjacent to the anode A in the direction of the diode 4, so the anode gate drive is also added.
It is conceivable that the dv'dt tolerance is slightly degraded compared to the method shown in FIG. Furthermore, the method shown in FIG. 3 has also been proposed as a method of integrating the circuit shown in FIG. 1 while eliminating the anode gate drive.
第３図では、アノードＡとトランジスタ２のベース間に
、第２のトランジスタ５を設け、そのベースはどこにも
接続されていない。かかる構成もｄｖ′ｄｔ耐量がやや
劣化する欠点を持つ。なぜならば、第２のトランジスタ
５のベース端子はいずれにも接続されていないため、該
回路のアノードＡーカソードＫ間に早い周期でｄｖ／ｄ
ｔパルスを繰返し印加すると、該ベースに電荷が蓄積さ
れたままとなり、微分電流が減少して実質的にｄｖ′ｄ
ｔ両寸量の大中向上が望みにくくなるからである。本発
明は上記した欠点をなくし、集積化に適し、ｄｖ／ｄｔ
耐量の優れた半導体スイッチを提供しようとするもので
ある。In FIG. 3, a second transistor 5 is provided between the anode A and the base of the transistor 2, and its base is not connected to anything. Such a configuration also has the disadvantage that the dv'dt tolerance is slightly degraded. This is because the base terminal of the second transistor 5 is not connected to any one, so the dv/d between the anode A and the cathode K of the circuit is fast.
When t pulses are repeatedly applied, the charge remains accumulated at the base, and the differential current decreases to substantially dv'd
This is because it becomes difficult to expect improvements in both dimensions. The present invention eliminates the above-mentioned drawbacks, is suitable for integration, and has a dv/dt
The present invention aims to provide a semiconductor switch with excellent durability.
本発明は、２つのＰＮＰＮスイッチを互いに逆並列に接
続せしめ、該逆並列の２つのＰＮＰＮスイッチのアノー
ドゲートを共通とし、且つ３つのトランジスタによって
スイッチ切換を行なわしめるようにしたものである。In the present invention, two PNPN switches are connected in antiparallel to each other, the anode gates of the two antiparallel PNPN switches are common, and the switching is performed by three transistors.
この際、アノードゲート端にはＰＮ接合を通じて電荷放
電を行わしめる構成とした。以下、本発明を実施例によ
って詳細に説明を行なう。At this time, a configuration was adopted in which charge discharge was performed through a PN junction at the anode gate end. Hereinafter, the present invention will be explained in detail with reference to Examples.
第４図は本発明の先願となる待機昭５３−６７６９８号
（特公昭５８−５６０８号）に記載の回路図であり、ア
ノードＡ、カソードＫ、ゲートＧを持つＰＮＰＮスイッ
チ１１のゲートＧ−カソードＫ間には、第１のトランジ
スタ（ＮＰＮ型）１２のコレクタ、ヱミツタを接続し、
そのベースは、ェミツタをＰＮＰＮスイッチ１１のアノ
ードＡに接続した第２のトランジスタ（ＰＮＰ型）１６
のコレクタと接続している。FIG. 4 is a circuit diagram described in Patent Publication No. 53-67698 (Japanese Patent Publication No. 58-5608), which is a prior application of the present invention, and is a circuit diagram of a PNPN switch 11 having an anode A, a cathode K, and a gate G. Between the cathode K, the collector and emitter of the first transistor (NPN type) 12 are connected,
Its base is connected to a second transistor (PNP type) 16 whose emitter is connected to the anode A of the PNPN switch 11.
is connected to the collector.
そして、第２のトランジスタ１６のベースには、ダイオ
ード１７のアノード側を接続し、そのダイオード１７の
カソードはＰＮＰＮスイッチ１１のアノードＡに隣接し
たＮ層（アノードゲート）と接続してある。ダイオード
１７は以下に述べる如く、第２のトランジスタ１６のベ
ースに蓄積する電荷を放電させてＰＮＰＮスイッチ１１
のアノードゲートの電位より高い電圧にならないように
しようとするものである。かかる構成によれば、ＰＮＰ
Ｎスイッチ１ １のアノードＡ、カソードＫ間に順万向
電圧上昇が加わると、第２のトランジスタ１６のベース
、コレクタ接合に存在する接合容量を充電する電流がミ
ラー増中されて、第１のトランジスタ１２のベースに流
れ込み、第１のトランジスタ１２が動作してＰＮＰＮス
イッチ１１のゲートＧ、カソードＫ間を短絡し、ＰＮＰ
Ｎスイッチ１１の中央の接合充電電流によるレィト効果
を防止する事ができる。この時、ダイオード１７の両端
の電位差はほとんどない（ダイオードＩ７の両端は、ア
ノードＡから共に接合を１つずつ経由した電位にあり、
ほとんど同電位）上に、仮に電位差があったにしてもダ
イオード１７の極性はアノードゲートから流れ出す電流
を阻止する方向に向いており、第２図の例で指摘した問
題は全く生じない。一方、ＰＮＰＮスイッチ１１のアノ
ードＡ、カソードＫ間に直流電圧が加えられた状態でゲ
ートＧに電流を供給してそのＰＮＰＮスイッチ１１を点
弧させると、Ａ−Ｋ間の電位差は低下（約ＩＶ）するが
、もし、ダイオード１７がない第３図の状態では点弧前
にトランジスタ５のベースコレクタ間に充電されていた
電荷（ベースが正、コレクタが負の電荷）はベース、ェ
ミッ夕が阻止方向となっているため放電できす、先に第
３図で述べたような問題を生ずるが、第４図で示す本発
明の実施例ではダイオード１７を設けてあるので、トラ
ンジスタ１６のベースに蓄積されていた電荷はＰＮＰＮ
スイッチ１１のアノードゲート（Ｎ層）に向って流れ去
り、すみやかにアノードゲート電位に近ず〈。この結果
、次回に加わる庄原電圧上昇に対しても充分なｄｖ／ｄ
ｔ保護作用が得られる。第５図は本発明の原理にかかわ
る回路図であり、ここでは、第４図に示したダイオード
１７の代りに、ＰＮＰＮスイッチ２１のアノードＡに隣
接したＮ層なるアノードゲートにもう一つの領域（Ｐｃ
）を付加し、第２のトランジスタ２６のべ−スを該領域
（Ｐｃ）と接続したものである。The anode side of a diode 17 is connected to the base of the second transistor 16, and the cathode of the diode 17 is connected to the N layer (anode gate) adjacent to the anode A of the PNPN switch 11. The diode 17 discharges the charge accumulated in the base of the second transistor 16 and connects the PNPN switch 11, as described below.
The purpose is to prevent the voltage from becoming higher than the potential of the anode gate. According to this configuration, PNP
When a voltage increase is applied across the anode A and cathode K of the N switch 1 1, the current charging the junction capacitance existing at the base and collector junction of the second transistor 16 is increased by the mirror, The flow flows into the base of the transistor 12, and the first transistor 12 operates to short-circuit between the gate G and cathode K of the PNPN switch 11, and the PNP
The rate effect due to the junction charging current at the center of the N switch 11 can be prevented. At this time, there is almost no potential difference between both ends of the diode 17 (both ends of the diode I7 are at a potential that has passed through one junction from the anode A,
Even if there is a potential difference between the diode 17 (almost the same potential), the polarity of the diode 17 is oriented to block the current flowing from the anode gate, and the problem pointed out in the example of FIG. 2 does not occur at all. On the other hand, when a current is supplied to the gate G with a DC voltage applied between the anode A and cathode K of the PNPN switch 11 to fire the PNPN switch 11, the potential difference between A and K decreases (approximately IV ) However, if the diode 17 is not present in the state shown in Figure 3, the charge that was charged between the base and collector of the transistor 5 before ignition (positive charge on the base and negative charge on the collector) will be blocked by the base and emitter. However, in the embodiment of the present invention shown in FIG. 4, since the diode 17 is provided, the discharge cannot occur at the base of the transistor 16. The charge that was
It flows away toward the anode gate (N layer) of the switch 11 and quickly approaches the anode gate potential. As a result, sufficient dv/d is available for the next Shobara voltage increase.
A protective effect is obtained. FIG. 5 is a circuit diagram related to the principle of the present invention. Here, in place of the diode 17 shown in FIG. 4, another region ( Pc
), and the base of the second transistor 26 is connected to the region (Pc).
ＰＮＰＮスイッチ２１にこの種の付加領域Ｐｃを設ける
事は、半導体技術では容易に実施できる構造である。か
かる構成によっても、第２のトランジスタ２６のベース
は、１つのＰＮ接合を介してアノードゲートと接続した
事に等価でり、第４図の実施例と同様な効果が得られる
。しかも、独立したダイオードが不要であって半導体Ｉ
Ｃ化する上でも有利な構成である。第６図は本発明の実
施例になる回路図である。Providing this type of additional region Pc in the PNPN switch 21 is a structure that can be easily implemented using semiconductor technology. Even with this configuration, the base of the second transistor 26 is equivalent to being connected to the anode gate through one PN junction, and the same effect as the embodiment shown in FIG. 4 can be obtained. Moreover, there is no need for an independent diode, and semiconductor I
This is an advantageous configuration when converting to C. FIG. 6 is a circuit diagram of an embodiment of the present invention.
ここでは、アノード層（Ｎ層）を共通とし、前例と同様
な付加領域（Ｐｃ）を設けた逆並列ＰＮＰＮスイッチ３
１，３ １′のそれぞれのゲートＧ，，Ｇ２、カソー
ドＴ，（あるいはＴ２）端子間に、第１のトランジスタ
３２、３２′のコレクタ、ェミツタ、及び抵抗３８，３
８′を接続している。各第１のトランジスタ３２，３２
′のベース、エミツタにはダイオード３９，３９′を設
けており、各ベースは第２のトランジスタ３６と図示の
如く接続している。そして第２のトランジスタ３６のベ
ースは、ＰＮＰＮスイッチ３ １，３ １′の付加領域
（Ｐｃ）に接続している。図に於て、第２のトランジス
タ３６はェミッタを２個有し、コレクタのないものとし
て示したが、２つのェミツタの部分は印加される電圧の
極性によってある時は、一方が真のェミッタ他方がコレ
クタとして働き、また、逆の極性では一方がコレクタ他
方が真のェミッタとして作用するものである。この構成
は、集積回路に於てラテラルトランジス夕として構成す
れば容易に実現でき、２つのェミッタとべ−ス間の逆阻
止耐圧は共に高い。また、抵抗３８，３８′はＰＮＰＮ
スイッチ３１，３１′の高温リーフ電流に対する安定性
を与えようとするものであって、比較的高抵抗が選ばれ
る。さらに、ダイオード３９，３９′は、第２のトラン
ジスタ３６の２つの工ミツ夕にＰＮＰＮスイッチ３ １
，３ １′の２つの主端子Ｔ，，Ｔ２間の電圧を該ダィ
オ−ド３９，３９′を通して間接的に印加できるように
設計したものであり、また、回路中の発振防止の役割（
詳細な説明は省略する。）をも合せ持っている。かかる
構成に於て、例えば主端子Ｔ２に対し、主端子Ｔ，の電
位が正万向に上昇する時（Ｔ，がアノードＡで、Ｔ２が
カソードＫ）には、ダイオード３９′を介してトランジ
スタ３６の図示上側ェミッタに主端子Ｔ，の電位が印加
され、第５図と同様にトランジスタ３２が動作してＰＮ
ＰＮスイッチ３１の謀点弧を防止する。（この場合、Ｐ
ＮＰＮスイッチ３１′は逆阻止状態にある。）ＰＮＰＮ
スイッチ３１を点弧制御した時には、付加領域Ｐ（Ｐｃ
）とアノードゲート間にできるＰＮ接合が、トランジス
タ３６のベースの電荷放出に顕著な効果を表わす事は前
例と同様である。そして、電位関係が正負逆転した時に
はダイオード３９、トランジスタ３６，３２′によつて
、ＰＮＰＮスイッチ３１′のレィト効果を防止できる。
ここで、ＰＮＰＮスイッチ３１，３１′はアノードゲー
ト層（Ｎ層）を共通とした逆並列スイッチの例で示した
が、通常の２つのＰＮＰＮスイッチを逆並列接続した構
成でもよい。なお、以上の説明に於ては、暗黙の内に第
２のトランジスタ１６，２６，３６はＰＮＰＮスイッチ
と同時に集積化した時、正負双方向に高耐圧が得られる
ＰＮＰ形として記載したが、これらの実施例のＰ型、Ｎ
型を全て反転した相補な回路構成も実施できることはい
うまでもない。Here, the anti-parallel PNPN switch 3 has a common anode layer (N layer) and an additional region (Pc) similar to the previous example.
Between the respective gates G, , G2, cathodes T, (or T2) terminals of the first transistors 32, 32', and the resistors 38, 31', the collectors and emitters of the first transistors 32, 32'
8' is connected. Each first transistor 32, 32
Diodes 39 and 39' are provided at the base and emitter of the transistor 1, and each base is connected to a second transistor 36 as shown. The base of the second transistor 36 is connected to the additional region (Pc) of the PNPN switch 3 1, 3 1'. In the figure, the second transistor 36 is shown as having two emitters and no collector, but depending on the polarity of the applied voltage, one of the two emitters may be a true emitter while the other is a true emitter. acts as a collector, and with opposite polarity, one acts as a collector and the other acts as a true emitter. This configuration can be easily realized by configuring it as a lateral transistor in an integrated circuit, and the reverse blocking voltage between the two emitters and the base is both high. Also, resistors 38 and 38' are PNPN
A relatively high resistance is chosen to provide stability to the high temperature leaf currents of the switches 31, 31'. Furthermore, the diodes 39, 39' connect the two transistors of the second transistor 36 to the PNPN switch 31.
, 31' is designed so that the voltage between the two main terminals T, , T2 can be applied indirectly through the diodes 39, 39', and also serves to prevent oscillation in the circuit (
Detailed explanation will be omitted. ). In such a configuration, for example, when the potential of the main terminal T increases in the opposite direction with respect to the main terminal T2 (T is the anode A and T2 is the cathode K), the transistor is connected via the diode 39'. The potential of the main terminal T is applied to the illustrated upper emitter of 36, and the transistor 32 operates as in FIG.
To prevent accidental firing of the PN switch 31. (In this case, P
NPN switch 31' is in a reverse blocking state. )PNPN
When the switch 31 is ignited, the additional area P (Pc
) and the anode gate have a significant effect on charge discharge from the base of the transistor 36, as in the previous example. When the potential relationship is reversed, the rate effect of the PNPN switch 31' can be prevented by the diode 39 and the transistors 36 and 32'.
Here, the PNPN switches 31 and 31' are shown as anti-parallel switches having a common anode gate layer (N layer), but they may also have a configuration in which two ordinary PNPN switches are connected in anti-parallel. Note that in the above explanation, the second transistors 16, 26, and 36 are implicitly described as PNP types that can obtain high withstand voltage in both positive and negative directions when integrated together with a PNPN switch. Examples of P type, N
Needless to say, a complementary circuit configuration in which the types are completely inverted can also be implemented.
以上説明した如く、本発明によれば、ＰＮＰＮスイッチ
のｄｖ／ｄｔ耐量を改善でき、集積化が容易で、特に早
い周期の電圧変化が加わる半導体スイッチに有役な技術
を提供できる。As described above, according to the present invention, the dv/dt withstand capability of a PNPN switch can be improved, integration is easy, and it is possible to provide a technology that is particularly useful for semiconductor switches that are subject to fast-cycle voltage changes.
第１図〜第３図は、公知の技術による半導体スイッチの
回路構成図、第４図は本発明の先願の回路例図、第５図
は本発明の原理図、第６図は本発明の実施例による半導
体スイッチの回路構成図である。
１ １，２ １，３ １，３ １′・・・・・・ＰＮＰ
Ｎスイツチ、１２，２２，３２，３２′……第１のトラ
ンジスタ、１６，２６，３６……第２のトランジスタ、
１７，３９，３９′……ダイオード、３８，３８′・・
・・・・抵抗。
第１図
第２図
第３図
第４図
第５図
第６図1 to 3 are circuit configuration diagrams of a semiconductor switch according to known technology, FIG. 4 is a circuit example diagram of a prior application of the present invention, FIG. 5 is a principle diagram of the present invention, and FIG. 6 is a diagram of the present invention. FIG. 2 is a circuit configuration diagram of a semiconductor switch according to an embodiment of the present invention. 1 1,2 1,3 1,3 1'...PNP
N switch, 12, 22, 32, 32'... first transistor, 16, 26, 36... second transistor,
17, 39, 39'...Diode, 38, 38'...
····resistance. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
ゲートを持つ第１、第２のＰＮＰＮスイツチと、第１の
ＰＮＰＮスイツチのゲートと逆並列接続の一方の共通端
子との間に設けた第１のトランジスタと、第２のＰＮＰ
Ｎスイツチのゲートと逆並列接続の他方の共通端子との
間に設けた第２のトランジスタと、該第１、第２のトラ
ンジスタのベース間に設けられてなると共に、それ自身
のベースが、ＰＮ接合層を介して共通アノードゲートに
接続してなる第３のトランジスタと、より成る半導体ス
イツチ。1 first and second PNPN switches connected in anti-parallel to each other and having a common anode gate; a first PNPN switch provided between the gate of the first PNPN switch and one common terminal of the anti-parallel connection; transistor and second PNP
A second transistor is provided between the gate of the N switch and the other common terminal of the anti-parallel connection and the bases of the first and second transistors, and its own base is a PN a third transistor connected to a common anode gate through a bonding layer;
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12086179A JPS6040739B2 (en) | 1979-09-21 | 1979-09-21 | semiconductor switch |
| DE8080105547T DE3071552D1 (en) | 1979-09-21 | 1980-09-16 | Semiconductor switch |
| EP80105547A EP0027888B1 (en) | 1979-09-21 | 1980-09-16 | Semiconductor switch |
| US06/188,745 US4365170A (en) | 1979-09-21 | 1980-09-19 | Semiconductor switch |
| CA000360656A CA1149885A (en) | 1979-09-21 | 1980-09-19 | Semiconductor switch |
| AU62588/80A AU526957B2 (en) | 1979-09-21 | 1980-09-22 | Pnpn switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12086179A JPS6040739B2 (en) | 1979-09-21 | 1979-09-21 | semiconductor switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5646337A JPS5646337A (en) | 1981-04-27 |
| JPS6040739B2 true JPS6040739B2 (en) | 1985-09-12 |
Family
ID=14796759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12086179A Expired JPS6040739B2 (en) | 1979-09-21 | 1979-09-21 | semiconductor switch |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6040739B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0420558U (en) * | 1990-06-13 | 1992-02-20 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS605625A (en) * | 1983-06-24 | 1985-01-12 | Oki Electric Ind Co Ltd | Electronic switching circuit |
-
1979
- 1979-09-21 JP JP12086179A patent/JPS6040739B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0420558U (en) * | 1990-06-13 | 1992-02-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5646337A (en) | 1981-04-27 |
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