JPS6122867B2 - - Google Patents
Info
- Publication number
- JPS6122867B2 JPS6122867B2 JP53088979A JP8897978A JPS6122867B2 JP S6122867 B2 JPS6122867 B2 JP S6122867B2 JP 53088979 A JP53088979 A JP 53088979A JP 8897978 A JP8897978 A JP 8897978A JP S6122867 B2 JPS6122867 B2 JP S6122867B2
- Authority
- JP
- Japan
- Prior art keywords
- turn
- diode
- gate
- electrode
- type base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101100449816 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GTO1 gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/73—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
- H03K17/732—Measures for enabling turn-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
- Thyristor Switches And Gates (AREA)
Description
【発明の詳細な説明】
この発明は、ターンオン機能およびターンオフ
機能を有し、ターンオフ後いままで流していた電
流の向きとは逆向きに電流を流すことができる逆
導通ゲートターンオフサイリスタ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reverse conduction gate turn-off thyristor circuit that has a turn-on function and a turn-off function, and is capable of allowing current to flow in the opposite direction of the current flowing after being turned off.
ゲートターンオフサイリスタ(Cate Turn Off
Thyrister、以下G.T.Oと略称する)は、ゲート
ターンオフ機能を持つているということで、普通
のサイリスタよりもより完全なスイツチング素子
に近ずいたということができる。すなわち、G.
T.Oのゲートに正の電流を流すとターンオンし、
この後、負の電流を流すことによつてターンオフ
する。そしてG.T.Oは上記のような機能から、チ
ヨツパ回路あるはインバータ回路等に用いられる
ことが多い。またチヨツパ回路あるはインバータ
回路において、G.T.Oをターンオフした後はG.
T.Oにいままで流していた電流の向きとは逆向き
の電流を流すことが必要な場合が多い。このため
従来では第1図に示すようにG.T.O1のアノー
ド・カソード間に逆並列的にデイスクリートのダ
イオード2を接続した回路が用いられている。す
なわち、G.T.O1のターンオン後に、電流はG.
T.O1を介して流れ、ターンオフ後にはいきまま
で流れていた電流とは逆向きの電流がダイオード
2を介して流れるようになつている。しかしなが
ら上記ダイオード2の耐圧としては、G.T.O1の
アノード・カソード間に印加される電圧のピーク
電圧以上の耐圧が必要となる。例えば上記G.T.O
1をテレビ受像機の水平偏向回路に使用する場
合、上記ダイオード2はおおよそ1500Vの耐圧を
持つたものが必要となる。このようにダイオード
の耐圧が高いと必然的に価格も高くなるため、第
1図に示すような回路構成では価格的に不利であ
る。このためさらに従来では価格の低減化を計る
ため、G.T.Oとダイオードをモノリシツク化する
方法が考えられた。 Cate Turn Off Thyristor
Since the Thyrister (hereinafter abbreviated as GTO) has a gate turn-off function, it can be said that it is closer to a perfect switching element than an ordinary thyristor. That is, G.
When a positive current flows through the gate of TO, it turns on,
Thereafter, it is turned off by flowing a negative current. Because of the functions mentioned above, GTO is often used in chopper circuits, inverter circuits, etc. Also, in a chopper circuit or an inverter circuit, after turning off the GTO, the G.
It is often necessary to flow a current in the opposite direction to the current flowing through the TO. For this reason, conventionally, as shown in FIG. 1, a circuit is used in which a discrete diode 2 is connected in antiparallel between the anode and cathode of the GTO 1. That is, after GTO1 turns on, the current is G.
The current flows through T.O1, and after turn-off, a current flows through diode 2 in the opposite direction to the current that was flowing normally. However, the diode 2 needs to have a withstand voltage higher than the peak voltage of the voltage applied between the anode and cathode of the GTO 1. For example, the above GTO
When the diode 1 is used in a horizontal deflection circuit of a television receiver, the diode 2 needs to have a withstand voltage of approximately 1500V. If the breakdown voltage of the diode is high as described above, the price will inevitably be high, so the circuit configuration as shown in FIG. 1 is disadvantageous in terms of cost. For this reason, in the past, in order to further reduce the cost, a method was considered to make the GTO and diode monolithic.
第2図はG.T.Oとダイオードとをモノリシツク
化した従来の逆導通G.T.Oの素子構造を示す断面
図である。図において11はN型ベース領域で、
このN型ベース領域11の一方露出面にはP型ベ
ース領域12が形成されている。またこのP型ベ
ース領域12の表面領域の一部にはN型エミツタ
領域13が形成されている。前記N型ベース領域
11の他方露出面にはP型エミツタ領域14と
N+型領域15とが併設形成されている。そして
前記P型ベース領域12の表面の一部にはゲート
電極16が形成されていると共に、N型エミツタ
領域13の表面およびP型ベース領域12の表面
には両領域を接続するようにカソード電極17が
形成されている。また前記P型エミツタ領域14
の表面およびN+型領域15の表面には両領域を
接続するようにアノード電極18が形成されてい
る。上記のような素子は第2図に示すA−A′線
を中心にして、左側にはG.T.Oが右側にはダイオ
ードが形成された構成となつている。 FIG. 2 is a cross-sectional view showing the element structure of a conventional reverse conducting GTO in which a GTO and a diode are monolithically formed. In the figure, 11 is an N-type base region,
A P-type base region 12 is formed on one exposed surface of the N-type base region 11 . Further, an N-type emitter region 13 is formed in a part of the surface region of this P-type base region 12. A P-type emitter region 14 is provided on the other exposed surface of the N-type base region 11.
An N + type region 15 is also formed. A gate electrode 16 is formed on a part of the surface of the P-type base region 12, and a cathode electrode is formed on the surface of the N-type emitter region 13 and the surface of the P-type base region 12 so as to connect both regions. 17 is formed. In addition, the P-type emitter region 14
An anode electrode 18 is formed on the surface of the N + type region 15 and on the surface of the N + type region 15 so as to connect both regions. The above-mentioned element has a configuration in which a GTO is formed on the left side and a diode is formed on the right side, centered on the line A-A' shown in FIG.
ところで一般にG.T.Oではターンオフゲインを
大きくとるために、N型エミツタ領域13の幅W
を狭くするとともに、P型ベース領域12の厚み
Dを厚くする構造をとるようにしている。しかし
ながら、このような構造とすることにより、ゲー
ト電極16とカソード電極17とが低インピーダ
ンスのP型ベース領域で接続されることになり、
見掛け上のゲートターンオフ電流が増大し実質上
のターンオフゲインが低下してしまうといつた欠
点があつた。すなわち、カソード電極17とゲー
ト電極16との間にカソード電極17側が高電位
となるような電圧を印加してターンオフさせる場
合、カソード電極17とゲート電極16との間に
流れる電流はN形エミツタ領域13とP形ベース
領域12とからなるPN接合を介して流れ、ター
ンオフに寄与するもの以外に、P形ベース領域1
2のみを通つてゲート電極16に達する無駄な電
流も存在しており、この無駄な電流がターンオフ
ゲインを低下させる原因となつている。 By the way, in general, in order to obtain a large turn-off gain in a GTO, the width W of the N-type emitter region 13 is
The structure is such that the thickness D of the P-type base region 12 is increased. However, with such a structure, the gate electrode 16 and the cathode electrode 17 are connected through a low impedance P-type base region.
The disadvantage is that the apparent gate turn-off current increases and the actual turn-off gain decreases. That is, when turning off the cathode electrode 17 and the gate electrode 16 by applying a voltage such that the cathode electrode 17 side has a high potential, the current flowing between the cathode electrode 17 and the gate electrode 16 flows through the N-type emitter region. 13 and the P-type base region 12, and in addition to that which contributes to turn-off, the P-type base region 1
There is also a wasteful current that reaches the gate electrode 16 through only the gate electrode 2, and this wasteful current causes a decrease in the turn-off gain.
この発明は上記のような事情を考慮してなされ
たもので、その目的とするところはターンオフゲ
インが十分に高くしかも価格も低廉な逆導通ゲー
トターンオフサイリスタ回路を提供することにあ
る。 The present invention has been made in consideration of the above circumstances, and its purpose is to provide a reverse conduction gate turn-off thyristor circuit which has a sufficiently high turn-off gain and is inexpensive.
以下図面を参照してこの発明の一実施例を説明
する。第3図は、この発明の逆導通ゲートターン
オフサイリスタ回路(逆導通G.T.O回路)の一実
施例を一部断面にした断面図である。図において
21は不純物濃度が1014以下のN型ベース領域
で、このN型ベース領域21の一方露出面には不
純物濃度が1016程度のP型ベース領域22が形成
されている。またこのP型ベース領域22の表面
領域の一部には不純物濃度が1021程度のN型エミ
ツタ領域23が形成されている。前記N型ベース
領域21の他方露出面にはまた不純物濃度が1018
程度の複数のP型エミツタ領域24と複数のN+
型領域25とが併設されたシヨートエミツタ領域
26が形成されている。さらに前記P型ベース領
域22の表面にはゲート電極27が形成されてい
るとともに、前記N型エミツタ領域23の表面に
はカソード電極28が形成されている。また前記
シヨートエミツタ領域26の表面にはアノード電
極29が形成されている。すなわち、上記素子は
基本的にはPNPN接合を持つサイリスタであり、
このサイリスタはゲートターンオフ機能を有する
G.T.O30となつている。そしてまた上記G.T.O
のゲート電極27とカソード電極28との間に
は、そのカソードをゲート電極27側に向けたダ
イオード31が接続されている。したがつて上記
回路をシンボル化すると第4図のようになる。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a partially sectional view of an embodiment of the reverse conduction gate turn-off thyristor circuit (reverse conduction GTO circuit) of the present invention. In the figure, reference numeral 21 denotes an N-type base region with an impurity concentration of 10 14 or less, and a P-type base region 22 with an impurity concentration of about 10 16 is formed on one exposed surface of the N-type base region 21 . Further, in a part of the surface region of this P type base region 22, an N type emitter region 23 having an impurity concentration of about 10 21 is formed. The other exposed surface of the N-type base region 21 also has an impurity concentration of 10 18
A plurality of P-type emitter regions 24 and a plurality of N +
Short emitter area with mold area 25
26 is formed. Furthermore, a gate electrode 27 is formed on the surface of the P-type base region 22, and a cathode electrode 28 is formed on the surface of the N-type emitter region 23. Further, an anode electrode 29 is formed on the surface of the short emitter region 26 . In other words, the above element is basically a thyristor with a PNPN junction,
This thyristor has gate turn-off function
It is called GTO 30 . And also the above GTO
A diode 31 with its cathode facing the gate electrode 27 is connected between the gate electrode 27 and the cathode electrode 28 . Therefore, when the above circuit is symbolized, it becomes as shown in FIG.
次に上記のように構成された素子の作用につい
て説明する。先ずG.T.O30をターンオフさせる
場合には、カソード電極28に対してアノード電
極29が正となるように電圧を与え、しかる後カ
ソード電極28に対して正の電圧をゲート電極2
7に与えることにより行なわれる。ターンオフ後
はアノード電極29〜P型エミツタ領域24,2
4,……〜N型ベース領域21〜P型ベース領域
22〜N型エミツタ領域23〜カソード電極28
の経路で電流が流れることになる。次にターンオ
フさせる場合には、カソード電極28に対して負
の電圧をゲート電極27に与える。いまアノード
電極29とカソード電極28との間に電流が流れ
ていなければ、ゲート電極27に負の電圧を与え
るとゲート電極27とカソード電極28との間、
すなわちP型ベース領域22とN型エミツタ領域
23のPN接合は逆バイアス状態となり、この間
にはほとんど電流は流れずダイオード31を介し
て流れることになる。しかしながらいままでこの
PN接合には順方向電流が流れているので、ゲー
ト電極27に負の電圧を与えた後に、P型ベース
領域22とN型エミツタ領域23とのPN接合の
逆方向インピーダンスの値は、ゲート電極27と
カソード電極28との間に接続されているダイオ
ード31の順方向インピーダンスの値と同等かあ
るいは小さくなる。この結果ゲート電極27から
カソード電極28に向つて電流が流れ、この後
G.T.Oはターンオフする。 Next, the operation of the element configured as described above will be explained. First, when turning off the GTO 30 , a voltage is applied to the cathode electrode 28 so that the anode electrode 29 becomes positive, and then a positive voltage is applied to the cathode electrode 28 to the gate electrode 2.
This is done by giving 7. After turn-off, the anode electrode 29 to P-type emitter region 24, 2
4, ... ~N type base region 21 ~P type base region 22 ~N type emitter region 23 ~cathode electrode 28
Current will flow along this path. Next, when turning off, a negative voltage with respect to the cathode electrode 28 is applied to the gate electrode 27. If no current is flowing between the anode electrode 29 and the cathode electrode 28, when a negative voltage is applied to the gate electrode 27, between the gate electrode 27 and the cathode electrode 28,
That is, the PN junction between the P-type base region 22 and the N-type emitter region 23 is in a reverse bias state, and almost no current flows therebetween, but instead flows through the diode 31. However, until now this
Since a forward current flows through the PN junction, after applying a negative voltage to the gate electrode 27, the value of the reverse impedance of the PN junction between the P-type base region 22 and the N-type emitter region 23 is equal to that of the gate electrode. The forward impedance value of the diode 31 connected between the cathode electrode 27 and the cathode electrode 28 is equal to or smaller than that of the diode 31 . As a result, a current flows from the gate electrode 27 to the cathode electrode 28, and then
GTO turns off.
その後、今度はカソード電極28が正、アノー
ド電極29が負となるような電圧がG.T.Oに与え
られる。このときカソード電極28〜ダイオード
31〜ゲート電極27〜P型ベース領域22〜N
型ベース領域21〜N+型領域25,25,……
〜アノード電極29の経路で電流が流れることに
なる。すなわち、このように上記回路は逆導通
G.T.Oと同様の作用を行なうことになる。しかも
上記ダイオード31に印加される逆電圧は、G.
T.O30のゲート、カソード間順方向電圧以上あ
れば良いので低いものとなり、このダイオード3
1として小型でしかも安価なものを用いることが
できる。ここでダイオード31の順方向インピー
ダンスがG.T.O30のゲート、カソード間インピ
ーダンスよりも十分大きくされていれば、ターン
オフ時にダイオード31に流れる電流の値はP型
ベース領域22とN型エミツタ領域23からなる
PN接合に流れる電流に比較して十分に小さなも
のとなる。従つてターンオフ時、カソード電極2
8とゲート電極27との間に流れる電流のほとん
どがターンオフに寄与する電流となるのでターン
オフゲインも十分に高いものとなる。またダイオ
ード31の順方向インピーダンスがターンオフゲ
インに悪影響をおよぼす場合には、このダイオー
ド30と直列的に他のダイオードを接続するかあ
るいはインピーダンス素子例えば抵抗を挿入する
ようにしても良い。 Thereafter, a voltage is applied to the GTO such that the cathode electrode 28 is positive and the anode electrode 29 is negative. At this time, cathode electrode 28 - diode 31 - gate electrode 27 - P type base region 22 - N
Type base area 21 to N + type area 25, 25,...
~A current will flow through the path of the anode electrode 29. In other words, the above circuit is reverse conducting in this way.
It will perform the same action as GTO. Moreover, the reverse voltage applied to the diode 31 is G.
The forward voltage between the gate and cathode of TO 30 is sufficient, so it is low.
1, a small and inexpensive one can be used. Here, if the forward impedance of the diode 31 is made sufficiently larger than the impedance between the gate and cathode of the GTO 30, the value of the current flowing through the diode 31 at turn-off is determined by the P-type base region 22 and the N-type emitter region 23.
The current is sufficiently small compared to the current flowing through the PN junction. Therefore, at turn-off, the cathode electrode 2
Since most of the current flowing between the gate electrode 8 and the gate electrode 27 contributes to turn-off, the turn-off gain is also sufficiently high. If the forward impedance of the diode 31 adversely affects the turn-off gain, another diode may be connected in series with the diode 30, or an impedance element such as a resistor may be inserted.
また、上記ダイオード31はゲート、カソード
間に接続されているので、このダイオード31と
して前記第1図の従来回路のダイオード2のよう
な高耐圧のものは必要ではなく、従つて回路全体
の価格も低廉にできる。 Furthermore, since the diode 31 is connected between the gate and the cathode, it is not necessary to use a high voltage diode 31 like the diode 2 of the conventional circuit shown in FIG. 1, and the cost of the entire circuit is also reduced. It can be done inexpensively.
以上説明したように、この発明によればアノー
ド側のP型エミツタ領域をシヨートエミツタ構造
としたゲートターンオフサイリスタのゲート・カ
ソード間に、ゲート側がカソードとなるようにダ
イオードを接続したことにより、ターンオフゲイ
ンが十分に高くしかも価格も低廉な逆導通ゲート
ターンオフサイリスタ回路を提供することができ
る。 As explained above, according to the present invention, the turn-off gain is increased by connecting a diode between the gate and cathode of a gate turn-off thyristor in which the P-type emitter region on the anode side has a short emitter structure, with the gate side serving as the cathode. It is possible to provide a reverse conduction gate turn-off thyristor circuit that is sufficiently expensive and inexpensive.
第1図は従来の逆導通型ゲートターンオフサイ
リスタ回路の構成図、第2図は従来の逆導通ゲー
トターンオフサイリスタの素子構造を示す断面
図、第3図はこの発明の一実施例を示す断面図、
第4図は上記実施例回路をシンボル化した図であ
る。
21……N型ベース領域、22……P型ベース
領域、23……N型エミツタ領域、24……P型
エミツタ領域、25……N+型領域、26……シ
ヨートエミツタ領域、27……ゲート電極、28
……カソード電極、29……アノード電極、30
……ゲートターンオフサイリスタ、31……ダイ
オード。
Fig. 1 is a block diagram of a conventional reverse conduction type gate turn-off thyristor circuit, Fig. 2 is a sectional view showing the element structure of a conventional reverse conduction gate turn-off thyristor, and Fig. 3 is a sectional view showing an embodiment of the present invention. ,
FIG. 4 is a symbolic diagram of the circuit of the above embodiment. 21... N type base region, 22... P type base region, 23... N type emitter region, 24... P type emitter region, 25... N + type region, 26 ... short emitter region, 27... gate electrode, 28
... Cathode electrode, 29 ... Anode electrode, 30
...gate turn-off thyristor, 31...diode.
Claims (1)
極が設けられ、アノード側のP型エミツタ領域を
シヨートエミツタ構造としたゲートターンオフサ
イリスタと、このゲートターンオフサイリスタの
ゲートおよびカソード電極間にゲート電極側がカ
ソードとなるように外付けされ、順方向インピー
ダンスが上記ゲートターンオフサイリスタのカソ
ードおよびゲート電極間のインピーダンス以上に
されたダイオードとを具備したことを特徴とする
逆導通ゲートターンオフサイリスタ回路。1 A gate turn-off thyristor is provided with an anode electrode, a cathode electrode, and a gate electrode, and the P-type emitter region on the anode side has a short emitter structure. 1. A reverse conducting gate turn-off thyristor circuit comprising: a diode having a forward impedance greater than the impedance between the cathode and gate electrode of the gate turn-off thyristor.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8897978A JPS5516541A (en) | 1978-07-21 | 1978-07-21 | Reverse-conducting gate turn-off thyristor circuit |
GB7920106A GB2030796B (en) | 1978-07-21 | 1979-06-08 | Thyristor circuit |
DE19792927709 DE2927709C2 (en) | 1978-07-21 | 1979-07-09 | Reverse-conducting switchable thyristor triode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8897978A JPS5516541A (en) | 1978-07-21 | 1978-07-21 | Reverse-conducting gate turn-off thyristor circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5516541A JPS5516541A (en) | 1980-02-05 |
JPS6122867B2 true JPS6122867B2 (en) | 1986-06-03 |
Family
ID=13957911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8897978A Granted JPS5516541A (en) | 1978-07-21 | 1978-07-21 | Reverse-conducting gate turn-off thyristor circuit |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS5516541A (en) |
DE (1) | DE2927709C2 (en) |
GB (1) | GB2030796B (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH668505A5 (en) * | 1985-03-20 | 1988-12-30 | Bbc Brown Boveri & Cie | SEMICONDUCTOR COMPONENT. |
EP0337193A1 (en) * | 1988-04-11 | 1989-10-18 | Siemens Aktiengesellschaft | Protection circuit for a gate turn off thyristor |
DE4218398A1 (en) * | 1992-06-04 | 1993-12-09 | Asea Brown Boveri | High current pulse thyristor with two opposite semiconductor main faces - has GTO structure with highly doped emitter distributed over first face in form of narrow cathode fingers |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5019437B1 (en) * | 1970-06-08 | 1975-07-07 |
-
1978
- 1978-07-21 JP JP8897978A patent/JPS5516541A/en active Granted
-
1979
- 1979-06-08 GB GB7920106A patent/GB2030796B/en not_active Expired
- 1979-07-09 DE DE19792927709 patent/DE2927709C2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB2030796B (en) | 1983-01-19 |
DE2927709A1 (en) | 1980-02-07 |
JPS5516541A (en) | 1980-02-05 |
GB2030796A (en) | 1980-04-10 |
DE2927709C2 (en) | 1984-04-05 |
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