JPS6040187B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS6040187B2
JPS6040187B2 JP55179817A JP17981780A JPS6040187B2 JP S6040187 B2 JPS6040187 B2 JP S6040187B2 JP 55179817 A JP55179817 A JP 55179817A JP 17981780 A JP17981780 A JP 17981780A JP S6040187 B2 JPS6040187 B2 JP S6040187B2
Authority
JP
Japan
Prior art keywords
chip
block
semiconductor chip
manufacturing
metal block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55179817A
Other languages
Japanese (ja)
Other versions
JPS57104230A (en
Inventor
義昭 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55179817A priority Critical patent/JPS6040187B2/en
Publication of JPS57104230A publication Critical patent/JPS57104230A/en
Publication of JPS6040187B2 publication Critical patent/JPS6040187B2/en
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明はパワートランジスタの如き半導体装置における
放熱基板に金属ブロックを付加してパワーの増加を可能
とした半導体装置とその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device such as a power transistor in which power can be increased by adding a metal block to a heat dissipating substrate, and a method for manufacturing the same.

パワートランジスタの製作にあたっては、第１図に示さ
れる様に、ニッケルめつきした鋼の放熱基板１に半導体
チップ２を麹材３により固着する場合、コレット４にて
、当初半導体チップ２の端部を保持し、鍵付け温度に加
熱している間に、コレット４を前後および左右にスクラ
ブ（揺動）し溶着を行なっている。又、鍵材の広がり向
上のためフラックスを使用する。外装にはモールドが一
般に使用されている。ここで、新品種、改良等によりパ
ワーの増加が必要であるが、同一外形を使用する場合に
は、チップサイズを大きくするか、又は同一チップサイ
ズを使用する場合は、外形自体大きなものとする以外に
方法はなく、両者ともコスト高となっていた。When manufacturing a power transistor, as shown in FIG. 1, when a semiconductor chip 2 is fixed to a heat dissipating substrate 1 made of nickel-plated steel using a koji material 3, the ends of the semiconductor chip 2 are initially fixed with a collet 4. While the collet 4 is held and heated to the locking temperature, the collet 4 is scrubbed (swung) back and forth and left and right to perform welding. Additionally, flux is used to improve the spread of the key material. Molds are generally used for the exterior. Here, it is necessary to increase the power due to new products, improvements, etc., but if the same external shape is used, the chip size should be increased, or if the same chip size is used, the external size itself should be increased. There was no other way, and both methods were expensive.

尚、前記の方法では、次の諸点も問題として生じてし、
た。In addition, the following problems arise with the above method:
Ta.

【１１ スクラブに際し、チップはコレツトにより保持
されているから、コレットにあたるチップ端部の欠け、
ひび割れ等が生ずる。[11 During scrubbing, the chip is held by the collet, so the end of the chip that corresponds to the collet may be chipped,
Cracks, etc. will occur.

‘２１ フラツクスを使用した場合、コレットとチップ
端よりフラックスのはい上り、および余剰鍵材のはし、
上りがあり、その除去工数および不良が注視されていた
。'21 When flux is used, the flux may creep up from the collet and tip ends, and the edges of excess key material may
There was an upsurge, and the number of man-hours required to remove it and defects were closely monitored.

｛３１ 蝋材は加熱中に表面張力により丸くなる現象が
あり、鍵材厚さを１０ミクロン程度にするには、コレッ
トにて押圧する必要がある。{31 Wax material tends to become round due to surface tension during heating, and in order to make the key material thickness about 10 microns, it is necessary to press it with a collet.

コレットの平行度、磨耗によるくるし、等により鋼材厚
さのばらつきを生じ、又、チップの傾きを生じ特性（熱
抵抗等）がばらつく結果、装置の信頼性が低下する。本
発明は上記の問題点に鑑み、従前と同一の外形のままで
もパワー増加が図れる半導体装置を提供せんとするもの
であり、また、上記の諸問題を伴わない半導体装置の製
造方法を提供せんとするものである。Variations in the thickness of the steel material occur due to the parallelism of the collet, curling due to wear, etc., and the inclination of the chip causes variations in characteristics (thermal resistance, etc.), resulting in a decrease in the reliability of the device. In view of the above-mentioned problems, the present invention aims to provide a semiconductor device that can increase the power while keeping the same external shape as before, and also provides a method for manufacturing a semiconductor device that does not involve the above-mentioned problems. That is.

これらの目的は本発明によれば、放熱基板に半導体チッ
プを鍵付けした半導体装置において、該半導体チップの
周辺に近接して、半導体チップより肉厚の金属ブロック
を該放熱基板に該半導体チップを固着する鋼材と同じ鍵
材でことを特徴とする半導体装置とすることにより達成
される。According to the present invention, in a semiconductor device in which a semiconductor chip is locked to a heat dissipation board, a metal block thicker than the semiconductor chip is attached to the heat dissipation board in close proximity to the periphery of the semiconductor chip. This is achieved by making the semiconductor device characterized by using the same key material as the steel material to which it is fixed.

また、放熱基板に鍵材を塗布し、半導体チップおよび該
半導体チップの周辺に近接して、半導体チップより肉厚
の金属ブロックを該鍵村上に載直し、鍵付け温度に加熱
中該金属ブロックを揺動させることにより半導体チップ
を移動させて磯付けすることを特徴とする半導体装置の
製造方法によって達成される。以下、本発明を図面に示
した実施例により説明する。In addition, a keying material is applied to the heat dissipation board, and a metal block thicker than the semiconductor chip is remounted on the key board near the semiconductor chip and the periphery of the semiconductor chip, and the metal block is heated to the keying temperature. This is achieved by a method for manufacturing a semiconductor device, which is characterized in that the semiconductor chip is moved and bonded by rocking. The present invention will be explained below with reference to embodiments shown in the drawings.

第２図は本発明の実施例になるパワートランジスタの斜
視図であって、放熱基板１は、ＴＯ−２２０なる外形に
あっては、幅が１２肌、長さ１６凧、厚さ１．２脚で、
通常ニッケルめつきした鋼板である。FIG. 2 is a perspective view of a power transistor according to an embodiment of the present invention, and the heat dissipation board 1 has a TO-220 external shape with a width of 12 mm, a length of 16 mm, and a thickness of 1.2 mm. with legs,
It is usually a nickel-plated steel plate.

この放熱基板１にトランジスタチップ２が半田付けされ
ており、その上面にあるェミツ夕およびベース電極は、
アルミニウム紬線５により、それぞれ、外部リード線６
，７に接続されている。本発明により、放熱基板全体の
熱容量を増大させる金属ブロック８がチップ２の周囲に
近接して同じく半田付けにより固着されている。この金
属フロック８は放熱性の良い材料とし、例えば銅、鉄、
アルミニウム等から選択し得るが、ここでは基板１と同
じ鋼を用い、その厚さは０．８肋とした。外装は従来と
同じェポキシ樹脂９であって、モールド外形を点線にて
表示した。第２図のパワートランジスタの製法につき、
第３図を参照して説明する。A transistor chip 2 is soldered to this heat dissipation board 1, and the emitter and base electrode on its upper surface are
External lead wires 6 are connected by aluminum pongee wires 5, respectively.
, 7. According to the present invention, a metal block 8 that increases the heat capacity of the entire heat dissipation board is fixed close to the periphery of the chip 2 by soldering as well. This metal flock 8 is made of a material with good heat dissipation, such as copper, iron,
Although it may be selected from aluminum or the like, the same steel as the substrate 1 was used here, and its thickness was set to 0.8 ribs. The exterior is made of the same epoxy resin 9 as the conventional one, and the outer shape of the mold is shown with dotted lines. Regarding the manufacturing method of the power transistor shown in Figure 2,
This will be explained with reference to FIG.

放熱基板１上に、クリーム半田３を塗布する。Cream solder 3 is applied on the heat dissipation board 1.

このクリーム半田は米国マルチコア社で製作されている
もので、１８０００から３００００までの用途に応じた
ものが提供されている。クリーム半田を所定温度に加熱
中に、ェァ・ピンセットにてトランジスタチップ２を保
持してクリーム半田上に載せる。また、金属ブロック８
を載直する。この順序は逆でも良い。この状態で、ブロ
ック８の端にあたる広幅のコレット４にてスクラブを行
なうと、半田３の余剰分はブロック８の下にまわり込み
、チップ２の下には接着に必要な最小限の１０ミクロン
の厚さとなり、鋼材厚が薄くて、且つ安定した磯付けが
できる。This cream solder is manufactured by Multicore Co., Ltd. in the United States, and is available in sizes ranging from 18,000 to 30,000 depending on the application. While the cream solder is being heated to a predetermined temperature, the transistor chip 2 is held with air tweezers and placed on the cream solder. Also, metal block 8
Repost. This order may be reversed. In this state, when scrubbing is performed using the wide collet 4 at the end of the block 8, the excess solder 3 wraps around the bottom of the block 8, and the minimum 10 micron thickness necessary for adhesion is placed under the chip 2. The thickness of the steel material is thin, and stable anchoring is possible.

既述の通り半田付けの際、半田は表面張力によって丸く
なる現象があり、この上にチップを載せても、チップと
放熱基板とは平行とならないが、ブロック８を使用する
と、チップを浮上させているチップ周辺の半田は、第３
図に図示した通りブロック８の下にまわり込む結果、チ
ップ２は半田３で浮き上ることはなく、チップ２への押
圧をせずとも、技少限半田厚さの１０ミクロンを実現で
きる利点がある。尚、上記ブロック８のスクラブ工程で
、ブロック８の内壁面にはチップ２の左右端が接触し、
同じくスクラブされる。As mentioned above, when soldering, there is a phenomenon in which the solder becomes rounded due to surface tension, and even if a chip is placed on top of this, the chip and the heat dissipation board will not be parallel to each other. However, if block 8 is used, the chip will float and become round. The solder around the chip that is
As shown in the figure, as a result of going under the block 8, the chip 2 is not lifted up by the solder 3, and there is an advantage that a solder thickness of 10 microns, which is the technical limit, can be achieved without pressing the chip 2. be. In addition, in the scrubbing process of the block 8, the left and right ends of the chip 2 come into contact with the inner wall surface of the block 8,
Also scrubbed.

半田の広がりを良くするため、上記のクＩＪーム半田に
はフラツクスが入っているが、ブロック８がリング状ま
たは多角形状であると、ブロック８とチップ２の接触は
、チップの角のみとなり、フラツクス等のはし、上りを
最も抑えられるものであるが、ブロック８がチップ２と
同一の形状（短形）であっても、肉厚となっているので
実際上、スクラブ工程で、チップとブ。To improve the spread of the solder, flux is contained in the above-mentioned IJ solder, but if the block 8 is ring-shaped or polygonal, the contact between the block 8 and the chip 2 will be only at the corners of the chip. However, even if block 8 has the same shape as chip 2 (rectangular shape), it is thicker, so in practice, it is difficult to prevent the chip from rising during the scrubbing process. And bu.

ックの接触面で半田がはし、上ることはない。チップ２
とブロック８の半田付けが終了した後は、チップ上のェ
ミッタ、ベース電極と、外部リード線とをアルミニウム
細線で接続し、ェポキシ樹脂にて外装する。The solder will bleed on the contact surface of the hook and will not rise. Chip 2
After completing the soldering of the block 8 and the block 8, the emitter and base electrodes on the chip and the external lead wires are connected with thin aluminum wires and covered with epoxy resin.

この様にして、ＴＯ−２２の外形をもつパワートランジ
スタを製作し、パワー増加を測定した結果、同一種のチ
ップで２０〜３０％の増加が得られた。In this manner, a power transistor having a TO-22 external shape was fabricated, and the power increase was measured. As a result, an increase in power of 20 to 30% was obtained with the same type of chip.

上記の実施例は、一般的なＴＯ−２２０外形寸法のもの
を用いて製作したが、本発明は放熱基板が特に厚い（２
脚）ものに適用しても効果が著しいことを確認した。The above embodiment was manufactured using a general TO-220 with external dimensions, but in the present invention, the heat dissipation board is particularly thick (220 mm).
It was confirmed that the effect was remarkable even when applied to the legs).

比較のため、次の５つのサンプルを試作した。（１｝
標準として、ニッケルめつきした鋼の放熱基板１にクリ
ーム半田にてトランジスタチップを固着し、ェポキシ樹
脂にて外装した。For comparison, the following five samples were produced. (1}
As a standard, a transistor chip was fixed to a heat dissipation board 1 made of nickel-plated steel using cream solder, and then covered with epoxy resin.

■‘１｝のヱポキシ樹脂に代えて、高熱伝導性樹脂（ェ
ポキシの３倍の熱伝導率）にて外装した。■Instead of the epoxy resin in '1}, it was covered with a highly thermally conductive resin (3 times the thermal conductivity of epoxy).

（３’サンプル１においてシリコーンコーテインク１１
を行なわず、直接高熱伝導性樹脂（ェポキシの約３の音
の熱伝導率）をコーティングした。外装は同じくエポキ
シである。（４｝ サンプル１において、２側のェポキ
シを介してチップ上に放熱板をとりつけ、両面ヒートシ
ンク構造とした。(3' In sample 1, silicone coating ink 11
Instead, it was directly coated with a high thermal conductive resin (thermal conductivity about 3 times that of epoxy). The exterior is also epoxy. (4) In sample 1, a heat sink was attached to the chip via epoxy on the 2 side to create a double-sided heat sink structure.

脚 本発明により放熱板に、チップと金属ブロック（厚
さ２肌の銅ブロック）を同時に半田付けし、ェポキシ樹
脂にて封止した。Legs According to the present invention, a chip and a metal block (a copper block with a thickness of two layers) were simultaneously soldered to a heat sink and sealed with epoxy resin.

上記５つのサンプルを多数作成し、そのパワー増加率を
平均値で比較すると次の通りとなった。A large number of samples of the above five were prepared and the average power increase rates were compared as follows.

‘１’ 標準（平均出力 １１８．５Ｗ）‘２ｌ＋３％ ‘３｝十５％ ‘４｝ 十１０％ ‘５）十１５％ 上記の本発明実施例は、種々変更が可能であることは明
らかである。'1' Standard (average output 118.5W) '2l+3% '3} 15% '4} 10% '5) 15% It is clear that various changes can be made to the above embodiment of the present invention. be.

例えば第３図において、金属ブロック８はその下面が平
坦であるが、第４図に示す如く、鍵材溜１０を設けてお
くことにより鍵付けにおけるスクラブ工程で、余剰の磯
材を完全に吸い取ることができ、チップ下の鍵材厚さを
最少限とすることを保証する。又、金属ブロック８の外
形は、第２図では矩形状として示したが、第５図ａ乃至
ｅに示す形状とすることができる。For example, in FIG. 3, the metal block 8 has a flat bottom surface, but as shown in FIG. 4, by providing a key material reservoir 10, excess rock material can be completely absorbed during the scrubbing process during locking. This ensures that the thickness of the keying material under the chip is kept to a minimum. Further, although the outer shape of the metal block 8 is shown as a rectangular shape in FIG. 2, it may have the shape shown in FIGS. 5 a to 5 e.

スクラブ工程のため、第５図ｂ〜ｅの外形が特に適して
いる。もちろんスクラブはコレツトに依るばかりでなく
、ピンセットによるマニュアル操作でも実施可能である
。上述の様に、本発明によれば、チップの麹付けにあた
って、チップの近傍に放熱ブロックを同じく磯付けした
構造とすることにより、同一チップで同一外形寸法のパ
ッケージであっても２０〜３０％以上のパワー増加が可
能であり、新品種、改良にあたってコスト増を伴わずに
パワー増加が実現できる。For the scrubbing process, the contours of FIGS. 5b-e are particularly suitable. Of course, scrubbing can be performed not only by collection but also by manual operation using tweezers. As described above, according to the present invention, when molding a chip, by creating a structure in which a heat dissipation block is similarly attached to the vicinity of the chip, the cost reduction is reduced by 20 to 30% even for packages with the same chip and the same external dimensions. It is possible to increase the power by more than 100%, and it is possible to increase the power without increasing costs when creating new products or improving the product.

また、磯付けのスクラブに際しては、チップより肉厚の
外形も大なる金属ブロックをスクラブすれば足りるので
、作業は容易であり、チップの端部での欠け、ひび割れ
等の欠損は生じない。Furthermore, when scrubbing for rocking, it is sufficient to scrub a metal block that is thicker than the chip and has a larger outer diameter, so the work is easy and no defects such as chips or cracks occur at the end of the chip.

更に鋼材の余剰分は金属ブロックの麹材として働くため
、チップ下には接着に必要な最小限の錨しか残らず、従
って、チップへの押圧ないこ、放熱板と完全に平行度の
とれたチップ付けができ、鋼材厚さは安定し、特性（熱
抵抗）のバラッキ、信頼性の低下は起らない。更に、フ
ラックスを使用した場合でも、コレットとチップ機から
フラックスがはし、上ることもないし、余剰鍵材のはし
、上りもないから、その除去工程も不要であり、不良の
発生が抑えられる。Furthermore, since the excess steel material acts as a koji material for the metal block, only the minimum amount of anchor necessary for adhesion remains under the chip. Chips can be attached, the steel thickness is stable, and there is no variation in characteristics (thermal resistance) or deterioration of reliability. Furthermore, even when flux is used, the flux does not leak out from the collet and tipping machine, and there is no excess key material to remove or climb up, so there is no need to remove it, which reduces the occurrence of defects. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のパワートランジスタ製作におけるチッ
プの半田付け工程を示す断面面、第２図は、本発明実施
例になるパワートランジスタの斜視図、第３図は、第２
図のトランジスタ製作における半田付け工程を示す断面
図、第４図は、第３図における金属ブロックを改善した
断面図、第５図は、本発明にて使用できる金属ブロック
の形状を示す上面図である。 図中、１は放熱基板、２はトランジスタチップ、３は半
田、４はコレツト、８は金属ブロックを示す。 豹′図 第３図 災４図 弟ふ図 第２図FIG. 1 is a cross-sectional view showing the chip soldering process in conventional power transistor manufacturing, FIG. 2 is a perspective view of a power transistor according to an embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view showing the soldering process in manufacturing the transistor shown in FIG. 4. FIG. 4 is a cross-sectional view of an improved metal block in FIG. 3. FIG. be. In the figure, 1 is a heat sink, 2 is a transistor chip, 3 is solder, 4 is a collector, and 8 is a metal block. Leopard Figure 3 Figure 4 Younger Brother Figure 2

Claims (1)

【特許請求の範囲】[Claims] １ 放熱基板に鑞材を塗布し、半導体チツプ及び該半導
体チツプの周辺に近接して、半導体チツプより肉厚の金
属ブロツクを該鑞材上に載置し、鑞付け温度に加熱中該
金属ブロツクを揺動させることにより半導体チツプを移
動させて鑞付けすることを特徴とする半導体装置の製造
方法。1. Apply a solder material to a heat dissipation board, place a semiconductor chip and a metal block thicker than the semiconductor chip on the solder material close to the periphery of the semiconductor chip, and heat the metal block to the brazing temperature. 1. A method of manufacturing a semiconductor device, characterized in that a semiconductor chip is moved and soldered by swinging the semiconductor chip.
JP55179817A 1980-12-19 1980-12-19 Manufacturing method of semiconductor device Expired JPS6040187B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55179817A JPS6040187B2 (en) 1980-12-19 1980-12-19 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55179817A JPS6040187B2 (en) 1980-12-19 1980-12-19 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57104230A JPS57104230A (en) 1982-06-29
JPS6040187B2 true JPS6040187B2 (en) 1985-09-10

Family

ID=16072403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55179817A Expired JPS6040187B2 (en) 1980-12-19 1980-12-19 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6040187B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8929582B2 (en) 2010-08-16 2015-01-06 Bose Corporation Earpiece positioning and retaining
US9398364B2 (en) 2011-07-28 2016-07-19 Bose Corporation Earpiece passive noise attenuating

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8929582B2 (en) 2010-08-16 2015-01-06 Bose Corporation Earpiece positioning and retaining
US8989426B2 (en) 2010-08-16 2015-03-24 Bose Corporation Earpiece positioning and retaining
US9398364B2 (en) 2011-07-28 2016-07-19 Bose Corporation Earpiece passive noise attenuating

Also Published As

Publication number Publication date
JPS57104230A (en) 1982-06-29

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