JPH0444347A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0444347A
JPH0444347A JP2153183A JP15318390A JPH0444347A JP H0444347 A JPH0444347 A JP H0444347A JP 2153183 A JP2153183 A JP 2153183A JP 15318390 A JP15318390 A JP 15318390A JP H0444347 A JPH0444347 A JP H0444347A
Authority
JP
Japan
Prior art keywords
resin
semiconductor chip
lead
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2153183A
Other languages
Japanese (ja)
Other versions
JP2895920B2 (en
Inventor
Kunihiro Tsubosaki
邦宏 坪崎
Masahiro Ichitani
昌弘 一谷
Ichiro Anjo
安生　一郎
Taisei Jin
神　大成
Akihiko Iwatani
昭彦 岩谷
Hajime Murakami
元 村上
Masamichi Ishihara
政道 石原
Junichi Arita
順一 有田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2153183A priority Critical patent/JP2895920B2/en
Priority to KR1019910009519A priority patent/KR100212095B1/en
Publication of JPH0444347A publication Critical patent/JPH0444347A/en
Priority to US07/990,633 priority patent/US5583375A/en
Priority to US08/721,240 priority patent/US5714405A/en
Priority to US08/721,339 priority patent/US5869888A/en
Application granted granted Critical
Publication of JP2895920B2 publication Critical patent/JP2895920B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To store a large-sized semiconductor chip so as to make it into a superthin package by fixing a lead to the circuit formation face through an insulating adhesive layer, and sealing only the circuit formation face of a chip or the side with resin. CONSTITUTION:A lead 3 is fixed through an insulating adhesive film 2 to the circuit formation part of a semiconductor chip 1, and the lead 3 and the outer terminal of the chip 1 are bonded to each other by a fine metallic wire 5. The circuit formation face of the chip 1 is sealed by potting method with liquid-form resin 6 such as epoxy resin, or the like. Then, the outer lead of the lead 3 is bent. Since the sealing resin does not exist on the side of the chip 1, or, even if it exists, it is such a thin layer at the level that it flows during resin bonding, it can be made into a package approximately same in dimension as the chip 2, and since there is no resin on the rear of the chip 1, the thickness of the package can be made thin. Heat radiation efficiency can be improved by bonding a heat radiating fin 9 to the rear of the chip 1 with a thermally conductive adhesive 10.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、樹脂封止型半導装置に関し、特に、半導体チ
ップの回路形成面でリードと半導体チップの外部端子と
が電気的に接続され、樹脂で封止され序束文額宜続の封
止技術に適用して有効な技術に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a resin-encapsulated semiconductor device, and in particular, to a semiconductor device in which leads and external terminals of the semiconductor chip are electrically connected on the circuit forming surface of the semiconductor chip. The present invention relates to a technique that is effective when applied to a sealing technique for prefaces and frames that are sealed with resin.

〔従来の技術〕[Conventional technology]

従来、樹脂封止型で小型の半導装置の一つとして、例え
ば、特開昭６１−２１８１３９号公報に記載されるよう
に、半導体素子の回路形成面に絶縁フィルムを介して複
数本のインナーリードが固定され、金線によってワイヤ
ボンディングされ、レジンでモールドするＬＯＧ　（Ｌ
ｅａｄ　Ｏｎ　Ｃｈｉｐ）構造のものがある。Conventionally, as one of the small resin-sealed semiconductor devices, for example, as described in Japanese Patent Application Laid-Open No. 61-218139, a plurality of inner wires are attached to the circuit forming surface of a semiconductor element via an insulating film. LOG (L
There are some with an head-on-chip structure.

また、特開平１−２１７９３３号公報に記載されるよう
に、デバイスホール内にフィンガ状のリートを突出させ
、このリートの先端部に半導体チップをフェイスアップ
で位置合せしてボンディングし、レジン等の樹脂でモー
ルドし、アウターリートがテープの端縁から突出しない
ように当該テープキャリアに枠部材を取り付けるかある
いは当該アウターリードを枠部材の裏面にまで折り曲げ
るようにしたＴ　Ａ　Ｂ　（Ｔ　ａｐｅ　Ａ　ｕｔｏｍ
ａｔｅｄ　Ｂ　ｏｎｄｉｎｇ）方式がある。Furthermore, as described in Japanese Patent Application Laid-Open No. 1-217933, a finger-shaped reat is protruded into the device hole, and a semiconductor chip is aligned face-up and bonded to the tip of the reet, and then a resin or the like is applied. A T A B (T ape automatic) molded with resin, and a frame member is attached to the tape carrier so that the outer lead does not protrude from the edge of the tape, or the outer lead is bent to the back side of the frame member.
There is a rated B onding method.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、本発明者は、前記従来のＬＯＧ構造の半
導体装置及びＴＡＢ方式の半導体装置を検討した結果、
次の問題点を見い出した。However, as a result of studying the conventional LOG structure semiconductor device and the TAB type semiconductor device, the present inventor found that
I found the following problem.

前記ＬＯＣ構造の半導体装置では、半導体チップの周囲
を、例えばトランスファモールド法により封止した構造
になっているため、一定寸法のパッケージ外形に対して
収納可能な半導体チップサイズは小さく、パッケージの
厚さも１ｍｍ程度が限度であり、また、半導体チップ内
で発生した熱の放散がよくない。In the semiconductor device with the LOC structure, the periphery of the semiconductor chip is sealed by, for example, a transfer molding method. Therefore, the size of the semiconductor chip that can be accommodated is small for a package external shape of a certain size, and the thickness of the package is also small. The limit is about 1 mm, and the heat generated within the semiconductor chip is not well dissipated.

また、ＴＡＢ方式では、半導体チップの外部端子（電極
）が特殊なものでありコストが高くなる。Furthermore, in the TAB method, the external terminals (electrodes) of the semiconductor chip are special, which increases the cost.

また、インナーリードが半導体チップに直接固定されて
いないので機械的強度が小さく、温度ストレスで発生す
る熱応力に対して信頼性が低下する。Furthermore, since the inner leads are not directly fixed to the semiconductor chip, their mechanical strength is low, and reliability is reduced against thermal stress caused by temperature stress.

また、ポリイシドフィルムにエツチング技術でリードを
形成するためにコストが高くなる。Furthermore, since the leads are formed on the polyamide film using an etching technique, the cost becomes high.

本発明の課題は、大型半導体チップを収納することがで
き、かつ超薄型のパッケージを得ることが可能な技術を
提供することにある。An object of the present invention is to provide a technique that can accommodate a large semiconductor chip and that can obtain an ultra-thin package.

本発明の他の課題は、半導体チップ内で発生する熱の放
散を効率よく行うことが可能な技術を提供することにあ
る。Another object of the present invention is to provide a technique that can efficiently dissipate heat generated within a semiconductor chip.

本発明の他の課題は、パッケージを基板にはんだ実装し
た状態で、温度ストレスによる熱応力を緩和させること
が可能な小型の超薄型半導体装置を提供することにある
。Another object of the present invention is to provide a small, ultra-thin semiconductor device that can alleviate thermal stress caused by temperature stress while a package is soldered onto a substrate.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

（１）半導体チップの回路形成面でリードと半導体チッ
プの外部端子とが電気的に接続され、樹脂で封止された
半導体装置において、前記リードが絶縁性の接着層を介
在して前記半導体回路化成面に固定さｔ、かつ前記半導
体チップの回路形成面部又は回路形成面部と側面部のみ
が樹脂で封止されているものである。(1) In a semiconductor device in which leads and external terminals of the semiconductor chip are electrically connected on the circuit formation surface of the semiconductor chip and sealed with resin, the leads are connected to the semiconductor circuit through an insulating adhesive layer. The semiconductor chip is fixed to a chemically formed surface, and only the circuit forming surface portion or the circuit forming surface portion and side portions of the semiconductor chip are sealed with resin.

（２）前記リートのアウターリート部が面実装で薄型化
に適切な形状になっている。(2) The outer reel portion of the reet has a shape suitable for surface mounting and thinning.

（３）前記リートのアウターリードが熱応力緩和形状に
構成されている。(3) The outer lead of the lead is configured to have a thermal stress relaxing shape.

（４）前記リートと半導体チップの外部端子との電気的
接続は、金属ワイヤまたは金属バンプ又は金属ボールに
よってなされている。(4) Electrical connection between the REIT and external terminals of the semiconductor chip is made by metal wires, metal bumps, or metal balls.

〔作　　用〕[For production]

前述した手段（１）によれば、半導体チップの回路形成
面部又は回路形成面部と側面部のみが樹脂で封止されて
いるので、パッケージを半導体チップのほぼ同一程度の
寸法の大きさにすることができる。また、半導体チップ
の回路形成面部と反対側の面が露出しているので、放熱
効率を向上することができる。また、リートが絶縁接着
層によって半導体チップの回路形成面に固定されている
ため、リートの機械的強度が大きく、機械的ストレス及
び熱ストレスに対して信頼性か高い。According to the above-mentioned means (1), since only the circuit forming surface of the semiconductor chip or the circuit forming surface and the side surfaces are sealed with resin, the package can be made to have almost the same size as the semiconductor chip. I can do it. Furthermore, since the surface of the semiconductor chip opposite to the circuit forming surface portion is exposed, heat dissipation efficiency can be improved. Furthermore, since the REIT is fixed to the circuit formation surface of the semiconductor chip by the insulating adhesive layer, the REIT has high mechanical strength and is highly reliable against mechanical stress and thermal stress.

手段（２）によれば、リートのアウターリード部が面実
装で薄型化に適切な形状になっているので、超薄型パッ
ケージすることができる。According to means (2), since the outer lead portion of the REIT has a shape suitable for surface mounting and thinning, an ultra-thin package can be achieved.

手段（３）によれば、リートのアウターリードが熱応力
緩和形状に構成されているので、半導体装置を基板には
んだ実装する時における熱応力を緩和させることができ
、かつ、半導体装置が基板に実装された状態で、温度ス
トレスによる熱応力を緩和させることができる。According to means (3), since the outer leads of the REIT are configured to have a thermal stress relaxing shape, it is possible to alleviate thermal stress when the semiconductor device is soldered onto the board, and the semiconductor device is not attached to the board. Thermal stress caused by temperature stress can be alleviated in the mounted state.

手段（４）によれば、リートと半導体チップの外部端子
との電気的接続は、ワイヤと金属ボールによってなされ
ているので、プレス又はエツチング法で作成される通常
のリードフレームが使用でき、コストを低減することが
できる。According to means (4), the electrical connection between the REIT and the external terminals of the semiconductor chip is made by wires and metal balls, so a normal lead frame made by pressing or etching can be used, reducing costs. can be reduced.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面を用いて具体的に説明す
る。Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

なお、実施例を説明するための全図において、同一機能
を有するものは、同一符号を付け、その繰り返しの説明
は省略する。In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔実施例１〕 第１図は、本発明の実施例１の小型の樹脂封止型半導体
装置の全体構成を示す斜視図、第２図は、第１図に示す
Ａ−Ａ線で切った要部断面図である。[Example 1] Fig. 1 is a perspective view showing the overall configuration of a small resin-sealed semiconductor device according to Example 1 of the present invention, and Fig. 2 is a perspective view taken along line A-A shown in Fig. 1. It is a sectional view of the main part.

第１図及び第２図に示すように、本実施例１の小型の樹
脂封止型半導体装置２０は、半導体チップ１の回路形成
面に絶縁性接着フィルム２を介在してリード３が固定さ
れ、該リード３と半導体チップ１の外部端子（アルミ電
極）４とが金線等の金属細線５でワイヤボンディングさ
れ、電気的に接続されている。そして、前記半導体チッ
プ１の回路形成面部は、エポキシ樹脂等からなる液状レ
ジン６でボッティング法によって封止される。その後、
リード３のアウターリードを第１図のように折り曲げて
、小型の樹脂封止型半導体装置が完成される。As shown in FIGS. 1 and 2, the small resin-sealed semiconductor device 20 of Example 1 has leads 3 fixed to the circuit forming surface of a semiconductor chip 1 with an insulating adhesive film 2 interposed therebetween. The leads 3 and external terminals (aluminum electrodes) 4 of the semiconductor chip 1 are electrically connected by wire bonding with thin metal wires 5 such as gold wires. Then, the circuit forming surface portion of the semiconductor chip 1 is sealed with a liquid resin 6 made of epoxy resin or the like by a botting method. after that,
By bending the outer leads of the leads 3 as shown in FIG. 1, a small resin-sealed semiconductor device is completed.

前記半導体チップ１の厚さは、例えば０．２〜０　、５
　ｍａ＋、液状レジン６の厚さは、例えば０．２５〜０
　、６　ａｍ、リード３の厚さは、例えば０．１〜０゜
２５ｍｍ、絶縁性接着フィルム２の厚さは、絶縁フィル
ム（基材）が例えば２５〜１２５μ順、接着剤層が１０
〜３０μｍである。The thickness of the semiconductor chip 1 is, for example, 0.2 to 0.5.
ma+, the thickness of the liquid resin 6 is, for example, 0.25 to 0.
, 6 am, the thickness of the lead 3 is, for example, 0.1 to 0°25 mm, the thickness of the insulating adhesive film 2 is, for example, the insulating film (base material) is 25 to 125 μm, and the adhesive layer is 10 mm.
~30 μm.

また、半導体チップ１は、例えば、１６ＭＤＲＡＭ等で
あり、リード３は４２Ｎｉ−Ｆｅ材からなっている。絶
縁性接着フィルム２は、第８図に示すように、接着剤層
Ａ、基材Ｂ、接着剤層Ａの多層構造になっており、例え
ば、ポリエーテルアミドイミド／カプトン／ポリエーテ
ルアミドイミドからなっている。Further, the semiconductor chip 1 is, for example, a 16MDRAM or the like, and the leads 3 are made of a 42Ni-Fe material. As shown in FIG. 8, the insulating adhesive film 2 has a multilayer structure of an adhesive layer A, a base material B, and an adhesive layer A, and is made of, for example, polyetheramideimide/Kapton/polyetheramideimide. It has become.

第１図に示すように、この小型の樹脂封止型半導体装置
２０は、第１図に示すように、前記り−ド３のアウター
リードが実装配線基板７に、はんだ８で接着実装される
。As shown in FIG. 1, in this small resin-sealed semiconductor device 20, the outer leads of the leads 3 are adhesively mounted on a mounting wiring board 7 with solder 8. .

このようにすることにより、半導体チップ１の側面部に
封止レジンが存在しないか、或いは存在したとしてもレ
ジンポツティング時に流れる程度の薄い層であるため、
半導体チップ１とほぼ同一寸法のパッケージにすること
ができる。また、半導体チップ１の裏面部に封止レジン
が存在しないので、パッケージの厚さを０　、６　ａ＋
ｎ＋程度に薄くすることができる。By doing this, there is no sealing resin on the side surface of the semiconductor chip 1, or even if there is, it is a thin layer that flows during resin potting.
The package can have approximately the same dimensions as the semiconductor chip 1. In addition, since there is no sealing resin on the back surface of the semiconductor chip 1, the thickness of the package is 0.6 a+.
It can be made as thin as n+.

また、第３図に示すように、前記半導体チップ１の裏面
に放熱フィン９が熱良伝導性接着剤１゜で接着された構
造にすることにより、さらに放熱効率を向上させること
もできる。Further, as shown in FIG. 3, the heat dissipation efficiency can be further improved by forming a structure in which heat dissipation fins 9 are bonded to the back surface of the semiconductor chip 1 with a heat conductive adhesive of 1°.

〔実施例２〕 第４図は、本発明の実施例２の超薄型の樹脂封止型半導
体装置の要部断面図である。[Embodiment 2] FIG. 4 is a sectional view of a main part of an ultra-thin resin-sealed semiconductor device according to Embodiment 2 of the present invention.

本実施例２の超薄型の樹脂封止型半導体装置は、第４図
に示すように、半導体チップ１の回路形成面のＡＩ電極
上に金（Ａｕ）ボール５Ａが形成され、該金（Ａｕ）ボ
ール５Ａにリート３の錫（Ｓｎ）めっきされたインナー
リード先端が直接熱圧着されると共に、絶縁性接着フィ
ルム２を介在してリード３が固定されている。そして、
前記半導体チップ１の回路形成面部は、エポキシ樹脂等
からなる液状レジン６をポツティング法によって封止さ
れる。In the ultra-thin resin-sealed semiconductor device of Example 2, as shown in FIG. The tin (Sn)-plated inner lead tip of the lead 3 is directly thermocompressed onto the Au) ball 5A, and the lead 3 is fixed with an insulating adhesive film 2 interposed therebetween. and,
The circuit forming surface of the semiconductor chip 1 is sealed with a liquid resin 6 made of epoxy resin or the like by a potting method.

前記金（Ａｕ）ボール５Ａは、金（Ａｕ）線のネイルヘ
ットボンディングをした後、ボール部以外の金（Ａｕ）
線を除去する方法等によって作製される。The gold (Au) ball 5A is made of gold (Au) other than the ball portion after nail head bonding of the gold (Au) wire is performed.
It is produced by a method such as removing lines.

このようにすることにより、半導体チップ１の側面部に
封止レジンが存在しないか或いは存在したとしてもレジ
ンポツティング時に流れる程度の薄い層であるため、半
導体チップ１とほぼ同一寸法のパッケージにすることが
できる。また、半導体チップ１の裏面部に封止レジンが
存在しないので、パッケージの厚さを０　、６　ｍｍ程
度に薄くすることができる。By doing this, there is no sealing resin on the side surface of the semiconductor chip 1, or even if there is, it is a thin layer that flows during resin potting, so the package can be made to have approximately the same dimensions as the semiconductor chip 1. be able to. Furthermore, since there is no sealing resin on the back surface of the semiconductor chip 1, the thickness of the package can be reduced to about 0.6 mm.

さらに、半導体チップ１の回路形成面のＡ１電極上に金
（Ａｕ）ボール５Ａが形成され、該金（ＡＵ）ポール５
Ａにリード３の錫（Ｓｎ）めっきされたインナーリード
先端が直接熱圧着されるので、超薄型の樹脂封止型半導
体装置が得られる。Further, a gold (Au) ball 5A is formed on the A1 electrode on the circuit forming surface of the semiconductor chip 1, and the gold (AU) ball 5A is formed on the A1 electrode on the circuit formation surface of the semiconductor chip 1.
Since the tin (Sn) plated inner lead tips of the leads 3 are directly bonded to A by thermocompression, an ultra-thin resin-sealed semiconductor device is obtained.

第５図に示すように、この小型で超薄型の樹脂封止型半
導体装置３ｏは１、カード基板１１に実装穴１２が設け
られ、その中に実装される。As shown in FIG. 5, this small and ultra-thin resin-sealed semiconductor device 3o is mounted in a mounting hole 12 provided in a card substrate 11.

〔実施例３〕 第６図は、本発明の実施例３の樹脂封止型半導体装置の
要部断面図、 第７図は、本実施例３のリードフレームと半導体チップ
の関係を示す平面図である。[Example 3] FIG. 6 is a cross-sectional view of the main parts of a resin-sealed semiconductor device according to Example 3 of the present invention, and FIG. 7 is a plan view showing the relationship between the lead frame and the semiconductor chip of Example 3. It is.

本実施例３の樹脂封止型半導体装置は、第１図及び第２
図に示す実施例の樹脂封止型半導体装置のリート３を極
めて薄くして（リードのアウターリードが熱応力緩和形
状に構成されている）、パッケージを基板にはんだ実装
した状態で、温度ストレスによる熱応力を緩和させるこ
とができるようにしたものである。The resin-sealed semiconductor device of Example 3 is shown in FIGS. 1 and 2.
The REET 3 of the resin-sealed semiconductor device of the example shown in the figure is made extremely thin (the outer lead of the lead is configured in a shape that relieves thermal stress), and the package is soldered to the board. This allows thermal stress to be relaxed.

すなわち、第６図及び第７図に示すように、半導体チッ
プ１の回路形成面に絶縁性接着フィルム２を介在して極
めて薄いリード３０１が固定され、該リード３０１と半
導体チップ１の外部端子（アルミ電極）４とが金線等の
金属細線５でワイヤボンディングされ、電気的に接続さ
れている。そして、前記半導体チップ１の回路形成面部
は、エポキシ樹脂等からなる液状レジン６をポツティン
グ法によって封止される。That is, as shown in FIGS. 6 and 7, extremely thin leads 301 are fixed to the circuit forming surface of the semiconductor chip 1 with an insulating adhesive film 2 interposed therebetween, and the leads 301 and the external terminals of the semiconductor chip 1 ( The aluminum electrodes) 4 are wire-bonded with thin metal wires 5 such as gold wires, and are electrically connected. Then, the circuit forming surface of the semiconductor chip 1 is sealed with a liquid resin 6 made of epoxy resin or the like by a potting method.

前記リード３０１のアウターリード部には、補強用の絶
縁性接着テープ１３が設けられている。The outer lead portion of the lead 301 is provided with an insulating adhesive tape 13 for reinforcement.

第７図において、３００はリードフレーム、３０１Ａは
リード３０１のアウターリード、３０２゜３０３はリー
ドフレームの外枠である。In FIG. 7, 300 is a lead frame, 301A is an outer lead of the lead 301, and 302 and 303 are outer frames of the lead frame.

リード３０１の厚さは、例えば２０〜１００μｍ、絶縁
性接着フィルム２の厚さは、絶縁フィルム（基材）が例
えば２５〜１２５μｍ、接着剤層が例えば１０〜３０μ
ｍである。　また、半導体チップ１は、例えば、１６Ｍ
ＤＲＡＭ等である。The thickness of the lead 301 is, for example, 20 to 100 μm, the thickness of the insulating adhesive film 2 is, for example, 25 to 125 μm, and the thickness of the adhesive layer is, for example, 10 to 30 μm.
It is m. Further, the semiconductor chip 1 is, for example, 16M
DRAM etc.

リード３０１は、例えば、４２Ｎｉ−Ｆｅ材からなって
おり、その厚さは、例えば２０〜１５０μｍである。絶
縁性接着フィルム２は、第８図に示すように、接着剤層
Ａ、基材Ｂ、接着剤層Ａかなる多層構造になっており、
例えば、ポリエーテルアミトイミト２５μｍ／カプトン
５０μｍ／ポリエーテルアミトイミト２５μｍからなっ
ている。補強用の絶縁性接着テープ１３は、第９図に示
すように、接着剤層Ａ、基材Ｂからなる多層構成になっ
ており、例えば、ポリエーテルアミドイミド２５μｍ／
カプトン５０μｍからなっている。The lead 301 is made of, for example, 42Ni-Fe material, and has a thickness of, for example, 20 to 150 μm. As shown in FIG. 8, the insulating adhesive film 2 has a multilayer structure consisting of an adhesive layer A, a base material B, and an adhesive layer A.
For example, it is composed of 25 μm of polyether amitoimite/50 μm of Kapton/25 μm of polyether amitoimite. The reinforcing insulating adhesive tape 13 has a multilayer structure consisting of an adhesive layer A and a base material B, as shown in FIG.
It is made of Kapton 50 μm.

なお、前記カプトンの代りに他のポリイミド系フィルム
でもよい。Note that other polyimide films may be used instead of Kapton.

次に、本実施例の樹脂封止型半導体装置の組立工程を、
第１○図に示すフローチャートに添って説明する。Next, the assembly process of the resin-sealed semiconductor device of this example is as follows.
This will be explained with reference to the flowchart shown in FIG.

まず、最初に、リードフレーム３００のパターニングを
エツチング又はプレス法で行う（ステップ１０１）。次
に、第７図に示すように、パターニングされたリードフ
レーム３００に、３００〜４００　°Ｃ１１０〜１００
ｋｇ／Ｊ、３〜１０秒の条件で絶縁性接着フィルム（接
着剤層／基材／接着剤層）２及び補強用の絶縁性接着テ
ープ（接着剤層／基材）１３を貼り付る（ステップ１０
２゜１０３）。　次に、半導体チップ１を３００〜４０
０℃、１０−１００ｋｇ／ａＩｉ、　３−１０秒の条件
でリードフレーム３００に接着固定する（ステップ１０
４）。First, the lead frame 300 is patterned by etching or pressing (step 101). Next, as shown in FIG. 7, the patterned lead frame 300 is heated to
kg/J, for 3 to 10 seconds, paste the insulating adhesive film (adhesive layer/base material/adhesive layer) 2 and reinforcing insulating adhesive tape (adhesive layer/base material) 13 ( Step 10
2°103). Next, the semiconductor chip 1 is
Adhesively fix it to the lead frame 300 under the conditions of 0°C, 10-100 kg/aIi, and 3-10 seconds (step 10).
4).

次に、径３０μｍの金（Ａｕ）ｌｉＡ５を２００°Ｃの
温度下で超音波振動を併用した熱圧着法でワイヤボンデ
ングを行う（ステップｌ○５）。Next, wire bonding of gold (Au) LiA5 having a diameter of 30 μm is performed at a temperature of 200° C. by a thermocompression bonding method using ultrasonic vibration (step l○5).

次に、半導体チップ１の回路形成面上に液状エポキシ樹
脂からなるレジン６をポツティングして封止する（ステ
ップ１０６）。これを１８０℃で１時間加熱した後、１
５０℃で５時間加熱して硬化する（ステップ１０７）。Next, a resin 6 made of liquid epoxy resin is potted onto the circuit forming surface of the semiconductor chip 1 for sealing (step 106). After heating this at 180℃ for 1 hour,
It is cured by heating at 50° C. for 5 hours (step 107).

次に、リードフレーム３００の外枠３０２を切断しくス
テップ１０８）、エージング／選別しくステップ１０９
）、出荷する（ステップ１１ｏ）。Next, step 108) of cutting the outer frame 302 of the lead frame 300, and step 109 of aging/sorting.
), and shipped (step 11o).

そして、ユーザーは、リード３０１のアウターリード３
０１Ａを必要な形状に成形し、補強用の絶縁性接着テー
プ（接着剤層／基材）１３及び外枠３０３を切断して実
装配線基板にはんだ実装する。Then, the user selects the outer lead 3 of the lead 301.
01A is molded into a required shape, the reinforcing insulating adhesive tape (adhesive layer/base material) 13 and the outer frame 303 are cut, and soldered onto a mounting wiring board.

このようにリード３０１を薄くすることにより、半導体
装置を基板にはんだ実装する時における熱応力を緩和さ
せることができ、かつ、半導体装置が基板に実装された
状態で、温度ストレスによる熱応力を緩和させることが
できる。By making the lead 301 thinner in this way, it is possible to alleviate thermal stress when a semiconductor device is soldered onto a substrate, and also to alleviate thermal stress caused by temperature stress while the semiconductor device is mounted on a substrate. can be done.

また、補強用の絶縁性接着テープ１３を貼り付けた状態
で、組立９選別、出荷を行うことができるので、リード
等の変形や破損を防止することができる。Furthermore, since the assembly 9, sorting, and shipping can be performed with the reinforcing insulating adhesive tape 13 attached, deformation and damage to the leads etc. can be prevented.

また、前記半導体装置を基板にはんだ実装する時におけ
る熱応力を緩和させ、かつ、半導体装置が基板に実装さ
れた状態で、温度ストレスによる熱応力を緩和させるた
めに一４第１１図に示すように、リード３０１のアウタ
ーリード３０１Ａを折り曲げて弾力をもたせるようにし
てもよい。In addition, in order to alleviate the thermal stress when the semiconductor device is soldered onto the substrate, and also to alleviate the thermal stress caused by the temperature stress while the semiconductor device is mounted on the substrate, as shown in FIG. Additionally, the outer lead 301A of the lead 301 may be bent to provide elasticity.

〔実施例４〕 第１２図は、本発明の実施例４の樹脂封止型半導体装置
の要部断面図である。[Embodiment 4] FIG. 12 is a sectional view of a main part of a resin-sealed semiconductor device according to Embodiment 4 of the present invention.

本実施例４の樹脂封止型半導体装置は、第１２図に示す
ように、前記実施例１〜３において、前記半導体チップ
１の回路形成面部及びその側面部まで、エポキシ樹脂等
からなる樹脂成形粉トランスファモールド法により封止
したものである。図中１４は樹脂封止部である。As shown in FIG. 12, the resin-sealed semiconductor device of Example 4 is different from that of Examples 1 to 3, in which the circuit forming surface of the semiconductor chip 1 and its side surfaces are resin-molded with epoxy resin or the like. It was sealed using a powder transfer molding method. In the figure, 14 is a resin sealing part.

このようにすることにより、樹脂封止部１４の形状を一
定にすることができ、かつ信頼性を良くすることができ
る６ 以上、本発明を実施例にも゛とづき具体的に説明したが
、本発明は、前記実施例に限定されるものではなく、そ
の要旨を逸脱しない範囲において種々変更可能であるこ
とは言うまでもない。By doing so, the shape of the resin sealing portion 14 can be made constant and reliability can be improved.6 The present invention has been specifically explained based on the examples above. It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る （１）半導体チップの回路形成面部又は回路形成面部と
側面部のみが樹脂で封止されているので、パッケージを
半導体チップとほぼ同一程度の寸法の大きさにすること
ができる。また、半導体チップの回路形成面部と反対面
が露出しているので、パッケージ全体の厚さを薄くする
ことができ、また放熱効率を向上することができる。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows: (1) Only the circuit-forming surface or the circuit-forming surface and side surfaces of the semiconductor chip are sealed with resin. Therefore, the size of the package can be made almost the same as that of the semiconductor chip. Furthermore, since the surface of the semiconductor chip opposite to the circuit forming surface portion is exposed, the overall thickness of the package can be reduced and heat dissipation efficiency can be improved.

（２）リードのアウターリード部が面実装で薄型化に適
切な形状になっているので、超薄型パッケージにするこ
とができる。(2) Since the outer lead portion of the lead has a shape suitable for surface mounting and thinning, it is possible to create an ultra-thin package.

（３）リートのアウターリードが熱応力緩和形状に構成
されているので、半導体装置を基板にはんだ実装する時
における熱応力を緩和させることができ、かつ、半導体
装置が基板に実装された状態で、温度ストレスによる熱
応力を緩和させることができる。(3) Since the outer leads of the REIT are configured in a shape that relieves thermal stress, it is possible to alleviate the thermal stress when the semiconductor device is soldered onto the board, and it is possible to reduce the thermal stress when the semiconductor device is mounted on the board. , thermal stress caused by temperature stress can be alleviated.

（４）リードと半導体チップの外部端子との電気的接続
は、ワイヤ又は金属ボール又は金属バンプによってなさ
れているので、プレス又はの敵角情グ法で作成される通
常のリードフレームが使用でき、コストを低減すること
ができる。(4) Electrical connections between the leads and the external terminals of the semiconductor chip are made by wires, metal balls, or metal bumps, so a normal lead frame made by pressing or a metal cutting method can be used. Cost can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の実施例１の小型の樹脂封止型半導体
装置の全体構成を示す斜視図、第２図は、第１図に示す
Ａ　−、Ａ線で切った要部断面図、 第３図は、前記実施例１の半導体チップの裏面に放熱フ
ィンを設けた構造を示す断面図第４図は、本発明の実施
例２の超薄型の樹脂封止型半導体装置の要部断面図、 第５図は、本発明の実施例２の小型で超薄型の樹脂封止
型半導体装置がカート基板に実装される状態を示す断面
図、 第６図は、本発明の実施例３の樹脂封止型半導体装置の
要部断面図、 第７図は、本実施例３のリードフレームと半導体チップ
の関係を示す平面図、 第８図、第９図は、本実施例３の絶縁性接着フィルムの
構成を示す断面図。 第１０図は、本実施例３の樹脂封止型半導体装置の組立
工程を説明するためのフローチャート、第１１図は、本
実施例３の樹脂封止型半導体装置の変形例を説明するた
めの図、 第１２図は、本発明の実施例４の樹脂封止型半導体装置
の要部断面図である。 図中、１・・・半導体チップ、２・・・絶縁性接着フィ
ルム、３，３０１・・・リード、４・・半導体チップの
外部端子（アルミ電極）、５・・金属細線（ボンディン
グワイヤ）、５Ａ・・金属ボール、６・・液状レジン、
７・・・実装配線基板、８・・・はんだ、９・・・放熱
フィン、１０・・・熱良伝導性接着剤、１１・・カード
基板、１２・・・実装穴、１３・・・補強用の絶縁性接
着テープ、１４・・樹脂封止部、２０・・・樹脂封止型
半導体装置、３００・・・リードフレーム、３０１Ａ・
・・アウターリート、３０２，３０３・・・リードフレ
ームの外枠。1 is a perspective view showing the overall configuration of a small resin-sealed semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of essential parts taken along line A--A shown in FIG. , FIG. 3 is a cross-sectional view showing a structure in which heat dissipation fins are provided on the back surface of the semiconductor chip of the first embodiment, and FIG. FIG. 5 is a cross-sectional view showing a state in which a small and ultra-thin resin-sealed semiconductor device according to a second embodiment of the present invention is mounted on a cart board; FIG. FIG. 7 is a plan view showing the relationship between the lead frame and the semiconductor chip of Example 3. FIG. 8 and FIG. FIG. 3 is a cross-sectional view showing the structure of an insulating adhesive film. FIG. 10 is a flowchart for explaining the assembly process of the resin-sealed semiconductor device of Example 3, and FIG. 11 is a flowchart for explaining a modification of the resin-sealed semiconductor device of Example 3. FIG. 12 is a sectional view of a main part of a resin-sealed semiconductor device according to a fourth embodiment of the present invention. In the figure, 1... semiconductor chip, 2... insulating adhesive film, 3,301... lead, 4... external terminal of semiconductor chip (aluminum electrode), 5... thin metal wire (bonding wire), 5A...metal ball, 6...liquid resin,
7... Mounted wiring board, 8... Solder, 9... Radiation fin, 10... Good thermal conductivity adhesive, 11... Card board, 12... Mounting hole, 13... Reinforcement Insulating adhesive tape for use, 14...Resin sealing part, 20...Resin sealing type semiconductor device, 300...Lead frame, 301A.
... Outer lead, 302, 303... Outer frame of lead frame.

Claims (1)

【特許請求の範囲】 １、半導体チップの回路形成面でリードと半導体チップ
の外部端子とが電気的に接続され、樹脂で封止された半
導体装置において、前記リードが絶縁性に接着層を介在
して前記半導体の回路形成面に固定され、かつ前記半導
体チップの回路形成面部又は回路形成面部と側面部のみ
が樹脂で封止されていることを特徴とする半導体装置。 ２、前記請求項１に記載の半導体装置において、リード
のアウターリード部が面実装で薄型化に適切な形状にな
っていることを特徴とする半導体装置。 ３、前記請求項２に記載の半導体装置において、前記リ
ードのアウターリードが熱応力緩和形状に構成されてい
ることを特徴とする半導体装置。 ４、前記請求項１乃至３の各項に記載の半導体装置にお
いて、リードと半導体チップの外部端子との電気的接続
は、金属ワイヤ又は金属バンプ又は金属ボールによって
なされていることを特徴とする半導体装置。[Claims] 1. In a semiconductor device in which leads and external terminals of the semiconductor chip are electrically connected on the circuit forming surface of the semiconductor chip and sealed with resin, the leads are provided with an insulating adhesive layer interposed therebetween. A semiconductor device, wherein the semiconductor chip is fixed to a circuit-forming surface of the semiconductor chip, and only the circuit-forming surface portion or the circuit-forming surface portion and side portions of the semiconductor chip are sealed with resin. 2. The semiconductor device according to claim 1, wherein the outer lead portion of the lead has a shape suitable for surface mounting and thinning. 3. The semiconductor device according to claim 2, wherein the outer lead of the lead is configured to have a thermal stress relaxing shape. 4. The semiconductor device according to each of claims 1 to 3, wherein the electrical connection between the lead and the external terminal of the semiconductor chip is made by a metal wire, a metal bump, or a metal ball. Device.
JP2153183A 1990-06-11 1990-06-11 Semiconductor device and manufacturing method thereof Expired - Lifetime JP2895920B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2153183A JP2895920B2 (en) 1990-06-11 1990-06-11 Semiconductor device and manufacturing method thereof
KR1019910009519A KR100212095B1 (en) 1990-06-11 1991-06-10 Semiconductor device
US07/990,633 US5583375A (en) 1990-06-11 1992-12-14 Semiconductor device with lead structure within the planar area of the device
US08/721,240 US5714405A (en) 1990-06-11 1996-09-26 Semiconductor device
US08/721,339 US5869888A (en) 1990-06-11 1996-09-26 Semiconductor device with lead structure on principal surface of chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2153183A JP2895920B2 (en) 1990-06-11 1990-06-11 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0444347A true JPH0444347A (en) 1992-02-14
JP2895920B2 JP2895920B2 (en) 1999-05-31

Family

ID=15556861

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP2895920B2 (en)

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US5519251A (en) * 1992-10-20 1996-05-21 Fujitsu Limited Semiconductor device and method of producing the same
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US6534845B1 (en) 1998-10-16 2003-03-18 Oki Electric Industry Co., Ltd. Semiconductor device
US6558500B2 (en) 1996-04-19 2003-05-06 Hitachi Chemical Company, Ltd. Method of producing a lead frame with composite film attached, and use of the lead frame
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US5773313A (en) * 1992-10-20 1998-06-30 Fujitsu Limited Semiconductor device and method of producing the same
US6462424B1 (en) 1992-10-20 2002-10-08 Fujitsu Limited Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure
US5519251A (en) * 1992-10-20 1996-05-21 Fujitsu Limited Semiconductor device and method of producing the same
US6165819A (en) * 1992-10-20 2000-12-26 Fujitsu Limited Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure
US6084309A (en) * 1992-10-20 2000-07-04 Fujitsu Limited Semiconductor device and semiconductor device mounting structure
JPH06334110A (en) * 1993-05-26 1994-12-02 Hitachi Cable Ltd Film of excellent stamping property and lead frame using it
DE4421077B4 (en) * 1993-06-23 2007-01-04 Goldstar Electron Co., Ltd., Cheongju Semiconductor package and method for its manufacture
US5776802A (en) * 1993-12-08 1998-07-07 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method of the same
JPH08125066A (en) * 1994-10-26 1996-05-17 Dainippon Printing Co Ltd Resin-sealed semiconductor device and lead frame used for it, and manufacture of resin-sealed semiconductor device
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US5874783A (en) * 1995-06-21 1999-02-23 Oki Electric Industry Co., Ltd. Semiconductor device having the inner end of connector leads displaced onto the surface of semiconductor chip
EP0750342A3 (en) * 1995-06-21 1997-10-08 Oki Electric Ind Co Ltd Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip
EP1396886A3 (en) * 1995-06-21 2004-07-07 Oki Electric Industry Company, Limited Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip
US6558500B2 (en) 1996-04-19 2003-05-06 Hitachi Chemical Company, Ltd. Method of producing a lead frame with composite film attached, and use of the lead frame
EP0807973A2 (en) * 1996-05-16 1997-11-19 Oki Electric Industry Co., Ltd. Plastic molded type semiconductor device and method of manufacturing the same
EP0807973A3 (en) * 1996-05-16 1999-08-04 Oki Electric Industry Co., Ltd. Plastic molded type semiconductor device and method of manufacturing the same
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