JPS6040115U - preamplifier - Google Patents

preamplifier

Info

Publication number
JPS6040115U
JPS6040115U JP13106683U JP13106683U JPS6040115U JP S6040115 U JPS6040115 U JP S6040115U JP 13106683 U JP13106683 U JP 13106683U JP 13106683 U JP13106683 U JP 13106683U JP S6040115 U JPS6040115 U JP S6040115U
Authority
JP
Japan
Prior art keywords
terminal
transistor
resistor
preamplifier
npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13106683U
Other languages
Japanese (ja)
Inventor
邦雄 今井
Original Assignee
日立電子株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立電子株式会社 filed Critical 日立電子株式会社
Priority to JP13106683U priority Critical patent/JPS6040115U/en
Publication of JPS6040115U publication Critical patent/JPS6040115U/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプリアンプの回路図、第2図は本考案に
よるプリアンプ回路図、第3図、第4図は、第2図に示
す容量36の実際の構成を示す構成図である。 10:プリ・プリアンプ、20:増幅段、30:帰還回
路網、11:JEET、238,239.240:トラ
ンジスタ、35:可変抵抗、36:容量、Pa、Pb:
導体パターン。
FIG. 1 is a circuit diagram of a conventional preamplifier, FIG. 2 is a circuit diagram of a preamplifier according to the present invention, and FIGS. 3 and 4 are configuration diagrams showing the actual configuration of the capacitor 36 shown in FIG. 2. 10: Pre-preamplifier, 20: Amplification stage, 30: Feedback network, 11: JEET, 238, 239.240: Transistor, 35: Variable resistor, 36: Capacitance, Pa, Pb:
conductor pattern.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)接合形電界効果トランジスタのドレイン端子に抵
抗を介して、第1の電源を接続し、また、そのドレイン
端子を第1のNPNトランジスタのベースに接続し、該
NPNトランジスタのコレクタ端子に抵抗を介して、前
記第1の電源を接続し、該NPN)ランジスタのコレク
タをPNPトランジスタのベースに接続し、該PNPト
ランジスタのエミッタ端子に抵抗を介して前記第1の電
源を接続し、該PNPトランジスタのコレクタ端子に抵
抗を介して第2の電源を接続し、該PNPト)ンジスタ
のコレクタ端子を第2のNPNトランジスタのベース端
子に接続し、そのエミッタ端子に抵抗を介して前記第2
の電源を接続し、該第2のNPN)ランジスタのコレク
タ端子を前記第1の電源または第3の電源に接続し、該
第2のNPNトランジスタのエミッタ端子を抵抗と容量
との並列接続回路さらに、もうひとつの抵抗を介して前
記接合形電界効果トランジスタのゲート端子に接続し、
該接合形電界効果トランジスタのゲート端子を入力端子
とし、前記第2のNPNトランジスタのエミッタ端子を
出力端子とする構成のプリアンプ。
(1) A first power supply is connected to the drain terminal of the junction field effect transistor via a resistor, and the drain terminal is connected to the base of the first NPN transistor, and a resistor is connected to the collector terminal of the NPN transistor. the collector of the NPN transistor is connected to the base of the PNP transistor, the first power source is connected to the emitter terminal of the PNP transistor via a resistor, A second power source is connected to the collector terminal of the transistor via a resistor, the collector terminal of the PNP transistor is connected to the base terminal of a second NPN transistor, and the second power source is connected to the emitter terminal of the transistor via a resistor.
, the collector terminal of the second NPN transistor is connected to the first power supply or the third power supply, and the emitter terminal of the second NPN transistor is connected to a parallel connection circuit of a resistor and a capacitor. , connected to the gate terminal of the junction field effect transistor via another resistor,
A preamplifier configured such that the gate terminal of the junction field effect transistor is an input terminal, and the emitter terminal of the second NPN transistor is an output terminal.
(2)  前記プリアンプにおいて、前記第2のNPN
トランジスタのエミッタ端子に接続される抵抗と並列接
続の容量を、プリント基板等の導体パターンで実現する
ことを特徴とする実用新案登録請求の範囲第1項記載の
プリアンプ。
(2) In the preamplifier, the second NPN
The preamplifier according to claim 1, wherein the preamplifier is characterized in that the capacitance connected in parallel with the resistor connected to the emitter terminal of the transistor is realized by a conductor pattern such as a printed circuit board.
JP13106683U 1983-08-26 1983-08-26 preamplifier Pending JPS6040115U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13106683U JPS6040115U (en) 1983-08-26 1983-08-26 preamplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13106683U JPS6040115U (en) 1983-08-26 1983-08-26 preamplifier

Publications (1)

Publication Number Publication Date
JPS6040115U true JPS6040115U (en) 1985-03-20

Family

ID=30296433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13106683U Pending JPS6040115U (en) 1983-08-26 1983-08-26 preamplifier

Country Status (1)

Country Link
JP (1) JPS6040115U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116851A (en) * 1974-08-01 1976-02-10 Mitsubishi Electric Corp FUKIKANGATAZO FUKUKAIRO
JPS5211477U (en) * 1975-07-09 1977-01-26
JPS5742211A (en) * 1980-08-28 1982-03-09 Nippon Gakki Seizo Kk Feedback amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116851A (en) * 1974-08-01 1976-02-10 Mitsubishi Electric Corp FUKIKANGATAZO FUKUKAIRO
JPS5211477U (en) * 1975-07-09 1977-01-26
JPS5742211A (en) * 1980-08-28 1982-03-09 Nippon Gakki Seizo Kk Feedback amplifier

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