JPS6037746A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6037746A JPS6037746A JP14702083A JP14702083A JPS6037746A JP S6037746 A JPS6037746 A JP S6037746A JP 14702083 A JP14702083 A JP 14702083A JP 14702083 A JP14702083 A JP 14702083A JP S6037746 A JPS6037746 A JP S6037746A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- polycrystalline
- wirings
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置における多層Ｓｉ配線構造に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer Si wiring structure in a semiconductor device.
従来、半導体装置における多層ＳＺ配線構造は、第１図
に断面図で示す如＜、”’基板１上には絶縁Ｍ２が形成
され、該絶縁膜２上に第１のｓ７配線３が多結晶ＳＺに
より形成され、層間絶縁膜４を介して設けられた第２の
Ｓ＄配線５と前記層間絶縁膜に開けられたコンタクト穴
を通して接続されて成るのが通例であった。Conventionally, in a multilayer SZ wiring structure in a semiconductor device, as shown in a cross-sectional view in FIG. It was customary to be formed of SZ and connected to a second S$ wiring 5 provided through an interlayer insulating film 4 through a contact hole made in the interlayer insulating film.
１、か１２、ト配従来技術によると、第１のｓ７配線と
第２のｓ７配腺の接続部に自然酸化膜等が形成され、接
触抵抗が大きくなると論う欠点があった。1 and 12. According to the conventional technology, a natural oxide film or the like is formed at the connection between the first S7 wiring and the second S7 wiring, resulting in an increase in contact resistance.
本発明は、上記従来技術の欠点をなくシ、多層ｓ４配線
の接触抵抗を小さくすることを目的とする。The present invention aims to eliminate the drawbacks of the prior art described above and to reduce the contact resistance of multilayer S4 wiring.
前記目的を達成するための本発明の基本的な構成は、半
導体装置に於て、第１のｓ７配線と第２のｓ７配線の少
くとも接続部に１寸、Ｔｉ、Ｃｕ等の金属膜が挾まれて
形成されて成ることを特徴とする。The basic structure of the present invention for achieving the above object is that in a semiconductor device, a metal film of Ti, Cu, etc. is coated at least at the connection portion of the first S7 wiring and the second S7 wiring. It is characterized by being formed by being sandwiched.
以下、実施例により本発明を詳述する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図は本発明の一実施例を示す半導体装置の多層Ｓｉ
配線構造の断面図である。すなわち、８ｉ基板工１上に
は絶Ｒ膜１２が形成され、該絶縁膜１２上には第１のｓ
７配線及が多結晶Ｓｉにより形成され、該ｓ７配線１３
は、その上に形成された層間絶縁膜１４を介して形成さ
れた多結晶Ｓｉからなる第２のｓ７配線工６とは前記層
間絶縁膜Ｉ４に開けられたコンタクト穴を通して、予じ
めコンタクト穴内あるいはコンタクト穴周辺に迄メッキ
あるいはスパッタ等によ）形成されたＣｕあるいはＴｉ
等からなる金属膜１５を挾んで接続されて成る。FIG. 2 shows a multilayer Si of a semiconductor device showing an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the wiring structure. That is, the insulating film 12 is formed on the 8i substrate processing 1, and the first s
7 wirings are formed of polycrystalline Si, and the s7 wirings 13
The second S7 wiring 6 made of polycrystalline Si formed through the interlayer insulating film 14 formed thereon is connected to the second S7 interconnect 6 made of polycrystalline Si through the contact hole formed in the interlayer insulating film I4. Alternatively, Cu or Ti (by plating or sputtering, etc.) is formed around the contact hole.
They are connected by sandwiching a metal film 15 consisting of, etc.
本発明の如く、多Ｂｓ４配線のコンタクト部に於て金属
膜を挾んで接続することにより、Ｓｉ配線同志の接触抵
抗を下げることができる効果がある。By sandwiching and connecting metal films at the contact portions of multiple Bs4 wirings as in the present invention, there is an effect that the contact resistance between Si wirings can be lowered.
本発明は多結晶ｓ７配線相互の接続のみならず、下地Ｓ
Ｚ基板に形成された拡散層と、多結晶ＳＺ配線との接続
にも適用できることは云うまでもない。The present invention not only connects polycrystalline S7 wiring to each other, but also connects the underlying S7 wiring.
Needless to say, the present invention can also be applied to the connection between a diffusion layer formed on a Z substrate and a polycrystalline SZ wiring.
更に、金属膜はＳｉ配線下に延在して存在しても良い。Furthermore, the metal film may extend and exist under the Si wiring.
第１図は従来技術による半導体装置におけるＳｉ多層配
線構造を示す断面図、第２図は本発明の一実施例を示す
半導体装置におけるＳｉ多層配線構造の断面図である。
１．１１・・ｓ７基板 ２，１２・・絶縁膜３．１３・
・第１のｓ５配線 ４．Ｊ４・・層間絶縁膜 ５’ 、
３６−−第２のＳｉ配線１５−−金属膜。
以 上
出願人 株式会社諏訪精工舎FIG. 1 is a sectional view showing a Si multilayer wiring structure in a semiconductor device according to the prior art, and FIG. 2 is a sectional view showing a Si multilayer wiring structure in a semiconductor device showing an embodiment of the present invention. 1.11...s7 substrate 2,12...insulating film 3.13...
・First s5 wiring 4. J4...Interlayer insulating film 5',
36--Second Si wiring 15--Metal film. Applicant: Suwa Seikosha Co., Ltd.
Claims (1)
はＴｉ、Ｃｕ等の金属膜が狭まれて形成されて成ること
を特徴とする半導体装置。A semiconductor device characterized in that a metal film such as Ti, Cu, etc. is formed in a narrow manner at least at a connecting portion between a first S< wiring and a second S < wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14702083A JPS6037746A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14702083A JPS6037746A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037746A true JPS6037746A (en) | 1985-02-27 |
Family
ID=15420726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14702083A Pending JPS6037746A (en) | 1983-08-10 | 1983-08-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037746A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63211650A (en) * | 1987-02-26 | 1988-09-02 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
-
1983
- 1983-08-10 JP JP14702083A patent/JPS6037746A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63211650A (en) * | 1987-02-26 | 1988-09-02 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
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