JPS6035573A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6035573A JPS6035573A JP14385283A JP14385283A JPS6035573A JP S6035573 A JPS6035573 A JP S6035573A JP 14385283 A JP14385283 A JP 14385283A JP 14385283 A JP14385283 A JP 14385283A JP S6035573 A JPS6035573 A JP S6035573A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- layer
- region
- type
- type region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000009826 distribution Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical class N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
【発明の詳細な説明】
し技術分野〕
本発明は、金属酸化物半導体電界効果トランジスタ(以
下MO8FETと称す)に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a metal oxide semiconductor field effect transistor (hereinafter referred to as MO8FET).
二重拡散(DSA)型とも呼ばれる縦形のMOSFET
は第1図を参照し、例えばn′m5i(シリコン)基体
lの表面に酸化膜(S i Ox膜)2を介してポリ(
多結晶)シリコン層を形成し、これをバターニングした
ポリシリコンゲート3をマスクとし℃例えばホウ素(B
)を基体表面に拡散して深いn型領域4を形成し、上記
ポリシリコンゲート3を再びマスクとして例えばヒ素(
As)を拡散してソースとなる浅いn+型領領域5形成
し、このn型領域に接続するアルミニウム電極6を設け
ることにより、p型領域表面におけるn+型領領域5形
成されない部分4aをチャネル部とするとともVC,n
型基体をドレインとする同図に示すような二重拡散縦形
MO8FETが得られていた。Vertical MOSFET also called double diffusion (DSA) type
Referring to FIG. 1, for example, poly(
A polysilicon gate 3 made by forming a polycrystalline silicon layer and patterning it is used as a mask.
) is diffused into the substrate surface to form a deep n-type region 4, and using the polysilicon gate 3 again as a mask, for example, arsenic (
By diffusing As) to form a shallow n+ type region 5 that becomes a source and providing an aluminum electrode 6 connected to this n type region, the portion 4a on the surface of the p type region where the n+ type region 5 is not formed can be used as a channel part. VC,n
A double-diffused vertical MO8FET as shown in the figure was obtained, with the type substrate serving as the drain.
コノヨうな二重拡散型MO8FETにおいては、ポリシ
リコンゲートによって自己整合的に形成はれたチャネル
部となるp型拡散領域が、表面に高濃度部を有するため
にvth (Lきい電圧)の温度依存性が大きくなる。In a double-diffused MO8FET like this one, the p-type diffusion region, which becomes the channel part and is formed in a self-aligned manner by the polysilicon gate, has a high concentration part on the surface, so vth (L threshold voltage) depends on the temperature. sexuality becomes greater.
このため第2図に示されるようなID−voBの温度特
性において、温度係数θvth/aTがa V t h
/ II T−0となる点(Qpoint)における
ドレイン電流IQが大きくなる。同図において、温度係
数θV、h/aTが負となる領域(a Vt h /
a T (0)は素子温度が上昇するとドレイン電流1
1)が小さくなる領域であることを意味し、me係数a
Vth/a Tカ正ノ領H(θvt、、/a’r)O)
は素子温度が上昇するとドレイン電流lDが大きKなる
。Therefore, in the temperature characteristics of ID-voB as shown in FIG. 2, the temperature coefficient θvth/aT is a V th
/ II The drain current IQ at the point (Qpoint) where T-0 becomes large. In the figure, a region where the temperature coefficient θV, h/aT is negative (a Vt h /
a T (0) is the drain current 1 when the element temperature increases
1) means that it is a region where the value is small, and the me coefficient a
Vth/a T positive area H(θvt,, /a'r)O)
As the element temperature rises, the drain current ID increases.
この領域+111−いて■、とVD8の関係tみると第
3図を参照し、vo8?一定に置屋しているにもかかわ
らず、あるvD8からドレイン電流が暴走(矢印に示す
ように上方へ向う)し始める。温度係数正の領域では次
の正帰還がかかる。Looking at the relationship between this area +111-t■ and VD8, and referring to Figure 3, vo8? Despite being kept constant, the drain current begins to run out of control (upward as shown by the arrow) at a certain vD8. In the region where the temperature coefficient is positive, the following positive feedback is applied.
正帰還は、次のように起こる。IDXVD、の発熱によ
り素子温度(ケース温度)が上昇する。ケース温度が上
昇するとVthが減少する。vthが減少するとvGI
lが一定であるのでlDが増加する。Positive feedback occurs as follows. The element temperature (case temperature) increases due to the heat generated by the IDXVD. As the case temperature increases, Vth decreases. When vth decreases, vGI
Since l is constant, ID increases.
そして工。が増加すると1.の増加分の電流×vDaだ
けまた発熱する。これが繰り返えされる。And engineering. When increases, 1. Heat is generated again by the increase in current x vDa. This is repeated.
この正帰還は、■、8が大きい領域ではより小袋なID
でも発生しやすく、二重拡散型MO3FETのような■
、が3〜6Aの素子では500V以上の高耐圧に設計す
る場合に回避できない問題となる。This positive feedback shows that ■, in the region where 8 is large, the ID is more compact.
However, it is easy to occur, such as double diffusion type MO3FET■
, is 3 to 6 A, this becomes an unavoidable problem when designing a device with a high withstand voltage of 500 V or more.
本発明の目的は、MOS F E ’、1’、 q!f
にパワーMO8FETにお〜・て、チャネルfA度を低
減し、■、を下げ熱暴走を押え、これにより安全動作領
域(DOASO)を広く確保することにある。The object of the present invention is to provide MOS F E ', 1', q! f
In the power MO8FET, the objective is to reduce the channel fA degree, reduce the ①, suppress thermal runaway, and thereby secure a wide safe operating area (DOASO).
本願におい工開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、絶縁ゲート型電界効果トランジスタの製造法
において、ドレインとなるn型シリコン半導体基体の表
面にS iO2膜を介しくポリ(多結晶)シリコン層を
部分的に形成し、このポリシリコン層をマスクにしてシ
リコン基体表面にp型領域を拡散し、次いで上記ポリシ
リコン層の側端の一部を取り除い1ゲートとじ、このポ
リシリコン層を、マスクにしてp型領域の表面1(ソー
スとなるn+型領領域拡散することにより、p型惟域表
面のチャネル部のall勾配を小1くしもってI。That is, in a method for manufacturing an insulated gate field effect transistor, a polysilicon layer is partially formed on the surface of an n-type silicon semiconductor substrate that will serve as a drain via a SiO2 film, and this polysilicon layer is masked. Then, a part of the side edge of the polysilicon layer is removed to form one gate, and this polysilicon layer is used as a mask to diffuse the p-type region on the surface 1 of the p-type region (n+ which becomes the source). By diffusing the type region, the all gradient of the channel part on the surface of the p-type region can be made small by 1.
を低下させ前記目的を達成させるものである。This is to achieve the above objective by reducing the
第4図〜第9図は本発明による実施例であって二重拡散
型M OS F E Tの製造プロセスの要部を示す工
程断面図である。FIGS. 4 to 9 are process cross-sectional views showing essential parts of the manufacturing process of a double diffusion type MOSFET according to an embodiment of the present invention.
以下各工程にそって詳述する。Each step will be explained in detail below.
(11第4図に示すようにn型Si(シリコン)基体1
の底面(下面)K高濃度のn++層1aを拡散した基体
(ザブストレート)を用意し、表面(上面)を熱酸化し
て500八程度の厚さのゲート絶縁膜(Sin、膜)2
を生成し、その上に気相よりSiをデポジットして1〜
2μm厚のポリSi層3を形成する。さらにこの上に、
プラズマ処理によるシリコン・ナイトライド(SI3N
4)膜7を形成する。(11 As shown in Fig. 4, an n-type Si (silicon) substrate 1
A substrate (substrate) in which a high-concentration n++ layer 1a is diffused is prepared, and the surface (top surface) is thermally oxidized to form a gate insulating film (Sin, film) 2 with a thickness of approximately 500 mm.
1 to 1 by depositing Si from the gas phase on it.
A poly-Si layer 3 with a thickness of 2 μm is formed. Furthermore, on top of this
Silicon nitride (SI3N) by plasma treatment
4) Form the film 7.
(21Si、N4膜7及びポリSi層3を、プラズマ・
エッチ等の手段で一部を第5図に示すように取り除いて
拡散窓を形成後、残ばれたポリシリコン層7をマスクに
してイオン打込みにより基体表面にボロン(B)を導入
する。(The 21Si, N4 film 7 and poly-Si layer 3 are
After removing a portion by etching or other means to form a diffusion window as shown in FIG. 5, boron (B) is introduced into the substrate surface by ion implantation using the remaining polysilicon layer 7 as a mask.
(3)アニールすることによりボロン(B)を基体l内
に拡散し、第6図に示すようにp型拡散領域4を形成す
る。このときの拡散時間は、素子の最大耐圧電圧に対し
てパンチスルーをおこさない拡散長(d、)を形成する
必要がある。例えば、耐圧800Vレベルの素子ではチ
ャネル長(実効)10/jm以上、チャネル部表面濃度
2. OX 17cm−’以下とする。(3) Boron (B) is diffused into the substrate 1 by annealing to form a p-type diffusion region 4 as shown in FIG. The diffusion time at this time must be set to a diffusion length (d,) that does not cause punch-through with respect to the maximum withstand voltage of the element. For example, in a device with a breakdown voltage level of 800V, the channel length (effective) is 10/jm or more, and the channel surface concentration is 2. OX 17cm-' or less.
(4) 次いでHF系エッチ液で拡散窓表面の5in2
膜2をエッチするが、このとき、表面をS I s N
4膜7で覆われたポリS1層3の側端部3aがエッチ(
サイドエッチ)され、第7図に示すようにd。(4) Next, 5in2 of the diffusion window surface is etched with HF-based etchant.
Film 2 is etched, but at this time, the surface is etched with S I s N
The side edges 3a of the poly S1 layer 3 covered with the 4 film 7 are etched (
d as shown in FIG.
分だけボ+) 31層3が後退する。+) 31 layer 3 retreats.
(5) 熱リン酸等によるエッチにより3i3N、膜7
を取り除き、拡散窓表面の一部にS + Ot膜等のマ
スフ材8を形成し、ヒ素(A s )又はリン(P)を
イオン打込み、拡散して拡散深さat(at<at)の
ノースとなるn+型領領域5第8図のように形成する。(5) 3i3N, film 7 by etching with hot phosphoric acid, etc.
is removed, a mass material 8 such as an S + Ot film is formed on a part of the diffusion window surface, and arsenic (A s ) or phosphorus (P) is ion-implanted and diffused to a diffusion depth at (at<at). An n+ type region 5 serving as a north region is formed as shown in FIG.
このときポリSi層3がdoだけチャネル側へずれた状
態の拡散窓を通し’7n+型拡散がなされる。At this time, '7n+ type diffusion is performed through the diffusion window in which the poly-Si layer 3 is shifted by do to the channel side.
(6)全面にリンシリケートガラス(PSG)等の絶縁
膜9をデポジットし、コンタクトホトエッチ後アルミニ
ウム(kl)を蒸着して第9図に示すようにn+型領領
域5びそれに隣接するp型領域4の一部表面に低抵抗接
触するAI電極6を形成し、その後バターニングしてソ
ース電極(配線)を完成する。(6) An insulating film 9 such as phosphosilicate glass (PSG) is deposited on the entire surface, and after contact photoetching, aluminum (kl) is evaporated to form the n+ type region 5 and the adjacent p type region as shown in FIG. An AI electrode 6 that makes low resistance contact is formed on a part of the surface of the region 4, and then patterned to complete a source electrode (wiring).
第11図は、本発明による二重拡散型MO8FETのチ
ャネル部近傍の拡大断面図を示す。なお、第10図は、
これと対照して示ばれるこれまでの二重拡散ff1M0
8f”ETのチャネル部近傍の拡大断面図である。FIG. 11 shows an enlarged cross-sectional view of the vicinity of the channel portion of the double-diffused MO8FET according to the present invention. In addition, Fig. 10 shows
In contrast to this, the previous double diffusion ff1M0
FIG. 8 is an enlarged cross-sectional view of the vicinity of the channel portion of 8f''ET.
これまでの例では、基体表面部分におけるn型不純物の
濃度分布は第10A図に示すように拡散窓端な中心にピ
ークの部分10を含み、チャネル部分4aは比奴的濃度
の高い部分を含んでいる。In the example so far, the concentration distribution of n-type impurities in the substrate surface portion includes a peak portion 10 at the center of the diffusion window edge, as shown in FIG. 10A, and the channel portion 4a includes a portion with a relatively high concentration. I'm here.
これに対して本発明では、第11A図に示すようにn型
不純物のピーク部分はな(なっているため、チャネル部
分4aは比較的低い濃度をもつことになる。又、n型不
純物の拡散深さが同じである場合、これまでの例でのチ
ャネル長l、に対し℃本発明の例ではチャネル長7!2
はポリSi層をサイドエッチした深ζ(do )分だけ
短かく形成式れる。又、チャネル長とn型不純物の拡散
深さからn型不純物の拡散深さを差いた値Bとの関係は
、たとえは従来は、A、二〇、8XBであるのに対し本
発明の実施例ではβ2(0,6X13と短チャネルとな
る。On the other hand, in the present invention, as shown in FIG. When the depth is the same, the channel length l in the previous example is 7!2 in the example of the present invention.
is formed to be shorter by the depth ζ(do) of the side-etched poly-Si layer. Furthermore, the relationship between the channel length and the value B, which is the difference between the diffusion depth of the n-type impurity and the diffusion depth of the n-type impurity, is, for example, conventionally A, 20, 8XB, but in the present invention In the example, it is a short channel of β2(0,6×13).
第12図は本発明により完成した二重拡散型MO8F’
ETの一部を切り欠い1こ状態の斜視図である。11は
ドレイン電極、12は最終保護絶縁膜である。Figure 12 shows the double diffusion type MO8F' completed according to the present invention.
FIG. 2 is a perspective view of the ET in a partially cutaway state. 11 is a drain electrode, and 12 is a final protective insulating film.
以上実施例で述べた本発明によれば下記のように効果が
得られる。According to the present invention described in the embodiments above, the following effects can be obtained.
一般に二重拡散型MO8L”ETのゲート部しきい電圧
を表わす場合、下記の式
ゲート部 チャネル部
の濃度、ε6は誘電率、Ooはゲートチャネル間容量・
ψF0はゲート電極部の7エルミホテンゾヤル、む8
はチャネル基板のフェルミポテンシャルである。このう
ち最も影響の大きい項はチャネル部のを小きくするのに
有効である。Generally, when expressing the gate threshold voltage of a double-diffused MO8L"ET, the following formula is used.
ψF0 is 7 ermihotenzoyal of the gate electrode part, mu 8
is the Fermi potential of the channel substrate. Among these terms, the term that has the greatest influence is effective in reducing the channel area.
したがって、本発明によればυ11記実施例で述べたよ
うに拡散窓をずらせることでチャネル部となるp型領域
の濃度の濃い部分をN型不純物つぶし濃度を小さくする
ことによって、しきい電圧v11゜を有効に低減できる
。又、本発明によれは、第1回目の拡散層を深くとれる
ため、チャネル下の抵抗(ベース抵抗)を下げ、ホール
の蓄積をなくし負荷抵抗の問題を解決できる。Therefore, according to the present invention, as described in Example υ11, by shifting the diffusion window and reducing the N-type impurity concentration in the heavily concentrated part of the p-type region which becomes the channel part, the threshold voltage can be reduced. v11° can be effectively reduced. Further, according to the present invention, since the first diffusion layer can be made deep, the resistance under the channel (base resistance) can be lowered, hole accumulation can be eliminated, and the problem of load resistance can be solved.
第43図は、ドレイン耐圧800Vレベルの二重拡散型
MO8FET素子において1.をI八まで下げる例を示
す■D8”D特性曲線図である。同図において曲線A、
BはこれまでのMOSFETの例、曲線Cは本発明の方
法によるMOSFETの例を示す。FIG. 43 shows 1. ■D8"D characteristic curve diagram showing an example of lowering the value to I8. In the figure, curves A,
Curve B shows an example of a conventional MOSFET, and curve C shows an example of a MOSFET according to the method of the present invention.
なお、この場合のプロセス仕様、及び、Vtb特性は下
表のとおりである。Note that the process specifications and Vtb characteristics in this case are as shown in the table below.
(表) ※ポリSi層のサイドエッチ量do−3μmとする。(table) *The side etch amount of the poly-Si layer is set to do-3 μm.
このように本発明によればvtb特性を0.2〜0.6
(V)と小さくし、■。をIAまで下げることにより、
高電圧側で熱暴走を有効に抑えることができる。その結
果、第14図に示すように高耐圧パワーMO8FETの
安全動作領域(DOASO)を改善することができる。In this way, according to the present invention, the vtb characteristic is 0.2 to 0.6.
Make it smaller (V) and ■. By lowering to IA,
Thermal runaway can be effectively suppressed on the high voltage side. As a result, as shown in FIG. 14, the safe operating area (DOASO) of the high voltage power MO8FET can be improved.
図中の実線は、本発明による二重拡散型MO8FETの
DOASOを示している。一方点線は、従来の二重拡散
型MO8FETのDOASOを示している。両者を比較
すると、高圧側でDOASOが改善されていることがわ
かる。The solid line in the figure shows the DOASO of the double diffused MO8FET according to the present invention. On the other hand, the dotted line indicates the DOASO of the conventional double-diffused MO8FET. Comparing the two, it can be seen that DOASO is improved on the high pressure side.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱し。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and may depart from the gist thereof.
ない範囲で種々変更可能であることはいうまでもない。It goes without saying that various changes can be made within this range.
たとえば、ポリSi層ゲート上に3i3N。For example, 3i3N on poly-Si layer gate.
膜を形成する代りに薄い酸化膜を介してホトレジストで
覆い、これをマスクとしてポリSi層サイドエッチのた
めのマスクとするようにしてもよい。Instead of forming a film, it may be covered with a photoresist through a thin oxide film, and this may be used as a mask for side etching the poly-Si layer.
本発明は特にドレイン耐圧800Vの二重拡散高耐圧縦
型MO8FETに適用して有効である。The present invention is particularly effective when applied to a double-diffused high voltage vertical MO8FET with a drain voltage of 800V.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である高耐圧縦型パワーM
O8FETに適用した場合について説明したが、本発明
はこれ以外の一般の縦型パワーMO8FETの■th低
減手段として応用することができる。■thを低減する
ことで0−MOSFETの電源電圧(5v)と同様の電
圧からの駆動が可能となる。又、MOSFETにおいて
ON抵抗を低減することができる。The above explanation will mainly focus on the high voltage vertical power M
Although the case where the present invention is applied to an O8FET has been described, the present invention can also be applied as a th reduction means for other general vertical power MO8FETs. (2) By reducing th, it becomes possible to drive from a voltage similar to the power supply voltage (5V) of the 0-MOSFET. Further, the ON resistance of the MOSFET can be reduced.
第1図は、二重拡散型パワーMO8FETの一例を示す
断面図である。
第2図は、二重拡散型M OS F E Tにおける熱
依存性を示す■。、−1゜曲線図である。
第3図は、二重拡散型MO8FETにおける■Dll
’D特性曲線図である。
第4図〜第9図は、本発明による一実施例であって、二
重拡散型MO8FETの製造プロセスを示す工程断面図
である。
第10図及び第11図は二重拡散型M 03 F’ E
TKおけるチャネル部近傍の拡大断面図であって第10
図はこれまでの例、第11図は本発明の例を示す。第1
0A図及び第11A図は第1O図及び第11図に対応す
る基体表面におけるp型拡故濃度分布曲線図である。
第12図は、本発明による二重拡散型MO8FETの一
部切り欠いた状態の斜視Mである。
第13図は、本発明の効果を示す■。B’−Itl特性
曲線図である。
第14図は、本発明の効果を示すDOASO特性曲線図
である。
1・・・n型Si基体(ドレイン)、2・・・ゲート絶
縁膜(S r Ot膜)、3・・・ポリSiゲート、4
・・・p型拡散領域、4a・・・チャネル部、5・・・
n+型拡散領域(ソース)、6・・・ソースAl電極、
7・・・St、N、膜、8・・・マスク材、9・・・P
SG膜、10・・・ピーク部分、11・・・ドレイン電
極、12・・・最終保護膜絶縁膜。
代理人 弁理士 高 橋 明 失
策 1 図
第 2 図
第3図
陶
第 5 図
第 6 図
第 7 図
第 8 図
第12図
/Z
第13図
ゾρ5CVノ
第14図
VDδ
手続補正書(方式)
%式%
発明の名称
半導体装置の製造法
補正をする者
・1ケ1トノ関係特許出願人
名 称 15101株式会Jl: IJ 立 製 作
所二 理 人
補
袖
補
・・・・・・濃度分布曲線図である。」を削除する。
(2) 図面第10図及び第11図を別添の通り補正す
第1 Of¥1
第111]1
手続補正書(@8)
事件の表示
昭和58 年特許願第 143852 シ1発明の名称
半導体装置の製造法
補正をする者
+++1との1語 特許出願人
名 称 75101は式会ンI [1立 製 作 所代
理 人
明細書の発明の詳細な説明の欄
補正の内容
次頁のとおり。
(1)明細書第7頁下から2行と3行の間に行を改めて
下記事項を挿入する。
記
[第10図の(A)及び第11図の(B)は第10図及
び第11図に対応する基体表面におけるp型拡散濃度分
布曲線図である。」
(2) 明細書第7頁下から1行「第10A図」を「第
10図の(A)」と補正する。
(3)明細書第8頁3行「第11A図」を「第11図の
(B)」と補正する。FIG. 1 is a cross-sectional view showing an example of a double-diffused power MO8FET. Figure 2 shows the thermal dependence of double diffusion type MOS FET. , -1° curve diagram. Figure 3 shows ■Dll in double diffusion type MO8FET.
'D characteristic curve diagram. FIG. 4 to FIG. 9 are process cross-sectional views showing a manufacturing process of a double diffusion type MO8FET, which is an embodiment of the present invention. Figures 10 and 11 show double diffusion type M 03 F' E
FIG. 10 is an enlarged cross-sectional view of the vicinity of the channel part in TK;
The figure shows a conventional example, and FIG. 11 shows an example of the present invention. 1st
FIG. 0A and FIG. 11A are p-type diffusion concentration distribution curve diagrams on the substrate surface corresponding to FIGS. 1O and 11. FIG. 12 is a partially cutaway perspective view M of the double diffusion type MO8FET according to the present invention. FIG. 13 shows the effect of the present invention. It is a B'-Itl characteristic curve diagram. FIG. 14 is a DOASO characteristic curve diagram showing the effects of the present invention. DESCRIPTION OF SYMBOLS 1... N-type Si base (drain), 2... Gate insulating film (S r Ot film), 3... Poly Si gate, 4
...p-type diffusion region, 4a...channel part, 5...
n+ type diffusion region (source), 6... source Al electrode,
7...St, N, film, 8...mask material, 9...P
SG film, 10...Peak portion, 11...Drain electrode, 12...Final protective film insulating film. Agent Patent Attorney Akira Takahashi Mistakes 1 Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 12/Z Figure 13 ρ5CV Figure 14 VDδ Procedural amendment (method) % formula % Name of the invention Person who amends the manufacturing method of semiconductor devices / Name of the relevant patent applicant Name 15101 Co., Ltd. Jl: IJ Standing Manufacturing
This is a concentration distribution curve diagram. ” to be deleted. (2) Amend the drawings Figures 10 and 11 as attached. 1 Of\1 No. 111] 1 Procedural amendment (@8) Indication of the case 1982 Patent Application No. 143852 C1 Name of the invention Semiconductor The name of the patent applicant 75101 is the name of the person making the amendment to the manufacturing method of the device. (1) Insert the following information in a new line between the second and third lines from the bottom of page 7 of the specification. 10(A) and FIG. 11(B) are p-type diffusion concentration distribution curve diagrams on the substrate surface corresponding to FIGS. 10 and 11. (2) ``Figure 10A'' in the first line from the bottom of page 7 of the specification is corrected to ``(A) in Figure 10''. (3) ``Figure 11A'' on page 8 of the specification, line 3, is corrected to ``(B) in Figure 11''.
Claims (1)
縁膜を介してゲートとなる多結晶半導体層を部分的に形
成し、この多結晶半導体層をマスクにして基体表面に第
2導電型半導体領域を拡散し、次いで上記多結晶半導体
層の側端の一部を取り除き、この多結晶半導体層をマス
クとして第2導電型領域の表面にソースとなる第1導[
型領域を拡散することを特徴とする半導体装置の製造法
。1. A polycrystalline semiconductor layer, which will become a gate, is partially formed on the surface of a first conductivity type semiconductor substrate, which will become a drain, via an insulating film, and a second conductivity type semiconductor layer, which will become a gate, will be formed on the surface of the substrate, using this polycrystalline semiconductor layer as a mask. The semiconductor region is diffused, and then a part of the side edge of the polycrystalline semiconductor layer is removed, and using this polycrystalline semiconductor layer as a mask, a first conductive layer is formed on the surface of the second conductivity type region to serve as a source.
A method for manufacturing a semiconductor device characterized by diffusing a mold region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14385283A JPS6035573A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14385283A JPS6035573A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6035573A true JPS6035573A (en) | 1985-02-23 |
Family
ID=15348456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14385283A Pending JPS6035573A (en) | 1983-08-08 | 1983-08-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6035573A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6376932A (en) * | 1986-09-17 | 1988-04-07 | Kajima Corp | Dynamic vibration reducer |
JPH01231377A (en) * | 1988-03-11 | 1989-09-14 | Fuji Electric Co Ltd | Manufacture of mos-type semiconductor device |
JPH01238172A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Manufacture of mos type semiconductor device |
JPH01256172A (en) * | 1988-04-06 | 1989-10-12 | Fuji Electric Co Ltd | Manufacture of conductivity modulating mosfet |
JPH0349238A (en) * | 1989-07-18 | 1991-03-04 | New Japan Radio Co Ltd | Manufacture of vertical double diffusion mos transistor |
JP2004511084A (en) * | 2000-08-08 | 2004-04-08 | アドバンスド パワー テクノロジー,インコーポレイテッド | Power MOS device having asymmetric channel structure |
JP2007305724A (en) * | 2006-05-10 | 2007-11-22 | Matsushita Electric Ind Co Ltd | Device and method for deciding transfer state of paste |
CN106298525A (en) * | 2015-05-29 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS |
-
1983
- 1983-08-08 JP JP14385283A patent/JPS6035573A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6376932A (en) * | 1986-09-17 | 1988-04-07 | Kajima Corp | Dynamic vibration reducer |
JPH0555741B2 (en) * | 1986-09-17 | 1993-08-17 | Kajima Construction Corp | |
JPH01231377A (en) * | 1988-03-11 | 1989-09-14 | Fuji Electric Co Ltd | Manufacture of mos-type semiconductor device |
JPH01238172A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Manufacture of mos type semiconductor device |
JPH01256172A (en) * | 1988-04-06 | 1989-10-12 | Fuji Electric Co Ltd | Manufacture of conductivity modulating mosfet |
JPH0349238A (en) * | 1989-07-18 | 1991-03-04 | New Japan Radio Co Ltd | Manufacture of vertical double diffusion mos transistor |
JP2004511084A (en) * | 2000-08-08 | 2004-04-08 | アドバンスド パワー テクノロジー,インコーポレイテッド | Power MOS device having asymmetric channel structure |
JP2007305724A (en) * | 2006-05-10 | 2007-11-22 | Matsushita Electric Ind Co Ltd | Device and method for deciding transfer state of paste |
CN106298525A (en) * | 2015-05-29 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of plane VDMOS |
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