JPS59220971A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59220971A JPS59220971A JP9615783A JP9615783A JPS59220971A JP S59220971 A JPS59220971 A JP S59220971A JP 9615783 A JP9615783 A JP 9615783A JP 9615783 A JP9615783 A JP 9615783A JP S59220971 A JPS59220971 A JP S59220971A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- polysilicon layer
- mask
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 229920005591 polysilicon Polymers 0.000 claims description 44
- 238000009792 diffusion process Methods 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 206010011732 Cyst Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は絶縁ダート電界効果型トランジスタ等の半導
体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device such as an insulated dart field effect transistor.
近年の素子の高集積化に伴い絶縁ダート電界効果型トラ
ンジスタの微細化が進んでいるが、このようなトランジ
スタの微細化に伴い、トランジスタのドレイン近傍での
電界集中による装置の特性上および信頼性上の問題が目
立ってきた。すなわち、ドレイン近傍の強電界領域で電
荷（電子或いは正孔）が加速され、シリコン原子と衝突
してキャリア増倍を起こし、キャリア増倍によシ生じた
多数キャリアが基板側へ流れ、基板電流となって基板の
電位を持ち上げＩＣの特性を劣化させることになる。ま
た、この際に少数キャリアは大部分はドレインに流れ込
むが一部の充分に高いエネルギーを得たものはシリコン
とシリコン酸化膜との界面における電位障壁を乗）越え
てシリコン酸化膜中に入シ、ダートにまで達したものは
ダート電流となるが一部は上記酸化膜中に捕獲され酸化
膜中の電荷量を変化させ、結果としてトランジスタの、
ｌ、′、ｉ 血を変化させる。In recent years, insulated dirt field-effect transistors have become increasingly finer due to the increased integration of devices. However, with the miniaturization of such transistors, the electric field concentration near the drain of the transistor has caused problems in device characteristics and reliability. The above problem has become apparent. That is, charges (electrons or holes) are accelerated in the strong electric field region near the drain, collide with silicon atoms, cause carrier multiplication, and the majority carriers generated by carrier multiplication flow toward the substrate, increasing the substrate current. This raises the potential of the substrate and deteriorates the characteristics of the IC. At this time, most of the minority carriers flow into the drain, but some carriers with sufficiently high energy cross the potential barrier at the interface between silicon and silicon oxide film and enter the silicon oxide film. , the current that reaches the dirt becomes a dirt current, but some of it is captured in the oxide film and changes the amount of charge in the oxide film, resulting in
l,′,i Change blood.
ところで現在上述のようなドレイン近傍の電界集中によ
る問題を、ドレイン近傍の電界強度を緩和させて回避す
る手段として、ＬＤＤ４皆造（ｌｉｇｈｔｌｙ ｄｏｐ
ｅｄ ｄｒａＩｎ 梠造）の素子が提案されている。こ
のＬＤＤ ４：ｐｊ造の素子は従来のソース・ドレイン
領域と略同程度の不純物娘度を有する第１拡散層（高濃
度拡散層）のチャネル側に、この第１拡散層よシも不純
物濃度の低い電界強度緩和用の第２拡散層（低濃度拡散
層）を追加形成した２ Ｍ ＋’Ｒ造のソース・ドレイ
ン領域を形成したものである。By the way, as a means of alleviating the electric field strength near the drain to avoid the above-mentioned problem of electric field concentration near the drain, four LDDs (lightly doped) are being developed.
A device has been proposed. This LDD 4:pj structure element has an impurity concentration on the channel side of the first diffusion layer (high concentration diffusion layer) which has approximately the same impurity density as the conventional source/drain region. A source/drain region of 2 M+'R structure is formed in which a second diffusion layer (low concentration diffusion layer) for mitigating the electric field intensity is additionally formed.
次妃このようなＬＤＤ構造の素子の製造手順を簡単に説
明する。第１図に示すように、周知の方法によシ半導体
基板１ノ上に熱酸化によｐｃ−ト酸化膜１２を形成し、
このケ９−ト酸化膜１２上にポリシリコン層１３を被着
してレソスｈ１３’ｆ：マスクとしてポリシリコン層１
３をパターニングする。次に上記ポリシリコン層１３を
マスクとしてイオン注入を行ない高不純物濃度のｍｌ拡
散層１４．１５を形成する。Next, the manufacturing procedure of a device having such an LDD structure will be briefly explained. As shown in FIG. 1, a PC oxide film 12 is formed by thermal oxidation on a semiconductor substrate 1 by a well-known method,
A polysilicon layer 13 is deposited on this ketone oxide film 12 to form a resin layer h13'f: the polysilicon layer 1 is used as a mask.
Pattern 3. Next, ion implantation is performed using the polysilicon layer 13 as a mask to form ml diffusion layers 14 and 15 with high impurity concentration.
その後、第２図に示すようにレソスト１３′をマスクと
してケミカルドライエツチング或いはウェットエツチン
グによフポリシリコン層１３の側壁をエツチングし、ダ
ート電極１３Ｇを形成する。次に第３図に示すようにこ
のダート電極１３Ｇをマスクとして低濃度の不純物をイ
オン注入し、低濃度の第２拡散層１６．１７をそれぞれ
第１拡散層１５．１６のチャネル側に形成する。Thereafter, as shown in FIG. 2, the side wall of the polysilicon layer 13 is etched by chemical dry etching or wet etching using the resist 13' as a mask to form a dirt electrode 13G. Next, as shown in FIG. 3, low concentration impurities are ion-implanted using the dirt electrode 13G as a mask to form low concentration second diffusion layers 16 and 17 on the channel sides of the first diffusion layers 15 and 16, respectively. .
このようにして形成したＬＤＤ 栂造の素子は、電界集
中緩和用の第２拡散層１６．１７の幅りがポリシリコン
層１３の側壁の後退量によって略決定される。しかしな
がらこの後退量すなわチレシスト１３′ヲマスクとした
；Ｊ？ポリシリコン層３の横方向のエツチング量を制御
するのは極めて困難で、ＩＩＩＮＬのばらつきが大きい
ため、トランジスタの特性が一定しないという欠点があ
った。In the LDD Tozuzo element formed in this manner, the width of the second diffusion layers 16 and 17 for alleviating electric field concentration is approximately determined by the amount of recession of the side wall of the polysilicon layer 13. However, this amount of retreat, that is, the Chile cyst 13' was masked; J? It is extremely difficult to control the amount of lateral etching of the polysilicon layer 3, and the variation in IIINL is large, resulting in the disadvantage that the characteristics of the transistor are not constant.
ＬＤＤ構造の素子の製造方法としては他に、次に述べる
よりなＬＤＤ構造の素子の形成方法が採用される場合が
ある。すなわち、第４図において、通常の方法によシポ
リシリコン層を・ぐタ一二：ｙ ／’ ｌ、てダート電
極１３Ｇを形成し、このケ”−ト電極７３Ｇをマスクと
して低不純物濃度の第２拡散層１６．１７を形成した後
、基板ノ１の上面全面に厚いＣＶＤ （ｃｈｅｍｉｃａ
ｌ ｖａｐｏｕｒｄｅｐｏｓｉｔｉｏｎ ）酸化膜１８
を付着する。しかる後に第５図に示すようにＲＩＥ法（
ｒｅａｃｔｉｖｅ ｔｏｎｅｔｃｈｉｎｇ法）による異
方性エツチングによりＣＶＤ酸化膜を基板１ノに対して
垂直方向に一定の厚みでエツチングし、ケ゛−ｈ 電極
ｉ ｓ Ｇの側壁にＣＶＤ酸化膜１８を残すようにする
。その後、ダート電極１３Ｇおよび側壁のＣＶＤ酸化膜
１８をマスクとして高濃度の不純物をイオン注入し、第
１拡散層１５．１６を形成する。As a method for manufacturing an element having an LDD structure, the following method for forming an element having an LDD structure may be employed. That is, in FIG. 4, a dirt electrode 13G is formed by depositing a polysilicon layer in a conventional manner, and a dirt electrode 13G with a low impurity concentration is formed using this gate electrode 73G as a mask. After forming the second diffusion layers 16 and 17, thick CVD (chemical vapor deposition) is performed on the entire upper surface of the substrate 1.
l vapordeposition) oxide film 18
Attach. After that, as shown in Fig. 5, the RIE method (
The CVD oxide film 18 is etched to a constant thickness in the direction perpendicular to the substrate 1 by anisotropic etching using a reactive tone etching method, so that the CVD oxide film 18 is left on the side wall of the electrode i s G. After that, using the dirt electrode 13G and the CVD oxide film 18 on the sidewall as a mask, high concentration impurity ions are implanted to form the first diffusion layer 15.16.
このようにして形成したＬＤＤ構造の素子の低濃度の第
２拡散層１６．１７の幅りは、ＣＶＤ酸化膜１８の膜厚
およびＲＩＥ法にょるＣＶＤ酸化膜１８のエツチング条
件によシ決まる。この中で特にＲＩＥ法によるエツチン
グのエツチング条件は、その設定が困難で、やけ、９）
ランジスタ特性のばらつきが問題となっていた。さらに
この場合ではＲＩＰ法が°計度性に欠けるため、コスト
上昇を招く欠点もあった。The width of the lightly doped second diffusion layers 16 and 17 of the LDD structure element thus formed is determined by the thickness of the CVD oxide film 18 and the etching conditions of the CVD oxide film 18 by the RIE method. Among these, it is especially difficult to set the etching conditions for etching using the RIE method.
Variations in transistor characteristics were a problem. Furthermore, in this case, the RIP method lacks metricity, which has the disadvantage of increasing costs.
この発明は上記のような点に鑑みなされたもので、’ｒ
、Ｄｏ楢造のトランジスタをその特性のばらつきがない
ように制御性よくかつ低コストで製造することのできる
半導体装置の製造方法を提供しようとするものである。This invention was made in view of the above points.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can manufacture transistors of the same type with good controllability and at low cost so that there are no variations in characteristics.
すなわちこの発明による半導体装置の製造方法では、半
導体基板上にダート酸化膜を形成した後、トランジスタ
のチャネル形成予定部上にダート電極用のポリシリコン
層の／（ターンを形成し、このポリシリコン層をマスク
として基板と逆型の不純物をイオン注入することにより
電界強度緩和用の低濃度拡散層（第２拡散層）を形成す
る。次に上記ポリシリコン層の／？ターンの少ｉくとも
側壁を適宜窒化シリコン膜等の耐酸！化性のマスクを用
いて一定膜厚分だけ酸化させ、ポリシリコン層の・ヤタ
ーンに側壁酸化膜を成長させる。続いて上記ポリシリコ
ン層のツヤターンおよびその側壁の側壁酸化膜をマスク
としよりトランジスタのチャネル領域の両側に上記低濃
度拡散層が残るようにソース・ドレインとなる高濃度拡
散層（第１拡散層）を形成するものである。That is, in the method for manufacturing a semiconductor device according to the present invention, after forming a dirt oxide film on a semiconductor substrate, a turn of a polysilicon layer for a dirt electrode is formed on a portion where a channel of a transistor is to be formed, and this polysilicon layer is A low concentration diffusion layer (second diffusion layer) for mitigating electric field strength is formed by ion-implanting an impurity of the opposite type to the substrate using as a mask.Next, at least the sidewall of the /? turn of the polysilicon layer is formed. The polysilicon layer is oxidized to a certain thickness using an acid-resistant mask such as a silicon nitride film, and a sidewall oxide film is grown on the edges of the polysilicon layer.Subsequently, a sidewall oxide film is grown on the edges of the polysilicon layer and its sidewalls. Using the sidewall oxide film as a mask, high concentration diffusion layers (first diffusion layers) that will become sources and drains are formed so that the low concentration diffusion layers remain on both sides of the channel region of the transistor.
以下図面を参照してこの発明の一実施例につきＮチャネ
ルＭＯＳトランジスタを例にとシ説明する。An embodiment of the present invention will be described below with reference to the drawings, taking an N-channel MOS transistor as an example.
第６図において、Ｐ型シリコンの半導体基板１ノの表面
を熱酸化させ、基板１ノ上にｃ−ト酸化膜１２を形成す
る。次に、適宜リン等を導入したポリシリコン層１３を
ＣＶＤ法でダート酸化膜１２上に形成し、さらにこのポ
リシリコン層１３上に窒化シリコンＮ２０をＣＶＤ法に
よル積層形成する。次いでフォトレゾストを用いた写真
蝕刻技術により上記窒化シリコン膜２０およびぼりシリ
コン層１３をパターニングする。In FIG. 6, the surface of a P-type silicon semiconductor substrate 1 is thermally oxidized to form a c-type oxide film 12 on the substrate 1. Next, a polysilicon layer 13 doped with phosphorus or the like as appropriate is formed on the dirt oxide film 12 by the CVD method, and silicon nitride N20 is further laminated on this polysilicon layer 13 by the CVD method. Next, the silicon nitride film 20 and the raised silicon layer 13 are patterned by photolithography using photoresist.
次に、第７図に示すように上記窒化シリコン膜２０およ
びポリシリコン層１３のツヤターンをマスクとして、リ
ン、ひ素等のＮ型不純物を半導体基板１１表面にイオン
注入し、電界強度緩和用の第２拡散層（低濃度拡散層）
１６．１７を形成する。Next, as shown in FIG. 7, using the glossy turn of the silicon nitride film 20 and the polysilicon layer 13 as a mask, ions of N-type impurities such as phosphorus and arsenic are implanted into the surface of the semiconductor substrate 11 to reduce the electric field strength. 2 Diffusion layer (low concentration diffusion layer)
16.17 is formed.
続いて第８図に示すように、上記の基板１１を高温酸化
性４皿気中に設置し、上記窒化シリコン膜２０をマスク
としてその下層のポリシリコン層１３を酸化する。この
際に、上記ポリシリコン層１３の上面は１ｔ「］酸化性
の窒化シリコン膜２０で被われているため酸化されず、
結局ポリシリコン層１３の側壁のみが酸化される。また
、ポリシリコンが酸化される場合には、ｊν化シリコン
の体積がポリシリコンの約２倍となるので、ポリシリコ
ン層１３の側壁の側壁酸化膜１３ｏは酸化の進行と共に
元の側壁の位置から外側へと伸びる。例えば、元の側壁
の位置から０．１μｍ（図のａ）まで酸化ｊ１はを伸ば
す場合にはポリシリコンの側壁は約０．１μｍが酸化に
消費され、側壁酸化膜ｉｓ、全膜厚すは約０．２μｍで
ある。Subsequently, as shown in FIG. 8, the substrate 11 is placed in a high-temperature oxidizing atmosphere, and the underlying polysilicon layer 13 is oxidized using the silicon nitride film 20 as a mask. At this time, the upper surface of the polysilicon layer 13 is not oxidized because it is covered with an oxidizing silicon nitride film 20.
Eventually, only the sidewalls of polysilicon layer 13 are oxidized. In addition, when polysilicon is oxidized, the volume of the jv silicon is approximately twice that of polysilicon, so the sidewall oxide film 13o on the sidewall of the polysilicon layer 13 moves away from the original sidewall position as the oxidation progresses. Extends outward. For example, when extending oxide j1 from the original sidewall position to 0.1 μm (a in the figure), about 0.1 μm of the polysilicon sidewall is consumed by oxidation, and the sidewall oxide film is, the total film thickness is It is approximately 0.2 μm.
次に、上記窒化シリコン膜２θおよびその下地のぼりシ
リコン層および側壁酸化膜１３０をマスクとしてひ素等
のＮ型不純物をイオン注入し、第１拡散層（高濃度拡散
層）１４．１５を形成する。Next, using the silicon nitride film 2θ, its underlying silicon layer, and sidewall oxide film 130 as a mask, N-type impurities such as arsenic are ion-implanted to form first diffusion layers (high concentration diffusion layers) 14 and 15.
以上のようにして、ダート電極１３Ｇ下のチャネル領域
を挾み第２拡散層１６．１７さらにその外側に第１拡散
層１４．１５を有するＬＤＤ構造のＭＯＳ トランジス
タ構造が得られ、以下通常のＭＯＳ トランジスタの製
造工程と同様の工程を行って所定の回路機能を有する装
置を完成する。In the above manner, an LDD structure MOS transistor structure is obtained which has a second diffusion layer 16.17 sandwiching the channel region under the dirt electrode 13G and a first diffusion layer 14.15 outside the second diffusion layer 16.17. A device having a predetermined circuit function is completed by performing steps similar to those for manufacturing a transistor.
この実施例によるＬＤＤ構造の素子では、第２拡散層１
６．１７の幅りが７Ｊ？ ＩＪシリコン層１３の側壁に
成長する酸化膜の元の側壁からの伸びの長さく第８図の
ａ）と、酸化工程やその他の熱工程における第１拡散層
１４．１５および第２拡散層１６．１７のチャネル側へ
の伸び具合とで決定される。ここで、側壁酸化膜１３ｏ
の元のポリシリコン層１３の側壁からの伸びは、ポリシ
リコン層１３の酸化時の温度、酸化時間、酸化種（雰囲
気の種類）によシ決定されるが、これらは容易に精度良
く制御することができる。In the LDD structure element according to this embodiment, the second diffusion layer 1
Is the width of 6.17 7J? The length of the oxide film grown on the sidewall of the IJ silicon layer 13 from the original sidewall is a) in FIG. .17 is determined by the degree of extension toward the channel side. Here, the sidewall oxide film 13o
The extension from the sidewall of the original polysilicon layer 13 is determined by the temperature, oxidation time, and oxidation species (type of atmosphere) during oxidation of the polysilicon layer 13, but these can be easily controlled with high precision. be able to.
また、低不純物濃度の第２拡散層１６．１７のみを特に
チャネル側に伸ばしたいときには、第ｌ拡散層１４．１
５のイオン注入による形成工程の前に、非酸化性雰囲気
中で適宜熱処理し、第２拡散層１６．１１を成長させれ
ばよく、これも制御性の高いものである。In addition, when it is desired to extend only the second diffusion layer 16.17 with a low impurity concentration particularly toward the channel side, the first diffusion layer 14.1
Before the formation step by ion implantation in step 5, the second diffusion layer 16.11 may be grown by appropriately performing heat treatment in a non-oxidizing atmosphere, which is also highly controllable.
上述のような方法の他に第９図に示すようにポリシリコ
ン層１３の側壁酸化膜１３ｏを窒化シリコン膜を被着し
ないで形成することも可能である。この場合には、半導
体基板１１のｙ −ト酸化膜１２上にポリシリコン層１
３を形成し、その上層に窒化シリコン膜を被着すること
なくパターニングする。その後、イオン注入を行って低
濃度の第２拡散層１６．１７を形成し、適宜アニール等
を行った後、上記ポリシリコン層１３の表面を酸化させ
、酸化膜１３１を形成する。In addition to the method described above, it is also possible to form the sidewall oxide film 13o of the polysilicon layer 13 without depositing a silicon nitride film, as shown in FIG. In this case, a polysilicon layer 1 is formed on the y-oxide film 12 of the semiconductor substrate 11.
3 is formed and patterned without depositing a silicon nitride film on top of the silicon nitride film. Thereafter, ion implantation is performed to form low concentration second diffusion layers 16 and 17, and after appropriate annealing and the like, the surface of the polysilicon layer 13 is oxidized to form an oxide film 131.
なお、この場合には、ポリシリコン層１３の側壁に側壁
酸化膜１３ｏが形成されるだけでなく上面も酸化され、
号？リシリコン層１３の膜厚（高さ）が薄くなシポリシ
リコン層１３からなる配線層やｆ−）電極の抵抗が上昇
するため、ポリシリコン層１３の膜厚を予め厚くしてお
くとよい。例えば、０．４μｍの厚さのポリシリコン層
１３を酸化させ元の側壁からの酸化膜の伸びＣを０．１
μｍとすると、酸化膜１３１の膜厚ｄは約０．２μｍで
、酸化膜１３１形成のために消費されるポリシリコン層
Ｉ３の膜厚は約０．１μｍであ）、ポリシリコン層１３
の膜厚は約（）、３μｍとなる。このときのポリシリコ
ン層１３の抵抗値はその上面が酸化されない場合に比ら
べて約１．３倍に上昇する。In this case, not only the sidewall oxide film 13o is formed on the sidewall of the polysilicon layer 13, but also the upper surface is oxidized.
issue? Since the resistance of the wiring layer and the f-) electrode made of the polysilicon layer 13 having a small thickness (height) of the polysilicon layer 13 increases, it is preferable to increase the thickness of the polysilicon layer 13 in advance. For example, when a polysilicon layer 13 with a thickness of 0.4 μm is oxidized, the extension C of the oxide film from the original sidewall is reduced to 0.1 μm.
μm, the film thickness d of the oxide film 131 is approximately 0.2 μm, and the film thickness of the polysilicon layer I3 consumed for forming the oxide film 131 is approximately 0.1 μm).
The film thickness is approximately (), 3 μm. At this time, the resistance value of polysilicon layer 13 increases approximately 1.3 times compared to when the upper surface thereof is not oxidized.
この後、上記酸化膜１３１で覆われたポリシリコン層１
３をマスクとして高不純物濃度の第１拡散層１４．１５
をイオン注入によ多形成し、以下引き続き通常の工程を
行って、装置を完成する。After this, the polysilicon layer 1 covered with the oxide film 131 is
3 as a mask, first diffusion layer 14.15 with high impurity concentration
is formed by ion implantation, followed by normal steps to complete the device.
この場合も、ポリシリコン層ノ３の表面に成長する酸化
膜１３１の膜厚を制御性良く設定でき、特性のばらつき
の小さいトランジスタを形成することができる。また、
前述の実施例と同様に生産性の低いＲＩＥ法を用いる必
要もなく、簡易に製造できる。In this case as well, the thickness of the oxide film 131 grown on the surface of the polysilicon layer 3 can be set with good controllability, and a transistor with small variations in characteristics can be formed. Also,
As with the previous embodiments, there is no need to use the RIE method, which has low productivity, and it can be manufactured easily.
以上のようにこの発明によれば、ダート電極となるポリ
シリコン層・ヤターンの酸化によシ、ＬＤＤ構造のソー
ス・ドレイン領域を精度良く設定でき、工程が簡素で製
造コストの低減された半導体装置の製造方法を提供する
ことができる。As described above, according to the present invention, the source/drain regions of the LDD structure can be set with high precision by oxidation of the polysilicon layer/layer that becomes the dart electrode, and the semiconductor device has a simple process and reduced manufacturing cost. A manufacturing method can be provided.
第１図乃至第３図は従来の半導体装置の製造方法を説明
する断面図、第４図および第５図は従来の半導体装置の
他の製造方法を説明する断面図、第６０乃至第８図はこ
の発明の一実施例に係る半導体装置の４・４造方法を説
明する断面図、第９図はこの発明の他の実施例を説明す
るための断面図である。
１ノ・・・半導体基板、１２・・・ダート酸化膜、１３
・・・号？リシリコン層、１３０・・・側壁酸化膜、１
３１・・・酸化膜、１３Ｇ・・・ダート電極、１４．１
５・・・第１拡散層、１６．１７・・・第２拡散層、２
０・・・窒化シリコン膜。1 to 3 are cross-sectional views explaining a conventional method for manufacturing a semiconductor device, FIGS. 4 and 5 are cross-sectional views explaining another conventional method for manufacturing a semiconductor device, and FIGS. 60 to 8 9 is a cross-sectional view for explaining a 4-4 manufacturing method of a semiconductor device according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view for explaining another embodiment of the present invention. 1 No... Semiconductor substrate, 12... Dirt oxide film, 13
···issue? Silicon layer, 130... Sidewall oxide film, 1
31...Oxide film, 13G...Dart electrode, 14.1
5... First diffusion layer, 16.17... Second diffusion layer, 2
0...Silicon nitride film.
Claims (2)
このダート酸化膜上にポリシリコン層を被着しノｆター
ニングすることによルトランゾスタの略チャネル領域上
にポリシリコン層の・母ターンを形成する工程と、この
ポリシリコン層をマスクとして上記半導体基板表面に上
記半導体基板と逆型の不純物をイオン注入し低’１％度
拡散層を形成する工程と、上記、ｒｃ： リシリコン層
のパターンの側壁を酸化°し側壁酸化膜を形成する工程
と、上記側壁酸化膜を備えたポリシリコン層をマスクと
して半導体基板と逆型の不純物のイオン注入を行ない上
記低濃度拡散層よシもチャネル領域から離間した部位に
上記低濃度拡散層よシも高不純物濃度の高濃度拡散層を
形成する工程とを具備したことを特徴とする半導体装置
の製造方法。(1) forming a dirt oxide film on the semiconductor substrate;
A process of depositing a polysilicon layer on the dirt oxide film and performing no-f turning to form a mother turn of the polysilicon layer approximately on the channel region of the transducer, and using this polysilicon layer as a mask, the semiconductor substrate is a step of ion-implanting impurities of the opposite type to the semiconductor substrate into the surface to form a low 1% diffusion layer; a step of oxidizing the sidewalls of the rc: silicon layer pattern to form a sidewall oxide film; Using the polysilicon layer with the sidewall oxide film as a mask, ions of an impurity of the opposite type to the semiconductor substrate are implanted, and high impurity impurities are implanted into the low concentration diffusion layer and the region spaced apart from the channel region. 1. A method of manufacturing a semiconductor device, comprising the step of forming a highly concentrated diffusion layer.
コン層のパターンの上部に耐酸化性部材を被着し、この
耐０化性部材をマスクとして上記ポリシリコン層を酸化
する工程であることを特徴とする特許請求の範囲第１項
に記載の半導体装置の製造方法。(2) The step of forming the sidewall oxide film is a step of depositing an oxidation-resistant material on top of the pattern of the polysilicon layer, and oxidizing the polysilicon layer using the zero-oxidation-resistant material as a mask. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9615783A JPS59220971A (en) | 1983-05-31 | 1983-05-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9615783A JPS59220971A (en) | 1983-05-31 | 1983-05-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59220971A true JPS59220971A (en) | 1984-12-12 |
Family
ID=14157519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9615783A Pending JPS59220971A (en) | 1983-05-31 | 1983-05-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59220971A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0197738A2 (en) * | 1985-03-29 | 1986-10-15 | Kabushiki Kaisha Toshiba | Method for manufacturing an LDD semiconductor device |
| JPS6230374A (en) * | 1985-07-31 | 1987-02-09 | Toshiba Corp | Semiconductor device |
| US4682404A (en) * | 1986-10-23 | 1987-07-28 | Ncr Corporation | MOSFET process using implantation through silicon |
| JPS6373667A (en) * | 1986-09-17 | 1988-04-04 | Sanyo Electric Co Ltd | Manufacture of mos semiconductor device |
| JPS63204654A (en) * | 1987-02-19 | 1988-08-24 | Sanyo Electric Co Ltd | Manufacture of mos-type semiconductor device |
| JPS63204653A (en) * | 1987-02-19 | 1988-08-24 | Sanyo Electric Co Ltd | Manufacture of mos-type semiconductor device |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
| US5476802A (en) * | 1991-08-26 | 1995-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming an insulated gate field effect transistor |
| US5612234A (en) * | 1995-10-04 | 1997-03-18 | Lg Electronics Inc. | Method for manufacturing a thin film transistor |
| US5679589A (en) * | 1989-10-17 | 1997-10-21 | Lucent Technologies Inc. | FET with gate spacer |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6259120B1 (en) | 1993-10-01 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
-
1983
- 1983-05-31 JP JP9615783A patent/JPS59220971A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0197738A2 (en) * | 1985-03-29 | 1986-10-15 | Kabushiki Kaisha Toshiba | Method for manufacturing an LDD semiconductor device |
| JPS6230374A (en) * | 1985-07-31 | 1987-02-09 | Toshiba Corp | Semiconductor device |
| JPS6373667A (en) * | 1986-09-17 | 1988-04-04 | Sanyo Electric Co Ltd | Manufacture of mos semiconductor device |
| US4682404A (en) * | 1986-10-23 | 1987-07-28 | Ncr Corporation | MOSFET process using implantation through silicon |
| JPS63204654A (en) * | 1987-02-19 | 1988-08-24 | Sanyo Electric Co Ltd | Manufacture of mos-type semiconductor device |
| JPS63204653A (en) * | 1987-02-19 | 1988-08-24 | Sanyo Electric Co Ltd | Manufacture of mos-type semiconductor device |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5679589A (en) * | 1989-10-17 | 1997-10-21 | Lucent Technologies Inc. | FET with gate spacer |
| US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
| US5476802A (en) * | 1991-08-26 | 1995-12-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming an insulated gate field effect transistor |
| US6489632B1 (en) | 1993-01-18 | 2002-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film |
| US6995432B2 (en) | 1993-01-18 | 2006-02-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions |
| US7408233B2 (en) | 1993-01-18 | 2008-08-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having N-channel thin film transistor with LDD regions and P-channel thin film transistor with LDD region |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6867431B2 (en) | 1993-09-20 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6259120B1 (en) | 1993-10-01 | 2001-07-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6777763B1 (en) | 1993-10-01 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for fabricating the same |
| US7166503B2 (en) | 1993-10-01 | 2007-01-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a TFT with laser irradiation |
| US5767530A (en) * | 1995-10-04 | 1998-06-16 | Lg Electronics Inc. | Thin film transistor with reduced leakage current |
| US5612234A (en) * | 1995-10-04 | 1997-03-18 | Lg Electronics Inc. | Method for manufacturing a thin film transistor |
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