JPS6033681U - digital clock correction circuit - Google Patents
digital clock correction circuitInfo
- Publication number
- JPS6033681U JPS6033681U JP10064084U JP10064084U JPS6033681U JP S6033681 U JPS6033681 U JP S6033681U JP 10064084 U JP10064084 U JP 10064084U JP 10064084 U JP10064084 U JP 10064084U JP S6033681 U JPS6033681 U JP S6033681U
- Authority
- JP
- Japan
- Prior art keywords
- correction switch
- time
- timer
- fast
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例によるデジタル時計の修正回
路を示す回路構成図、第２図は上記実施例の動作に供す
るフローチャート図、第３図及び第４図は第１図の動作
に供する各部のタイムチャート図である。
１・・・・・・アンドゲート、２・・・・・・２秒間タ
イマ、３・・・・・・インバータ、４・・・・・・マル
チバイブレータ、５・・・・・・ディレー回路、６・・
・・・・アンドゲート、７・・・・・・分カウンタ、７
ａ・・・・・・１位桁カウンタ、７ｂ・・・・・・Ｗ位
桁カウンタ、Ｓ・・・・・・分修正スイッチ。FIG. 1 is a circuit configuration diagram showing a correction circuit for a digital clock according to an embodiment of the present invention, FIG. 2 is a flowchart for the operation of the above embodiment, and FIGS. 3 and 4 are for the operation of FIG. 1. It is a time chart figure of each part provided. 1...AND gate, 2...2 second timer, 3...Inverter, 4...Multi-vibrator, 5...Delay circuit, 6...
...And gate, 7...Minute counter, 7
a: 1st digit counter, 7b: W digit counter, S: Minute correction switch.
Claims (1)
た設定時間を予め設定し、その設定時間を基にして前記
修正スイッチのオン操作時間に応じた出力を送出するタ
イマと、前記修正スイッチのオン操作時間が前記タイマ
の設定時間以内にあるとき該タイマの出力に基いてその
修正スイッチのオン操作毎にそれぞれ単一のパルスを発
生するパルス発生手段と、前記修正スイッチのオン操作
時間が前記タイマの設定時間以上にあるとき該タイマの
出力に基いてその修正スイッチのオン操作期間に相当す
る数の早送り信号を作成する早送り信号作成手段とを具
備し、前記パルス発生手段により発生される単一パルス
を修正すべきカウンタの一方の桁に送出するとともに、
前記早送り信号作成手段によって作成される早送り信号
を前記カウンタの他方の桁に送出して修正するようにし
たことを特徴とするデジタル時計の修正回路。a correction switch, a timer that presets a set time corresponding to the operation time of the correction switch and sends an output corresponding to the on-operation time of the correction switch based on the set time; and an on-operation of the correction switch. pulse generating means for generating a single pulse each time the correction switch is turned on based on the output of the timer when the time is within the set time of the timer; a fast-forward signal generating means for creating a fast-forward signal of a number corresponding to the on-operation period of the correction switch based on the output of the timer when the set time is exceeded, and a single pulse generated by the pulse generating means; is sent to one digit of the counter to be modified, and
A correction circuit for a digital timepiece, characterized in that the fast-forward signal created by the fast-forward signal creating means is sent to the other digit of the counter for correction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10064084U JPS6033681U (en) | 1984-07-05 | 1984-07-05 | digital clock correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10064084U JPS6033681U (en) | 1984-07-05 | 1984-07-05 | digital clock correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6033681U true JPS6033681U (en) | 1985-03-07 |
Family
ID=30237992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10064084U Pending JPS6033681U (en) | 1984-07-05 | 1984-07-05 | digital clock correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6033681U (en) |
-
1984
- 1984-07-05 JP JP10064084U patent/JPS6033681U/en active Pending
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