JPS60124136U - Control device - Google Patents
Control deviceInfo
- Publication number
- JPS60124136U JPS60124136U JP911384U JP911384U JPS60124136U JP S60124136 U JPS60124136 U JP S60124136U JP 911384 U JP911384 U JP 911384U JP 911384 U JP911384 U JP 911384U JP S60124136 U JPS60124136 U JP S60124136U
- Authority
- JP
- Japan
- Prior art keywords
- control device
- switching signal
- cpu
- output port
- frequency switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Predetermined Time Intervals (AREA)
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の一実施例を示すもので、第１図はブロッ
ク図、第２図は動作を示すフローチャート、第３図ａは
通常のクロック信号の波形図、同図すは周波数切換信号
の波形図、同図Ｃは周波数切換信号を入力したときのク
ロック信号の波形図である。
１・・・・・・ＣＰＵ、 １ ａ・・・・・・周波数切
換信号の出力ポート、２・・・・・・クロックジェネレ
ータ、４・・・・・・水−晶発振回路、５・・・・・・
デイバイダ。The drawings show an embodiment of the present invention, in which Fig. 1 is a block diagram, Fig. 2 is a flowchart showing the operation, Fig. 3a is a waveform diagram of a normal clock signal, and the same figure shows a waveform diagram of a frequency switching signal. Waveform diagram: C in the figure is a waveform diagram of the clock signal when the frequency switching signal is input. 1... CPU, 1 a... Frequency switching signal output port, 2... Clock generator, 4... Crystal oscillation circuit, 5...・・・・・・
Divider.
Claims (1)
ぞタイマ一時間を設定するようにした制御装置において
、前記ｃｐｕに周波数切換信号の出力ポートを設けると
共に、該出力ポートから周波数切換信号を入力したとき
にクロック信号の発振周波数を変更するクロックジェネ
レータを接続してなることを特徴とする制御装置。In a control device that uses an internal timer of a CPU of a microcomputer to set a timer for one hour, the CPU is provided with an output port for a frequency switching signal, and when the frequency switching signal is input from the output port, the clock is set to one hour. A control device characterized by being connected to a clock generator that changes the oscillation frequency of a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP911384U JPS60124136U (en) | 1984-01-27 | 1984-01-27 | Control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP911384U JPS60124136U (en) | 1984-01-27 | 1984-01-27 | Control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60124136U true JPS60124136U (en) | 1985-08-21 |
Family
ID=30489021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP911384U Pending JPS60124136U (en) | 1984-01-27 | 1984-01-27 | Control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60124136U (en) |
-
1984
- 1984-01-27 JP JP911384U patent/JPS60124136U/en active Pending
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