JPS60235446A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60235446A JPS60235446A JP9214084A JP9214084A JPS60235446A JP S60235446 A JPS60235446 A JP S60235446A JP 9214084 A JP9214084 A JP 9214084A JP 9214084 A JP9214084 A JP 9214084A JP S60235446 A JPS60235446 A JP S60235446A
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- semiconductor substrate
- vertical wiring
- wiring
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置およびその製造方法に関し、更に詳
しくは多層構造半導体集積回路およびその製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a multilayer semiconductor integrated circuit and a method for manufacturing the same.
多層構造半導体集積回路はトランジスタ、抵抗およびコ
ンデンサ等の機能素子が３次元的に配置された集積回路
で、機能素子が２次元的に配置されている従来の集積回
路に比べて集積度や回路規模の向上、配線長の短縮によ
る動作速度の高速化が期待できる。多層構造半導体集積
回路を実現する方法の１つに、機能素子を２次元的に配
置した従来の集積回路素子（以下能動層と称する）を個
別に製造し、これらの能動層を順に積層する方法が考え
られる。この方法によって多層構造半導体集積回路を実
現するためには前記能動層間の配線を行なう垂直配線を
前記能動層に設ける必要がある。また各能動層に設けら
れた垂直配線同士を接続する方法としては拡散溶接法等
があげられる。A multilayer semiconductor integrated circuit is an integrated circuit in which functional elements such as transistors, resistors, and capacitors are arranged three-dimensionally, and has a higher degree of integration and circuit scale than conventional integrated circuits in which functional elements are arranged two-dimensionally. It is expected that the operating speed will be increased due to improved performance and shorter wiring length. One method for realizing a multilayer semiconductor integrated circuit is to individually manufacture conventional integrated circuit elements (hereinafter referred to as active layers) in which functional elements are arranged two-dimensionally, and then stack these active layers in order. is possible. In order to realize a multilayer semiconductor integrated circuit using this method, it is necessary to provide vertical wiring in the active layer for wiring between the active layers. Further, as a method for connecting the vertical wirings provided in each active layer, a diffusion welding method and the like can be cited.
第１図から第３図は多層構造半導体集積回路の一例を断
面形状で示したものである、
第１図はゲート１０５、ソースおよびドレイン１０４゜
１０５からなるＭＯＳＦＥＴ、第１の垂直配線１０９、
水平配線１０７、第２の垂直配線１１０および金属バン
プ１１１が半導体基板１０１上に形成された構造の断面
形状の一例を示しだものである。１０２ 、１０３は半
導体基板１０１とＭＯＳＦＥＴおよび水平配線を絶縁す
る第１の絶縁膜および第２の絶縁膜である。１０８は表
面の保饅等を目的とした第３の絶縁膜である。FIGS. 1 to 3 are cross-sectional views of an example of a multilayer semiconductor integrated circuit.
It shows an example of a cross-sectional shape of a structure in which a horizontal wiring 107, a second vertical wiring 110, and a metal bump 111 are formed on a semiconductor substrate 101. 102 and 103 are a first insulating film and a second insulating film that insulate the semiconductor substrate 101, MOSFET, and horizontal wiring. 108 is a third insulating film for the purpose of preserving the surface.
第１図の構造を形成する方法の一例を簡単に述べる。ま
ずシリコン等の半導体基板１０１上に（至）法や熱酸化
法を用いて二酸化シリコン等の第１の絶縁膜１０２を形
成する。次に第１の絶縁膜１０２の表面にゲート１０６
、ソースもしくはドレイン１０４゜１０５から成るＭＯ
ＳＦＥＴを通常の方法で形成する。An example of a method for forming the structure shown in FIG. 1 will be briefly described. First, a first insulating film 102 made of silicon dioxide or the like is formed on a semiconductor substrate 101 made of silicon or the like by using a thermal oxidation method or a thermal oxidation method. Next, a gate 106 is formed on the surface of the first insulating film 102.
, source or drain 104°105
The SFET is formed in a conventional manner.
この後、（至）法等を用いて二酸化シリコン等の第２の
絶縁層１０３を形成する。次に、第１の絶縁層１０２お
よび第２の絶縁層１０３の一部分を開口し、続けてその
開口部の＃−導体基板１０１を所望の深さ、例えば約１
μｍの深さになるまでエツチングする。Thereafter, a second insulating layer 103 made of silicon dioxide or the like is formed using a method or the like. Next, a portion of the first insulating layer 102 and the second insulating layer 103 is opened, and then the #-conductor substrate 101 in the opening is moved to a desired depth, for example, about 1
Etch to a depth of μm.
半導体基板１０１がシリコンの場合、通常のエツチング
法、例えば硝酸、万邦酸等の混合液によるウェットエツ
チング法や四塩化炭素ガス等によるドライエツチング法
を使用すれば、半導体基板１０１がエツチングされた断
面形状はほぼ長方形になる。If the semiconductor substrate 101 is made of silicon, the cross-sectional shape of the semiconductor substrate 101 can be etched by using a normal etching method, for example, a wet etching method using a mixed solution of nitric acid, pernicious acid, etc., or a dry etching method using carbon tetrachloride gas, etc. is almost rectangular.
この後、該開口部および半導体基板１０１がエツチング
された領域にアルミニウム等の導電材料を埋め込み、第
１の垂直配線１０９を形成する。更に、アルミニウム等
の水平配線１０７および二酸化シリコン等の第３の絶縁
層１０８を形成する。最後に、水平配線１０７上の第３
の絶縁層１０８ｆ、開口し、該第３の絶縁層１０８の開
口部にアルミニウム等の導電材料を理め込み第２の垂直
配線１１０、並びに金等の金属パン１１１１す形成する
。金ｋＡバンプ１１１は拡散溶接を容易にするために設
けられているが、必ずしも必要でｆ、（い。第１図に示
した構造において半導体基板１０１をエツチングにより
除去すれば。Thereafter, a conductive material such as aluminum is buried in the opening and the etched region of the semiconductor substrate 101 to form a first vertical wiring 109. Further, a horizontal wiring 107 made of aluminum or the like and a third insulating layer 108 made of silicon dioxide or the like are formed. Finally, the third line on the horizontal wiring 107
The insulating layer 108f is opened, and a conductive material such as aluminum is injected into the opening of the third insulating layer 108 to form a second vertical wiring 110 and a metal pan 1111 made of gold or the like. Although the gold kA bumps 111 are provided to facilitate diffusion welding, they are not necessarily necessary (if the semiconductor substrate 101 is removed by etching in the structure shown in FIG. 1).
多層構造集積回路の能動Ｊｆ１が形成される。以下、こ
れを第１の能動層と称する。第２図は第１の能動層と同
じ工程を経て形成された第２の能動層の断面図である。Active Jf1 of the multilayer integrated circuit is formed. Hereinafter, this will be referred to as the first active layer. FIG. 2 is a cross-sectional view of the second active layer formed through the same process as the first active layer.
第１図と同じ機能あるいは同じ構造のを素は第１図の要
素番号の３桁目を１から２に変更して示されている。例
えば第１の能動層の２０２に対応する。＃ｒ’！ ３図
は第１の能動層上に第２の能動層を積層し７た２層ｔＭ
造半尋体集積回路の断面図である。１を↓１ｖ・１間の
絶縁性充填剤で、接着機能を持つポリイミド系伺朋を用
いれば拮強剤として使用できるし、ダイヤモンド薄膜を
用いれば放熱層としても利用できる。Elements having the same function or structure as in FIG. 1 are shown with the third digit of the element number in FIG. 1 changed from 1 to 2. For example, it corresponds to 202 of the first active layer. #r'! Figure 3 shows a two-layer tM in which the second active layer is laminated on the first active layer.
FIG. 2 is a cross-sectional view of a half-sized integrated circuit. It is an insulating filler between 1 and 1 V and 1, and if a polyimide resin with adhesive function is used, it can be used as an antagonist, and if a diamond thin film is used, it can also be used as a heat dissipation layer.
第１の能動層の金ｈバンプ１１１と第２の能動層の第１
の垂直配線２０９を接続する方法に拡散溶接法がある。The gold h-bumps 111 of the first active layer and the first
Diffusion welding is a method for connecting the vertical wiring 209.
拡散溶接法は３００℃前後に加熱した２種類、あるいは
同種の金Ｓの接触面に圧力を加え、接触面での両金用分
子の拡散によシ接着させる方法で、他の接着法例えば導
電接着剤を用いる方法や、ハンダ等の低融点全組を溶か
して接着させる方法に比べて接着部の電気抵抗が小さい
、做細パターンの接着も可能である、接着力が強い、等
の特徴がある。一方、拡散溶接法の最大の欠点は接着さ
せる２つの金８３の接触面に有機物等の汚れ股や酸化膜
などが存在すると拡散浴接が著しく阻害されることであ
る。ところが、現実には洗浄等を田【八で １１．曲目
−祐ｈ ｉａｖ外官ｋに鈴ホで為 か１八 ネスいはア
ルミニウム等の様な金属の場合、表面が酸化されやすい
等の問題があり、最良の状態で拡散溶接することは実際
上節しい。従来、集積回路チップをパッケージやチップ
キャリア等に組み立てる場合に使用していた拡散溶接法
では、これらの問題を解決するため拡散溶接に必＠な圧
力以上の大きな圧力を加えて、接着する材料の一方ある
いは両方に塑性変形を与え、この結果接触面に発生する
すべり応力で前記汚れ膜や酸化膜を破壊、除去していた
。第３図の様な第２の能動層の円柱状あるいは角柱状の
第１の垂直配線２０９と第１の能動層の金属バンプ１１
１間の拡散溶接を例にとると、第２の垂直配線２０９と
金属バンプ１１１の界面にかける圧力は、該界面で第２
の垂直配線２０９、金属バンプ１１１の両者もしくは一
方が塑性変形する圧力である・例えは第２の垂直配線２
０９にアルミニウムを使用する場合、塑性変形に必要な
圧力はアルミニウムの硬度から計算すると２０ｋｇ／Ｉ
ＩＩＩＩ＋２以上である。仮に第２の垂直配線２０９の
サイズがｌｏＸｌｏμｍで、ｌチップ当り１０，０００
個存在するとすると、拡散溶接面積は１７７−となるか
ら、このような場合、第１および第２の能動層を接着す
るのに必要な圧力は２０ｋｇ以上となる。ところが、第
３図に示した構造では第２の能動層の厚さがせいぜい数
ミクロンで非常に薄いから、先に示した圧力では第２の
垂直配線２０９あるいは金帆バ／プ１１１が塑性変形す
ると同時に、第２の能動層も破壊される恐れがある・
〔発明の目的〕
本発明はこれらの事情を考慮し、拡散溶接時に加える圧
力を減らすことが可能な第２の能動層の第１の垂直配線
の構造およびその製造方法を提供するものである。Diffusion welding is a method in which pressure is applied to the contact surfaces of two types of gold or the same type of gold S heated to around 300°C, and the two types of gold S are bonded by diffusion of the gold molecules at the contact surfaces. Compared to methods that use adhesives or methods that melt and bond all components with low melting points such as solder, this method has the following characteristics: the electrical resistance of the bonded part is lower, it is possible to bond fine patterns, and the adhesive strength is strong. be. On the other hand, the biggest drawback of the diffusion welding method is that the presence of dirt such as organic substances or oxide films on the contact surfaces of the two pieces of gold 83 to be bonded significantly impedes diffusion welding. However, in reality, cleaning, etc. is difficult. Song - Yu h iav foreign official k ni suzuho de tame ka 18 In the case of metals such as aluminum, there are problems such as the surface being easily oxidized, so it is practically impossible to perform diffusion welding under the best conditions. Nostalgic. Diffusion welding, which has been traditionally used to assemble integrated circuit chips into packages, chip carriers, etc., solves these problems by applying pressure greater than the pressure required for diffusion welding to reduce the strength of the materials to be bonded. Plastic deformation is applied to one or both, and the resulting sliding stress generated on the contact surface destroys and removes the dirt film or oxide film. The cylindrical or prismatic first vertical wiring 209 of the second active layer and the metal bump 11 of the first active layer as shown in FIG.
Taking diffusion welding between 1 and 1 as an example, the pressure applied to the interface between the second vertical wiring 209 and the metal bump 111 is
This is the pressure that causes plastic deformation of both or one of the vertical wiring 209 and the metal bump 111.For example, the second vertical wiring 2
When using aluminum for 09, the pressure required for plastic deformation is 20 kg/I calculated from the hardness of aluminum.
III+2 or higher. Suppose that the size of the second vertical wiring 209 is loXloμm and 10,000 wires per l chip.
If there are two active layers, the diffusion welding area will be 177 -, so in such a case, the pressure required to bond the first and second active layers will be 20 kg or more. However, in the structure shown in FIG. 3, the thickness of the second active layer is very thin, a few microns at most, so the pressure shown above causes the second vertical wiring 209 or the gold plate 111 to undergo plastic deformation. At the same time, the second active layer may also be destroyed. [Objective of the Invention] Taking these circumstances into consideration, the present invention has developed a first active layer of the second active layer that can reduce the pressure applied during diffusion welding. The present invention provides a vertical wiring structure and a manufacturing method thereof.
本発明はトランジスタ、抵抗素子、コンデンサ等の機能
素子およびこれらの機能素子間を接続する水平配線があ
らかじめ同一平面上に形成されている能動層が、各能動
層に設けられている垂直配線同士を拡散溶接法で接続す
る方法を用いて順に積層される多層構造半導体集積回路
において、第１の能動層に設けられた垂直配線のうち、
該第１の能動層に隣接する第２の能動層に設けられた垂
直配線と接触する部分の断面形状を三角形あるいは台形
としたことを特徴とする半導体装置およびトランジスタ
、抵抗素子、コンデンサ等の機能素子およびこれらの機
能素子間を接続する水平配線があらかじめ同一平面上に
形成されている能動層が、各能動層に設けられている垂
直配線同志を拡散溶接法で接続する方法を用いてＩＥｔ
Ｋ積層される多層構造半導体集積回路の各能動層を形
成する製造方法において、半導体基板表面上に前記機能
素子を形成する工程、前記機能素子が形成されていない
前記半導体基板表面上の絶縁膜に開口部を設け、該開口
部の半導体基板を該開口部の面積より底面の面積が小さ
くなる様なエツチング法を用いて該開口部の半導体基板
に江みを形成した後、該開口部および該ｕ′、みに導電
材料を埋め込むことにより垂直配線を形成する工程、お
よび前記水平配線を形成する工程を行なった後、前ｉ己
半導体゛基板表面上に形成された機能素子、水平配線、
および垂直配線を残した状態で前記半導体基板裏面から
半導体基板をエツチングにより除去し、該垂直配線を裏
面から飛び出させると共に、該飛び出ている領域の断面
形状を三角形あるいは台形とすることを特徴とする半導
体装置の製造方法である。In the present invention, an active layer in which functional elements such as transistors, resistive elements, and capacitors, and horizontal wiring connecting these functional elements are formed in advance on the same plane, connects vertical wiring provided in each active layer. In a multilayer semiconductor integrated circuit that is sequentially stacked using a diffusion welding method, among the vertical wirings provided in the first active layer,
Functions of semiconductor devices, transistors, resistive elements, capacitors, etc., characterized in that the cross-sectional shape of the portion that contacts the vertical wiring provided in the second active layer adjacent to the first active layer is triangular or trapezoidal. An active layer in which elements and horizontal wiring connecting between these functional elements are formed in advance on the same plane is IEt by using a method of connecting vertical wiring provided in each active layer using a diffusion welding method.
In a manufacturing method for forming each active layer of a multilayer semiconductor integrated circuit in which K is stacked, the step of forming the functional element on the surface of the semiconductor substrate, the step of forming the functional element on the surface of the semiconductor substrate on which the functional element is not formed, After forming an opening in the semiconductor substrate of the opening and forming a recess in the semiconductor substrate of the opening using an etching method such that the area of the bottom surface is smaller than the area of the opening, the semiconductor substrate of the opening and the After performing the step of forming a vertical wiring by embedding a conductive material in the surface of the semiconductor substrate and the step of forming the horizontal wiring, the functional elements, horizontal wiring, and
The semiconductor substrate is removed by etching from the back surface of the semiconductor substrate with the vertical wiring remaining, and the vertical wiring is made to protrude from the back surface, and the cross-sectional shape of the protruding region is triangular or trapezoidal. This is a method for manufacturing a semiconductor device.
以下、図面を用いながら本発明の実施例を詳細に説明す
る。第４図は第２図に相当する本発明の第１実施例を示
す図である。第２図の要素と全く同じ構造の部分は同一
番号で示されている。第１の垂直配線２２０の先端２２
１の断面形状は三角形になっているが、実際には第１の
絶縁膜２０２の開口部形状が円形の場合は円錐状、正方
形の場合は角錐状である。第４図に示した第２の能動層
を第１図に示した第１の能動層上に積層する場合を考え
る。最初、圧力をかけない場合、第１の垂直配線２２０
の先端２２１と金属バンプ（１１１）の表面が接触して
いる。従って、この後わずかな圧力をかけても先端２２
１の部分に圧力が全て集中するから、この部分に大きな
圧力が加わり、第１の垂直配線ｍもしくは全組バンプ（
１１１）が容易に塑性変形する。Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a diagram showing a first embodiment of the present invention corresponding to FIG. 2. Parts of identical structure to elements of FIG. 2 are designated with the same numerals. Tip 22 of first vertical wiring 220
1 has a triangular cross-sectional shape, but in reality, when the opening shape of the first insulating film 202 is circular, it is conical, and when it is square, it is pyramidal. Consider the case where the second active layer shown in FIG. 4 is laminated on the first active layer shown in FIG. 1. Initially, when no pressure is applied, the first vertical wiring 220
The tip 221 of the metal bump (111) is in contact with the surface of the metal bump (111). Therefore, even if a slight pressure is applied after this, the tip 22
Since all the pressure is concentrated in part 1, a large pressure is applied to this part, and the first vertical wiring m or all the bumps (
111) is easily plastically deformed.
従って、前記汚れ膜や酸化膜が破壊され拡散溶接が行な
われるようになる。例えば第１の垂直配線２２０にアル
ミニウムを、金妨バンブ１１１に金を使用した場合、２
〜３にハｍ２の圧力を加え、３００℃に加熱すれば拡散
溶接が起こり、第１の能動層の第２の垂直配線１１０上
の金酋バンプ１１１と、第２の能動層の第１の垂直配線
が接続される、この圧力は第２図に示した円柱あるいは
角柱状の第１の垂直配線２０９を全屈バンブ１１１上に
拡敬ＲＺ接する場合の約１／１ｏである。Therefore, the dirt film and oxide film are destroyed and diffusion welding is performed. For example, if aluminum is used for the first vertical wiring 220 and gold is used for the gold interference bump 111,
By applying a pressure of Ham2 to ~3 and heating it to 300°C, diffusion welding occurs, and the gold plated bump 111 on the second vertical wiring 110 of the first active layer and the first The pressure at which the vertical wiring is connected is about 1/1o of the pressure when the first vertical wiring 209 in the shape of a cylinder or a prism shown in FIG.
第５図は第２図に相当する第２の実施例金示す図である
。第２図の４１・ｙ成要素と全く同じ構造の部分は同一
番号で示しである。第１の垂直配線２３０の先端２３１
の断面形状は台形になっているが、実際には第１の絶縁
膜２０２の開口部形状が円形のｊ・ゝ−１）合、円錐台
状、正方形の場合は角錐台状である。FIG. 5 is a diagram showing a second embodiment corresponding to FIG. 2. Portions having exactly the same structure as the 41.y component in FIG. 2 are designated by the same numbers. Tip 231 of first vertical wiring 230
The cross-sectional shape of the opening of the first insulating film 202 is a trapezoid, but in reality, if the opening shape of the first insulating film 202 is circular, it is a truncated cone, and if it is square, it is a truncated pyramid.
第５図に示した第２の能動層を第１図に示した第１の能
動層上に積層する場合を考える。最初、′圧力をかけな
い場合、第１の垂直配線２３０の先端２３１と金属バン
プ１１１の表面とが接触している。この接触面積は先端
２３１の面積と等しいから、第１の垂直配線２３０ある
いは金属バンプ１１１が塑性変形を起こすだめに必要な
圧力は、第２図に示されたような断面形状が長方形の第
１の垂直配線２０９の場合に比べて小さくなる。例えば
先端２３１の面積が第１の絶縁ル（２０２の開口部の面
積の１７４であるとすると、塑性変形に必要な圧力も１
／４に減少する。従って、第５図に示した様な構造の第
２の能動層を第１の能動層上に積層する時、第２図に示
した第２の能動層の場合に比べて拡散溶接時の圧力を下
げることができる、
以上示しだ２ ｅｆｉ Ｅｆｔの実施例でわかる様に、
第２の能動層に設けられる第１の垂直配線が圧力をかけ
る前に第１の能動層の金４バンプと接触する部分の面積
が第２の能動層の第１の絶縁膜の開口部の開口面積より
小さくすれば、拡散溶接時の圧力を下げることができる
、したがって、第４図や第５図に示した第１の垂直配線
先端部の断面形状、すなわち三角形あるいは台形に代え
てのこぎりの歯のような繰り返し形状を第１の垂直配ｆ
ｌ’ｆｌ先端部の断面形状に用いても同様な効果をｆｆ
）ることかできる。Consider the case where the second active layer shown in FIG. 5 is laminated on the first active layer shown in FIG. Initially, when no pressure is applied, the tip 231 of the first vertical wiring 230 and the surface of the metal bump 111 are in contact with each other. Since this contact area is equal to the area of the tip 231, the pressure necessary to cause plastic deformation of the first vertical wiring 230 or the metal bump 111 is the same as that of the first vertical wiring 230 or the metal bump 111 having a rectangular cross section as shown in FIG. The vertical wiring 209 is smaller than that of the vertical wiring 209. For example, if the area of the tip 231 is 174 times the area of the opening of the first insulator (202), the pressure required for plastic deformation is also 1.
/4. Therefore, when the second active layer having the structure shown in FIG. 5 is laminated on the first active layer, the pressure during diffusion welding is higher than in the case of the second active layer shown in FIG. As can be seen from the example of 2 efi Eft shown above,
The area of the portion where the first vertical wiring provided in the second active layer contacts the gold 4 bump of the first active layer before applying pressure is the area of the opening of the first insulating film of the second active layer. If the area is smaller than the opening area, the pressure during diffusion welding can be lowered. Therefore, the cross-sectional shape of the first vertical wiring tip shown in FIGS. A tooth-like repeating shape is placed in the first vertical arrangement.
A similar effect can be obtained by using the cross-sectional shape of the tip of l'fl.
) can be done.
以下、本発明による第２の能動層に設けられる第１の垂
直配線の形成力法を詳細に示す。第６図から第１２図は
、第４図に示す構造を実現するだめの製造方法を工程に
従い断面形状を示しだものである。第６図は例えば面方
位が（ｉｏｏ）のシリコン等の半導体基板５０１上に二
酸化シリコン等の絶縁膜５０２を形成したものである。Hereinafter, a method for forming the first vertical wiring provided in the second active layer according to the present invention will be described in detail. 6 to 12 show cross-sectional shapes according to the steps of the manufacturing method for realizing the structure shown in FIG. 4. In FIG. 6, for example, an insulating film 502 made of silicon dioxide or the like is formed on a semiconductor substrate 501 made of silicon or the like having a (ioo) plane orientation.
なお、５０２ ハ第４図に示された第１絶縁膜２０２お
よび第２の絶縁層２０３に相当する絶縁層である。１だ
、第６図に示されていない領域にＭＯＳＦＥＴ等の機能
素子が既に形成されていてもかまわない。次に、第７図
に示すように、第１の垂直配線が設けられる部分の絶縁
層５０２の一部を開口する。絶縁層５０２が二酸化シリ
コンの場合に、その開口法として、写真食刻法でパター
ニングしたフォトレジストをマスクとするバッフアート
硝酸等を用いたウェットエツチングや四＾外化炭素系ガ
ス等を用いたドライエツチングが知られ−〔いる。次に
第７図の構造をヒドラジンや水酸化カリウム灯のＲｉ液
の様な面方位（１００）のシリコン結晶面のエツチング
速度が面方位（１１１）のシリコン納品面のエツチング
速度に比べて十分速い異方性エツチング液に浸すと、第
８図に示すように、開口部５０３の”ｒ２１Ｘ分のシリ
コン基板が約３５゜の傾斜角５０５を持つ逆台形状にエ
ツチングされ、好み５０４が形成される、更にエツチン
グを継続すれば第９図に示すように…ｆ面形状が逆三角
形状のトドみ５０６が形成されてシリコン基板５０１の
エツチングが殆ど停止する。この後、第１θ図に示す様
に絶縁層５０２の開口部５０３および５０６内にアルミ
ニウム等の導電材料を埋め込み第１の垂直配線５０７を
形成した後、水平配線５０８を形成する。第１の垂直配
線５０７は第４図の２２０に相当し、その形成力法の一
例を以下に示す。Note that 502 C is an insulating layer corresponding to the first insulating film 202 and the second insulating layer 203 shown in FIG. 1. It does not matter if a functional element such as a MOSFET is already formed in a region not shown in FIG. Next, as shown in FIG. 7, a portion of the insulating layer 502 where the first vertical wiring is to be provided is opened. When the insulating layer 502 is made of silicon dioxide, the opening method may be wet etching using buffered nitric acid or the like using a photoresist patterned by photolithography as a mask, or dry etching using external carbon gas or the like. Etching is known. Next, the structure shown in Figure 7 can be etched using hydrazine or Ri solution from a potassium hydroxide lamp, where the etching rate of the silicon crystal plane with the plane orientation (100) is sufficiently faster than the etching rate of the silicon delivered plane with the plane orientation (111). When immersed in the anisotropic etching solution, as shown in FIG. 8, the silicon substrate corresponding to "r21X" of the opening 503 is etched into an inverted trapezoidal shape with an inclination angle 505 of about 35 degrees, forming a pattern 504. If the etching is continued further, as shown in FIG. 9, a groove 506 with an inverted triangular f-plane shape is formed, and the etching of the silicon substrate 501 is almost stopped.After this, as shown in FIG. After forming a first vertical wiring 507 by filling a conductive material such as aluminum into the openings 503 and 506 of the insulating layer 502, a horizontal wiring 508 is formed.The first vertical wiring 507 corresponds to 220 in FIG. An example of the forming force method is shown below.
まず、第９図の構造の表面にスパッタ法等を用いてアル
ミニウム等の導電材料膜を形成する。この導電材料膜の
膜厚は開口部５０３および窪み５０６の探さに等しいこ
とが好ましいが、必ずしもこれに限らない。この後、フ
ォトレジスト等をスピン塗布する、この結果、開口部５
０３および窪み５０６の領域のフォトレジストの膜厚が
他の部分に比べて厚くなる。したがって一様に前記フォ
トレジストを酸素プラズマ灰化等の方法で一様にエツチ
ングすれば開口部５０３およびＥ（み５０６の領域にの
みフォトレジストが残った状態で他の部分のフォトレジ
ストが除去される。最後に開口部５０３および窪み５０
６の領域に残っているフォトレジストヲマスクとしてア
ルミニウム等の前記導電材料を四塩化炭素ガスによるド
ライエツチング等の手法を用いてエツチングすれば、開
口部５０３および窪み５０６の領域に選択的にアルミニ
ウム等の導電材料が埋め込まれ、第１の垂直配線５０７
が形成される。なお、第１の垂直配線５０７を形成する
直前に第１の垂直配線５０７と基板５０１とを隔てる薄
い二酸化シリコン等の絶縁層を形成してもかまわない。First, a film of a conductive material such as aluminum is formed on the surface of the structure shown in FIG. 9 using a sputtering method or the like. The thickness of this conductive material film is preferably equal to the thickness of the opening 503 and the depression 506, but is not necessarily limited to this. After this, a photoresist or the like is spin-coated, and as a result, the opening 5
The film thickness of the photoresist in the regions 03 and 506 is thicker than in other parts. Therefore, if the photoresist is uniformly etched using a method such as oxygen plasma ashing, the photoresist in other parts will be removed with the photoresist remaining only in the openings 503 and E (506). Finally, the opening 503 and the depression 50
If the conductive material such as aluminum is etched as a mask for the photoresist remaining in the area 6 using a method such as dry etching using carbon tetrachloride gas, aluminum etc. will be selectively etched in the area of the opening 503 and the depression 506. conductive material is embedded, and the first vertical wiring 507
is formed. Note that immediately before forming the first vertical wiring 507, a thin insulating layer such as silicon dioxide may be formed to separate the first vertical wiring 507 and the substrate 501.
水平配線５０８は第４図の２０７に相当し、通常の集積
回路に用いられるアルミニウム等の配線である。次に第
１１図に示すように表面に二酸化シリコン等の絶縁膜５
０９を形成し、しかる後、該絶縁膜５０９の一部分を開
口し、成膜５０９の開口部にアルミニウム等の導電材料
を埋め込み、第２の垂直配線５１０を形成し、更に金等
の金属バンブ５１１を形成する。The horizontal wiring 508 corresponds to 207 in FIG. 4, and is a wiring made of aluminum or the like used in ordinary integrated circuits. Next, as shown in FIG. 11, an insulating film 5 of silicon dioxide, etc.
After that, a part of the insulating film 509 is opened, a conductive material such as aluminum is buried in the opening of the film 509, a second vertical wiring 510 is formed, and a metal bump 511 of gold or the like is formed. form.
金等の金属バンプ５１１の形成方法の一例としては、全
面にスパッタ法で形成した金膜を写真食刻法でパターニ
ングしたフォトレジストをマスクとするヨウ素系のエツ
チング液等を用いたウェットエツチング法やイオンミー
リング等のドライエツチング法等がある。最後に、半導
体基板５０１を除去すれば第１２図の構造となる。例え
ば半導体基板５０１がシリコン基板の場合、硝酸、万昇
酸、酢酸の容積比を５：３：５に選び室温で攪拌しなが
らエツチングすると毎分２〜３μｍの速さでシリコン基
板がエツチングされる。この結果得られた第１２図に示
す構造は第４図の左半分と同じ構造となる。なお、第８
図の状態で前記異方性エツチングを中止し、第１θ図以
後の工程を行なえば、第５図のような構造にすることも
可能である、
以上の説明は面方位が（ｉｏｏ）のシリコン基板を中心
に説明を行なったが、シリコン基板の面方位を（１１１
）以外に選べば傾斜角５０５は変化するが同様な構造が
得られる。また、第７図に示した開口部５０３の断面形
状をＶ状とし、ドライエツチング技術を用いれば、第８
図あるいは第９図に示したような半導体基板５０１に形
成する凹部５０５および５０６を形成することも可能で
ある。An example of a method for forming the metal bumps 511 made of gold or the like is a wet etching method using an iodine-based etching solution using a photoresist as a mask, which is a gold film formed by sputtering on the entire surface and patterned by photoetching. There are dry etching methods such as ion milling. Finally, if the semiconductor substrate 501 is removed, the structure shown in FIG. 12 will be obtained. For example, if the semiconductor substrate 501 is a silicon substrate, the silicon substrate will be etched at a rate of 2 to 3 μm per minute by selecting a volume ratio of nitric acid, 30% acid, and acetic acid to 5:3:5 and performing etching while stirring at room temperature. . The resulting structure shown in FIG. 12 is the same as the left half of FIG. 4. In addition, the 8th
If the anisotropic etching is stopped in the state shown in the figure and the steps after Figure 1θ are performed, it is possible to obtain the structure shown in Figure 5. Although the explanation focused on the substrate, the plane orientation of the silicon substrate is (111
), the same structure can be obtained although the inclination angle 505 changes. Moreover, if the cross-sectional shape of the opening 503 shown in FIG. 7 is made V-shaped and dry etching technology is used,
It is also possible to form recesses 505 and 506 in a semiconductor substrate 501 as shown in the figure or in FIG.
以上述べた様に、本発明を用いれば各能動層に設けられ
る垂直配線を拡散溶接で接続し７た多層構造半導体集積
回路を実現する上で拡散溶接に必要な圧力が小さい第１
の垂直配線の構造を得ることができる。As described above, if the present invention is used, the vertical wiring provided in each active layer can be connected by diffusion welding to realize a multilayer semiconductor integrated circuit, and the pressure required for diffusion welding is low.
vertical wiring structure can be obtained.
本発明を説明するに当り使用した基板材オ」、絶縁膜や
導電材料、エツチング液等は一例を示しだものであって
、必ずしもこれに限るものでない。The substrate materials, insulating films, conductive materials, etching solutions, etc. used in explaining the present invention are merely examples, and are not necessarily limited to these.
また、第１図から第５図に示しだ構造、例えば、ＭＯＳ
ＦＥＴの構造や多層構造半導体集積回路も薄膜構造のＭ
ＯＳＦＥＴとして示されているが、通常の半導体基板上
に形成された］！１１０８ＦＥＴやバイポーラトランジ
スタ等を含むものでもかまわない。In addition, the structures shown in FIGS. 1 to 5, for example, MOS
The structure of FETs and multilayer semiconductor integrated circuits are also thin film structures.
Although shown as an OSFET, it was formed on a regular semiconductor substrate]! It may also include a 1108 FET, a bipolar transistor, or the like.
第１図から第３図は多層構造半導体集積回路を示し、第
１図は第１の能動層の断面図、第２図は第１の能動層か
ら半導体基板を除去して薄膜化した第２の能動層の断面
図、第３図は第１の能動層の上に第２の能動層を積層し
た２層構造半導体集積回路である。
第４図、第５図は本発明の第１実施例、および８ｇ２の
実廁例を示すもので、いずれも第２の能動層の断面図、
第６Ｎからｉ、ｇ１２図は本発明による製造方法の一例
で、第４図に示した第２の能動層の垂直配線部分、即ち
、左半分の領域を製造する１怪１−に示す図である。
ｌ・・・絶縁性充填剤、１０１・・・半導体基板、１０
９・・・第１の能動層の第１の垂直配線、２２０ 、２
３０・・・第２能動層の第１の垂直配線、５０１・・・
半導体基板、５０２・・・絶縁層、５０３・・・開口部
、５０６・・・注み、５０７・・・第１の垂直配線、５
０８・・・水平配線、５０９・・・絶縁膜、５１０ ・
第２の垂直配線、５１１・・・金同バンプ第１図
第３図
第４図
第５図
第６図
第７図
第Ｆ３図
第９図
第１０図1 to 3 show a multilayer structure semiconductor integrated circuit, FIG. 1 is a cross-sectional view of the first active layer, and FIG. 2 is a cross-sectional view of the second active layer, which is thinned by removing the semiconductor substrate from the first active layer. The cross-sectional view of the active layer in FIG. 3 shows a two-layer structure semiconductor integrated circuit in which a second active layer is laminated on a first active layer. 4 and 5 show the first embodiment of the present invention and an actual example of 8g2, both of which are cross-sectional views of the second active layer,
Figures 6N to i, g12 show an example of the manufacturing method according to the present invention. be. l... Insulating filler, 101... Semiconductor substrate, 10
9...first vertical wiring of first active layer, 220, 2
30...First vertical wiring of second active layer, 501...
Semiconductor substrate, 502... Insulating layer, 503... Opening, 506... Pour, 507... First vertical wiring, 5
08... Horizontal wiring, 509... Insulating film, 510 ・
Second vertical wiring, 511... Gold bumps Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure F3 Figure 9 Figure 10
Claims (2)
子およびこれらの機能素子間を接続する水平配線があら
かじめ同一平面上に形成されている能動層が、各能動層
に設けられている垂直配線同志を拡散溶接法で接続する
方法を用いて順に積層される多層構造半導体集積回路に
おいて、第１の能動層に設けられた垂直配線のうち、該
第１の能動層に隣接する第２の能動層に設けられた垂直
配線と接触する部分の断面形状を三角形あるいは台形と
したことを特徴とする半導体装置。(1) An active layer in which functional elements such as transistors, resistive elements, capacitors, and horizontal wiring connecting these functional elements are formed in advance on the same plane, connects vertical wiring provided in each active layer. In a multilayer semiconductor integrated circuit that is sequentially stacked using a connection method using diffusion welding, among the vertical wiring provided in the first active layer, a second active layer adjacent to the first active layer is connected. A semiconductor device characterized in that a cross-sectional shape of a portion that contacts a provided vertical wiring is triangular or trapezoidal.
子およびこれらの機能素子間を接続する水平配線があら
かじめ同一平面上に形成されている能動層が、各能動層
に設けられている垂直配線同士を拡散溶接法で接続する
方法を用いて順に積層さ打ム名層椹浩半遵体駆積回路の
各能動層を形成する製造方法において、半導体基板表面
上に前記機能素子を形成する工程、前記機能素子が形成
されていない前記半導体基板表面上の絶縁膜に開口部を
設け、該開口部の半導体基板を該開口部の面積より底面
の面積が小さくなる様なエツチング法を用いて該開口部
の半導体基板に窪みを形成した後、該開口部および該江
みに導電材料を埋め込むことにより垂直配線を形成する
工程、および前記水平配線を形成する工８を行なった後
、前記半導体基板表面上に形成された機能素子、水平配
線、および垂直配線を残した状態で前記半導体基板裏面
から半導体基板をエツチングにより除去し、該垂直配線
を裏面から飛び出させると共に該飛び出ている領域の断
面形状を三角形あるいは台形とすること全特徴とする半
導体装置の製造方法。(2) An active layer in which functional elements such as transistors, resistive elements, and capacitors, and horizontal wiring connecting these functional elements are formed on the same plane in advance, connects vertical wiring provided in each active layer. In a manufacturing method for forming each active layer of a semiconductor integrated circuit in which layers are sequentially laminated using a connection method using a diffusion welding method, the step of forming the functional element on the surface of a semiconductor substrate; An opening is provided in the insulating film on the surface of the semiconductor substrate on which no functional element is formed, and the semiconductor substrate in the opening is etched using an etching method such that the area of the bottom surface is smaller than the area of the opening. After forming a recess in the semiconductor substrate, forming a vertical wiring by burying a conductive material in the opening and the recess, and forming the horizontal wiring, a step 8 is performed on the surface of the semiconductor substrate. The semiconductor substrate is removed by etching from the back side of the semiconductor substrate while leaving the functional elements, horizontal wiring, and vertical wiring formed on the semiconductor substrate, and the vertical wiring is made to protrude from the back side, and the cross-sectional shape of the protruding area is shaped into a triangle. Alternatively, a method for manufacturing a semiconductor device characterized by having a trapezoidal shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9214084A JPS60235446A (en) | 1984-05-09 | 1984-05-09 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9214084A JPS60235446A (en) | 1984-05-09 | 1984-05-09 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60235446A true JPS60235446A (en) | 1985-11-22 |
| JPH0533536B2 JPH0533536B2 (en) | 1993-05-19 |
Family
ID=14046128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9214084A Granted JPS60235446A (en) | 1984-05-09 | 1984-05-09 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60235446A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219954A (en) * | 1986-03-20 | 1987-09-28 | Fujitsu Ltd | Manufacture of three-dimensional ic |
| JPH11261001A (en) * | 1998-03-13 | 1999-09-24 | Japan Science & Technology Corp | Manufacture of three dimensional semiconductor integrated circuit device |
| US7029937B2 (en) * | 2002-03-19 | 2006-04-18 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| JP2008270797A (en) * | 1992-04-08 | 2008-11-06 | Glenn J Leedy | Manufacturing of insulating film layer isolation ic |
| JP2009164152A (en) * | 2007-12-28 | 2009-07-23 | Nikon Corp | Laminated semiconductor device |
-
1984
- 1984-05-09 JP JP9214084A patent/JPS60235446A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219954A (en) * | 1986-03-20 | 1987-09-28 | Fujitsu Ltd | Manufacture of three-dimensional ic |
| JPH0374508B2 (en) * | 1986-03-20 | 1991-11-27 | ||
| JP2008270797A (en) * | 1992-04-08 | 2008-11-06 | Glenn J Leedy | Manufacturing of insulating film layer isolation ic |
| JP2009218606A (en) * | 1992-04-08 | 2009-09-24 | Taiwan Semiconductor Manufacturing Co Ltd | Manufacture of membrane dielectric insulation ic |
| JP4648979B2 (en) * | 1992-04-08 | 2011-03-09 | 台湾積體電路製造股▲ふん▼有限公司 | Insulating layer separation IC manufacturing |
| JP4730672B2 (en) * | 1992-04-08 | 2011-07-20 | 台湾積體電路製造股▲ふん▼有限公司 | Insulating layer separation IC manufacturing |
| JPH11261001A (en) * | 1998-03-13 | 1999-09-24 | Japan Science & Technology Corp | Manufacture of three dimensional semiconductor integrated circuit device |
| US7029937B2 (en) * | 2002-03-19 | 2006-04-18 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
| JP2009164152A (en) * | 2007-12-28 | 2009-07-23 | Nikon Corp | Laminated semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0533536B2 (en) | 1993-05-19 |
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