JP2001015556A - Semiconductor device, its manufacture, and its mounting structure - Google Patents
Semiconductor device, its manufacture, and its mounting structureInfo
- Publication number
- JP2001015556A JP2001015556A JP11188675A JP18867599A JP2001015556A JP 2001015556 A JP2001015556 A JP 2001015556A JP 11188675 A JP11188675 A JP 11188675A JP 18867599 A JP18867599 A JP 18867599A JP 2001015556 A JP2001015556 A JP 2001015556A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- groove
- columnar electrode
- lateral direction
- columnar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、柱状電極を有す
る半導体装置及びその製造方法並びにその実装構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a columnar electrode, a method of manufacturing the same, and a mounting structure thereof.
【０００２】[0002]
【従来の技術】図１４は従来の柱状電極を有する半導体
装置を基板上に実装した状態の一例の一部の断面図を示
したものである。半導体装置１は、シリコン基板（半導
体基板）２の下面に接続パッド３が形成され、その下面
の接続パッド３の中央部を除く部分に絶縁膜４が形成さ
れ、絶縁膜４に形成された開口部５を介して露出された
接続パッド３の下面に下地金属層６を介して柱状電極７
が形成された構造となっている。基板１１は、対象技術
が液晶表示装置の場合には、液晶表示パネルの一方のガ
ラス基板やフレキシブル配線基板等である。この基板１
１の上面の所定の箇所には接続端子１２が形成されてい
る。2. Description of the Related Art FIG. 14 is a partial sectional view showing an example of a state in which a conventional semiconductor device having a columnar electrode is mounted on a substrate. In the semiconductor device 1, a connection pad 3 is formed on a lower surface of a silicon substrate (semiconductor substrate) 2, an insulating film 4 is formed on a portion of the lower surface except for a central portion of the connection pad 3, and an opening formed in the insulating film 4 is formed. The columnar electrode 7 is provided on the lower surface of the connection pad 3 exposed through the portion 5 with the base metal layer 6 interposed therebetween.
Is formed. When the target technology is a liquid crystal display device, the substrate 11 is one glass substrate of a liquid crystal display panel, a flexible wiring substrate, or the like. This substrate 1
A connection terminal 12 is formed at a predetermined location on the upper surface of 1.
【０００３】そして、半導体装置１を基板１１上に実装
する場合、まず基板１１上に絶縁性接着剤１３を介して
半導体装置１をただ単に載置し、次いでボンディング工
程を経ることにより、柱状電極７で絶縁性接着剤１３を
押し退けて柱状電極７の下面を接続端子１２の上面に圧
接させ、且つ、半導体装置１の絶縁膜４の下面を基板１
１の上面に絶縁性接着剤１３を介して接着する。この場
合、柱状電極７の下面は接続端子１２の上面に圧接され
ているだけであるので、この状態を維持するため、半導
体装置１の絶縁膜４の下面を基板１１の上面に絶縁性接
着剤１３を介して接着している。When the semiconductor device 1 is mounted on the substrate 11, the semiconductor device 1 is simply placed on the substrate 11 via the insulating adhesive 13, and then a bonding process is performed. 7, the insulating adhesive 13 is pushed away, the lower surface of the columnar electrode 7 is pressed against the upper surface of the connection terminal 12, and the lower surface of the insulating film 4 of the semiconductor device 1 is
1 is bonded to the upper surface of the substrate 1 via an insulating adhesive 13. In this case, since the lower surface of the columnar electrode 7 is merely pressed against the upper surface of the connection terminal 12, in order to maintain this state, the lower surface of the insulating film 4 of the semiconductor device 1 is attached to the upper surface of the substrate 11 by an insulating adhesive. 13 are adhered.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置の実装構造では、柱状電極７の下
面を接続端子１２の上面に圧接させているだけであるの
で、柱状電極７と接続端子１２との接合強度がどちらか
といえば弱いという問題があった。この発明の課題は、
柱状電極と接続端子との接合強度を強くすることであ
る。However, in such a conventional mounting structure of a semiconductor device, the lower surface of the columnar electrode 7 is merely pressed against the upper surface of the connection terminal 12, so that the columnar electrode 7 and the connection terminal are connected. However, there is a problem that the bonding strength with No. 12 is rather weak. The object of the present invention is to
The purpose is to increase the bonding strength between the columnar electrode and the connection terminal.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明に係
る半導体装置は、柱状電極に横方向に貫通する溝を形成
したものである。請求項６記載の発明に係る半導体装置
の製造方法は、半導体基板上に形成された接続パッド上
に複数の柱状電極を形成し、これにより全長に亘って横
方向に貫通する溝を有する柱状電極を形成するようにし
たものである。請求項７記載の発明に係る半導体装置の
製造方法は、半導体基板上に形成された接続パッド上に
下部柱状電極を形成し、該下部柱状電極上に複数の上部
柱状電極を形成し、これにより根元を除く部分に横方向
に貫通する溝を有する柱状電極を形成するようにしたも
のである。請求項８記載の発明に係る半導体装置の実装
構造は、横方向に貫通する溝を有する柱状電極を備えた
半導体装置を基板上に絶縁性接着剤または異方性導電接
着剤を介して実装したものである。以上の発明によれ
ば、半導体装置の柱状電極に横方向に貫通する溝を形成
しているので、この溝内に絶縁性接着剤または異方性導
電接着剤が進入することにより、柱状電極と接続端子と
の接合強度を強くすることができる。According to a first aspect of the present invention, there is provided a semiconductor device in which a groove penetrating in a lateral direction is formed in a columnar electrode. 7. A method for manufacturing a semiconductor device according to claim 6, wherein a plurality of columnar electrodes are formed on connection pads formed on the semiconductor substrate, and thereby the columnar electrodes have grooves penetrating in the lateral direction over the entire length. Is formed. According to a method of manufacturing a semiconductor device according to the present invention, a lower columnar electrode is formed on a connection pad formed on a semiconductor substrate, and a plurality of upper columnar electrodes are formed on the lower columnar electrode. A columnar electrode having a groove penetrating in the lateral direction is formed at a portion other than the root. The mounting structure of a semiconductor device according to the invention of claim 8 is that a semiconductor device having a columnar electrode having a groove penetrating in the lateral direction is mounted on a substrate via an insulating adhesive or an anisotropic conductive adhesive. Things. According to the above invention, since the groove penetrating in the lateral direction is formed in the columnar electrode of the semiconductor device, the insulating adhesive or the anisotropic conductive adhesive enters into this groove, and the columnar electrode is The joining strength with the connection terminal can be increased.
【０００６】[0006]
【発明の実施の形態】図１はこの発明の第１実施形態に
おける半導体装置を基板上に実装した状態の要部の断面
図を示し、図２はその半導体装置の一部の斜視図を示し
たものである。これらの図において、図１４と同一名称
部分には同一の符号を付し、その説明を適宜省略する。
この第１実施形態において、図１４に示す場合と異なる
点は、半導体装置１の柱状電極７の中央部に全長に亘っ
て横方向に貫通する一字形状の溝８を形成した点であ
る。FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention mounted on a substrate, and FIG. 2 is a perspective view of a part of the semiconductor device. It is a thing. In these drawings, the same reference numerals are given to the same components as those in FIG. 14, and the description thereof will be omitted as appropriate.
In the first embodiment, the difference from the case shown in FIG. 14 is that a single-shaped groove 8 penetrating in the lateral direction over the entire length is formed at the center of the columnar electrode 7 of the semiconductor device 1.
【０００７】このように、この第１実施形態では、半導
体装置１の柱状電極７の中央部に全長に亘って横方向に
貫通する一字形状の溝８を形成しているので、この溝８
内に絶縁性接着剤１３が進入することになる。この結
果、柱状電極７の溝８の内壁面及び溝８の部分における
下地金属層６の下面と、溝８の部分における接続端子１
２の上面とが、溝８内に進入した絶縁性接着剤１３を介
して接着され、したがって柱状電極７と接続端子１２と
の接合強度を強くすることができる。As described above, in the first embodiment, the single-shaped groove 8 penetrating in the lateral direction over the entire length is formed at the center of the columnar electrode 7 of the semiconductor device 1.
The insulating adhesive 13 enters the inside. As a result, the inner wall surface of the groove 8 of the columnar electrode 7 and the lower surface of the underlying metal layer 6 at the groove 8 portion and the connection terminal 1 at the groove 8 portion
2 is bonded via the insulating adhesive 13 that has entered the groove 8, so that the bonding strength between the columnar electrode 7 and the connection terminal 12 can be increased.
【０００８】なお、半導体装置１の柱状電極７に形成さ
れる溝８の形状等は、上記第１実施形態に限定されるも
のではない。例えば、図３に示すこの発明の第２実施形
態のように、柱状電極７に全長に亘って横方向に貫通す
る十字形状の溝８を形成するようにしてもよい。また、
図４に示すこの発明の第３実施形態のように、柱状電極
７の根元を除く部分に横方向に貫通する一字形状の溝８
を形成するようにしてもよい。また、図５に示すこの発
明の第４実施形態のように、柱状電極７の根元を除く部
分に横方向に貫通する十字形状の溝８を形成するように
してもよい。また、柱状電極７の断面形状は、正方形に
限らず、円形や長方形等であってもよい。さらに、絶縁
性接着剤１３の代わりに、異方性導電接着剤を用いるよ
うにしてもよい。The shape and the like of the groove 8 formed in the columnar electrode 7 of the semiconductor device 1 are not limited to the first embodiment. For example, as in the second embodiment of the present invention shown in FIG. 3, a cross-shaped groove 8 penetrating in the lateral direction over the entire length of the columnar electrode 7 may be formed. Also,
As in the third embodiment of the present invention shown in FIG. 4, a single-shaped groove 8 penetrating in a lateral direction at a portion other than the base of the columnar electrode 7.
May be formed. Further, as in the fourth embodiment of the present invention shown in FIG. 5, a cross-shaped groove 8 penetrating in the lateral direction may be formed at a portion other than the base of the columnar electrode 7. The sectional shape of the columnar electrode 7 is not limited to a square, but may be a circle, a rectangle, or the like. Further, an anisotropic conductive adhesive may be used instead of the insulating adhesive 13.
【０００９】次に、図２に示す半導体装置１の製造方法
の一例について説明する。まず、図６に示すように、ウ
エハ状態のシリコン基板２の上面に接続パッド３が形成
され、その上面の接続パッド３の中央部を除く部分に酸
化シリコン等からなる絶縁膜４が形成され、絶縁膜４に
形成された開口部５を介して露出された接続パッド３の
上面を含む絶縁膜４の上面全体に下地金属層形成用層６
Ａが形成されたものを用意する。Next, an example of a method for manufacturing the semiconductor device 1 shown in FIG. 2 will be described. First, as shown in FIG. 6, a connection pad 3 is formed on an upper surface of a silicon substrate 2 in a wafer state, and an insulating film 4 made of silicon oxide or the like is formed on a portion of the upper surface except for a central portion of the connection pad 3, The base metal layer forming layer 6 covers the entire upper surface of the insulating film 4 including the upper surface of the connection pad 3 exposed through the opening 5 formed in the insulating film 4.
A product having A formed thereon is prepared.
【００１０】次に、図７に示すように、接続パッド３上
における絶縁膜４の上面の所定の箇所にフォトレジスト
膜２１を形成する。次に、フォトレジスト膜２１をマス
クとして下地金属層形成用層６Ａをエッチングすると、
図８に示すように、フォトレジスト膜２１下に下地金属
層６が形成される。この後、フォトレジスト膜２１を剥
離する。Next, as shown in FIG. 7, a photoresist film 21 is formed on a predetermined portion of the upper surface of the insulating film 4 on the connection pad 3. Next, the underlying metal layer forming layer 6A is etched using the photoresist film 21 as a mask.
As shown in FIG. 8, the underlying metal layer 6 is formed under the photoresist film 21. Thereafter, the photoresist film 21 is peeled off.
【００１１】次に、図９に示すように、絶縁膜４の上面
及び下地金属層６の上面にメッキレジスト膜２２を形成
すると共に、このメッキレジスト膜２２の下地金属層６
の上面中央部の両側に対応する部分に開口部２３を形成
する。次に、メッキレジスト膜２２の開口部２３内にお
ける下地金属層６の上面に無電解メッキにより柱状電極
７を形成する。この後、メッキレジスト膜２２を剥離す
る。次に、ダイシング工程を経ると、図２に示す半導体
装置１が得られる。なお、図３に示す半導体装置１も上
記と同様の製造方法により製造することができる。Next, as shown in FIG. 9, a plating resist film 22 is formed on the upper surface of the insulating film 4 and the upper surface of the base metal layer 6, and the base metal layer 6 of the plating resist film 22 is formed.
Openings 23 are formed in portions corresponding to both sides of the central portion of the upper surface of. Next, the columnar electrode 7 is formed on the upper surface of the base metal layer 6 in the opening 23 of the plating resist film 22 by electroless plating. Thereafter, the plating resist film 22 is peeled off. Next, after a dicing step, the semiconductor device 1 shown in FIG. 2 is obtained. The semiconductor device 1 shown in FIG. 3 can be manufactured by the same manufacturing method as described above.
【００１２】次に、図４に示す半導体装置１の製造方法
の一例について説明する。この場合も、まず、図６に示
すものを用意する。次に、図１０に示すように、下地金
属層形成用層６Ａの上面に第１メッキレジスト膜２４を
形成すると共に、この第１メッキレジスト膜２４の接続
パッド３に対応する部分に開口部２５を形成する。次
に、下地金属層形成用層６Ａをメッキ電流路として電解
メッキを行うことにより、第１メッキレジスト膜２４の
開口部２５内における下地金属層形成用層６Ａの上面に
下部柱状電極７ａを形成する。Next, an example of a method for manufacturing the semiconductor device 1 shown in FIG. 4 will be described. Also in this case, first, the one shown in FIG. 6 is prepared. Next, as shown in FIG. 10, a first plating resist film 24 is formed on the upper surface of the base metal layer forming layer 6A, and an opening 25 is formed in a portion of the first plating resist film 24 corresponding to the connection pad 3. To form Next, the lower columnar electrode 7a is formed on the upper surface of the base metal layer forming layer 6A in the opening 25 of the first plating resist film 24 by performing electrolytic plating using the base metal layer forming layer 6A as a plating current path. I do.
【００１３】次に、図１１に示すように、第１メッキレ
ジスト膜２４及び下地金属層形成用層６Ａの上面に第２
メッキレジスト膜２６を形成すると共に、この第２メッ
キレジスト膜２６の下部柱状電極７ａの上面中央部の両
側に対応する部分に開口部２７を形成する。次に、電解
メッキを行うことにより、第２メッキレジスト膜２６の
開口部２７内における下部柱状電極７ａの上面に上部柱
状電極７ｂを形成する。この後、第２及び第１メッキレ
ジスト膜２６、２４を剥離すると、図１２に示すように
なる。Next, as shown in FIG. 11, a second plating resist film 24 and a second metal layer
At the same time as forming the plating resist film 26, openings 27 are formed in portions of the second plating resist film 26 corresponding to both sides of the center of the upper surface of the lower columnar electrode 7a. Next, the upper columnar electrode 7b is formed on the upper surface of the lower columnar electrode 7a in the opening 27 of the second plating resist film 26 by performing electrolytic plating. Thereafter, when the second and first plating resist films 26 and 24 are peeled off, the result is as shown in FIG.
【００１４】次に、上部柱状電極７ｂ及び下部柱状電極
７ａをマスクとして下地金属層形成用層６Ａをエッチン
グすると、図１３に示すように、下部柱状電極７ａ下に
下地金属層６が形成される。次に、ダイシング工程を経
ると、図４に示す半導体装置１が得られる。なお、図５
に示す半導体装置１も上記と同様の製造方法により製造
することができる。Next, when the base metal layer forming layer 6A is etched using the upper columnar electrode 7b and the lower columnar electrode 7a as a mask, the base metal layer 6 is formed below the lower columnar electrode 7a as shown in FIG. . Next, after a dicing step, the semiconductor device 1 shown in FIG. 4 is obtained. FIG.
Can be manufactured by the same manufacturing method as described above.
【００１５】[0015]
【発明の効果】以上説明したように、この発明によれ
ば、半導体装置の柱状電極に横方向に貫通する溝を形成
しているので、この溝内に絶縁性接着剤または異方性導
電接着剤が進入することにより、柱状電極と接続端子と
の接合強度を強くすることができる。As described above, according to the present invention, since a groove penetrating in the lateral direction is formed in the columnar electrode of the semiconductor device, an insulating adhesive or an anisotropic conductive adhesive is formed in the groove. The penetration of the agent can increase the bonding strength between the columnar electrode and the connection terminal.
【図１】この発明の第１実施形態における半導体装置を
基板上に実装した状態の要部の断面図。FIG. 1 is a sectional view of a main part of a state where a semiconductor device according to a first embodiment of the present invention is mounted on a substrate.
【図２】図１に示す半導体装置の一部の斜視図。FIG. 2 is a perspective view of a part of the semiconductor device shown in FIG.
【図３】この発明の第２実施形態における半導体装置の
一部の斜視図。FIG. 3 is a perspective view of a part of a semiconductor device according to a second embodiment of the present invention.
【図４】この発明の第３実施形態における半導体装置の
一部の斜視図。FIG. 4 is a perspective view of a part of a semiconductor device according to a third embodiment of the present invention.
【図５】この発明の第４実施形態における半導体装置の
一部の斜視図。FIG. 5 is a perspective view of a part of a semiconductor device according to a fourth embodiment of the present invention.
【図６】図２に示す半導体装置の製造に際し、当初用意
したものの断面図。FIG. 6 is a sectional view of a device initially prepared for manufacturing the semiconductor device shown in FIG. 2;
【図７】図６に続く製造工程の断面図。FIG. 7 is a sectional view of the manufacturing process following FIG. 6;
【図８】図７に続く製造工程の断面図。FIG. 8 is a sectional view of the manufacturing process following FIG. 7;
【図９】図８に続く製造工程の断面図。FIG. 9 is a sectional view of the manufacturing process following FIG. 8;
【図１０】図４に示す半導体装置の製造に際し、所定の
製造工程の断面図。FIG. 10 is a sectional view of a predetermined manufacturing step in manufacturing the semiconductor device shown in FIG. 4;
【図１１】図１０に続く製造工程の断面図。FIG. 11 is a sectional view of the manufacturing process continued from FIG. 10;
【図１２】図１１に続く製造工程の断面図。FIG. 12 is a sectional view of the manufacturing process following FIG. 11;
【図１３】図１２に続く製造工程の断面図。FIG. 13 is a sectional view of the manufacturing process following FIG. 12;
【図１４】従来の半導体装置を基板上に実装した状態の
一例の一部の断面図。FIG. 14 is a partial cross-sectional view illustrating an example of a state where a conventional semiconductor device is mounted on a substrate.
１ 半導体装置 ２ シリコン基板 ３ 接続パッド ４ 絶縁膜 ６ 下地金属層 ７ 柱状電極 ８ 溝 １１ 基板 １２ 接続端子 １３ 絶縁性接着剤 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Silicon substrate 3 Connection pad 4 Insulating film 6 Base metal layer 7 Columnar electrode 8 Groove 11 Substrate 12 Connection terminal 13 Insulating adhesive
Claims (10)
前記柱状電極に横方向に貫通する溝が形成されているこ
とを特徴とする半導体装置。In a semiconductor device having a columnar electrode,
A semiconductor device, wherein a groove penetrating in the lateral direction is formed in the columnar electrode.
前記柱状電極の全長に亘って形成されていることを特徴
とする半導体装置。2. The semiconductor device according to claim 1, wherein said groove is formed over the entire length of said columnar electrode.
前記柱状電極の根元を除く部分に形成されていることを
特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein said groove is formed in a portion other than a root of said columnar electrode.
おいて、前記溝は一字形状であることを特徴とする半導
体装置。4. The semiconductor device according to claim 1, wherein said groove has a straight-line shape.
おいて、前記溝は十字形状であることを特徴とする半導
体装置。5. The semiconductor device according to claim 1, wherein the groove has a cross shape.
に複数の柱状電極を形成し、これにより全長に亘って横
方向に貫通する溝を有する柱状電極を形成することを特
徴とする半導体装置の製造方法。6. A semiconductor device wherein a plurality of columnar electrodes are formed on connection pads formed on a semiconductor substrate, thereby forming a columnar electrode having a groove penetrating in the lateral direction over the entire length. Manufacturing method.
に下部柱状電極を形成し、該下部柱状電極上に複数の上
部柱状電極を形成し、これにより根元を除く部分に横方
向に貫通する溝を有する柱状電極を形成することを特徴
とする半導体装置の製造方法。7. A lower columnar electrode is formed on a connection pad formed on a semiconductor substrate, and a plurality of upper columnar electrodes are formed on the lower columnar electrode, thereby penetrating a portion except a root in a lateral direction. A method for manufacturing a semiconductor device, comprising: forming a columnar electrode having a groove.
備えた半導体装置を基板上に絶縁性接着剤または異方性
導電接着剤を介して実装したことを特徴とする半導体装
置の実装構造。8. A mounting structure for a semiconductor device, wherein a semiconductor device provided with a columnar electrode having a groove penetrating in the lateral direction is mounted on a substrate via an insulating adhesive or an anisotropic conductive adhesive. .
前記柱状電極の全長に亘って形成されていることを特徴
とする半導体装置の実装構造。9. The mounting structure of a semiconductor device according to claim 8, wherein the groove is formed over the entire length of the columnar electrode.
は前記柱状電極の根元を除く部分に形成されていること
を特徴とする半導体装置の実装構造。10. The semiconductor device mounting structure according to claim 8, wherein said groove is formed in a portion other than a root of said columnar electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11188675A JP2001015556A (en) | 1999-07-02 | 1999-07-02 | Semiconductor device, its manufacture, and its mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11188675A JP2001015556A (en) | 1999-07-02 | 1999-07-02 | Semiconductor device, its manufacture, and its mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001015556A true JP2001015556A (en) | 2001-01-19 |
Family
ID=16227890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11188675A Pending JP2001015556A (en) | 1999-07-02 | 1999-07-02 | Semiconductor device, its manufacture, and its mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001015556A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005526374A (en) * | 2001-08-03 | 2005-09-02 | シュラムバーガー システムズ | Method for enabling electronic and mechanical connection between an electrical device and a surface equipped with a contact pad |
| JP2007294916A (en) * | 2006-03-31 | 2007-11-08 | Brother Ind Ltd | Connecting structure, method of forming bump and the like |
| JP2008153296A (en) * | 2006-12-14 | 2008-07-03 | Fujitsu Ltd | Connecting structure and manufacturing method therefor, and semiconductor device and manufacturing method therefor |
| JP2017034031A (en) * | 2015-07-30 | 2017-02-09 | シチズン電子株式会社 | Semiconductor element and light-emitting device |
| CN109980059A (en) * | 2019-04-17 | 2019-07-05 | 厦门乾照半导体科技有限公司 | A kind of electrode has the LED chip structure of opening |
-
1999
- 1999-07-02 JP JP11188675A patent/JP2001015556A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005526374A (en) * | 2001-08-03 | 2005-09-02 | シュラムバーガー システムズ | Method for enabling electronic and mechanical connection between an electrical device and a surface equipped with a contact pad |
| JP2007294916A (en) * | 2006-03-31 | 2007-11-08 | Brother Ind Ltd | Connecting structure, method of forming bump and the like |
| JP2008153296A (en) * | 2006-12-14 | 2008-07-03 | Fujitsu Ltd | Connecting structure and manufacturing method therefor, and semiconductor device and manufacturing method therefor |
| JP2017034031A (en) * | 2015-07-30 | 2017-02-09 | シチズン電子株式会社 | Semiconductor element and light-emitting device |
| CN109980059A (en) * | 2019-04-17 | 2019-07-05 | 厦门乾照半导体科技有限公司 | A kind of electrode has the LED chip structure of opening |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5649739B2 (en) | No flow underfill | |
| TW201250957A (en) | Reinforced fan-out wafer-level package | |
| JP3003624B2 (en) | Semiconductor device | |
| USRE48421E1 (en) | Flip chip and method of making flip chip | |
| JP2001044197A (en) | Semiconductor device and manufacture thereof | |
| JP7201296B2 (en) | Semiconductor device and its manufacturing method | |
| US6339247B1 (en) | Structure for mounting a semiconductor device on a liquid crystal display, and semiconductor device | |
| JPS59139636A (en) | Bonding method | |
| JP2001015556A (en) | Semiconductor device, its manufacture, and its mounting structure | |
| JP3529915B2 (en) | Lead frame member and method of manufacturing the same | |
| JP2937111B2 (en) | Semiconductor device and manufacturing method thereof | |
| US10651374B2 (en) | Semiconductor device, and method for manufacturing the same | |
| JP2004087657A (en) | Tab tape, method for manufacturing the same, and semiconductor device using the same | |
| JP2748530B2 (en) | Method for manufacturing semiconductor device | |
| JP2874184B2 (en) | Method for manufacturing semiconductor device | |
| JPH09223759A (en) | Semiconductor device and manufacture thereof | |
| JP4168494B2 (en) | Manufacturing method of semiconductor device | |
| JP2001093869A (en) | Method for manufacturing semiconductor device | |
| JP4071121B2 (en) | Semiconductor device | |
| JP2003243813A (en) | Terminal structure | |
| JPS59111338A (en) | Bonding method of semiconductor element with circuit board | |
| JP2002252248A (en) | Semiconductor device and its jointing structure | |
| JPH10340907A (en) | Formation of protruding electrode | |
| JPH02172245A (en) | Semiconductor device | |
| JP2000332155A (en) | Semiconductor device and manufacture thereof |