JPS60231351A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60231351A
JPS60231351A JP59086993A JP8699384A JPS60231351A JP S60231351 A JPS60231351 A JP S60231351A JP 59086993 A JP59086993 A JP 59086993A JP 8699384 A JP8699384 A JP 8699384A JP S60231351 A JPS60231351 A JP S60231351A
Authority
JP
Japan
Prior art keywords
film
sio2 film
temperature
gas atmosphere
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59086993A
Other languages
Japanese (ja)
Inventor
Kazunori Imaoka
今岡 和典
Takao Miura
隆雄 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59086993A priority Critical patent/JPS60231351A/en
Publication of JPS60231351A publication Critical patent/JPS60231351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve the yield rate and reliability of an IC, by performing the heat treatment of a silicon substrate in a neutral gas atmosphere, in which halogen gas is mixed, oxidizing the surface of the substrate, and forming a high- quality thin SiO2 film having desired dielectric strength. CONSTITUTION:The surface of a silicon substrate 11 is heat-treated in oxygen at 850 deg.C (surface protection process; A), and an SiO2 film 13 is formed. Temperature is increased in an argon gas atmosphere, in which 0.5% hydrochloric acid gas is mixed and kept at 1,100 deg.C (gettering process; B). The hydrochloric acid gas is stopped, and the temperature is decreased only in argon gas atmosphere to 800 deg.C. Oxidizing treatment for increasing the temperature up to 1,050 deg.C is performed in a dry oxygen gas atmosphere including hydrochloric acid (oxidizing process; C). The temperature is decreased immediately. An SiO2 film 12 is formed at the interface between silicon and the SiO2 film 13. The SiO2 film 13 is etched away in the oxidizing process, and only the SiO2 film 12 remains.

Description

【発明の詳細な説明】 ia) 発明の技術分野 本発明は半導体装置の製造方法のうち、特にシリコン基
板面に二酸化シリコン(Si02)膜を生成する酸化処
理に関する。
DETAILED DESCRIPTION OF THE INVENTION ia) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to an oxidation treatment for forming a silicon dioxide (Si02) film on a silicon substrate surface.

申)従来技術と問題点 周知のように、現用されているIC(半導体集積回路)
などの半導体装置は、シリコン基板を用いたシリコン半
導体が主体となっているが、このようなシリコン半導体
装置の製造方法において、シリコン基板の表面を熱酸化
して5i02膜を生成し、その5i02膜を絶縁膜とし
て利用する酸化処理工程は、製造法の中枢をなしており
、この巧妙な絶縁膜形成法がシリコン半導体を発展させ
た最大の原因でもある。
) Conventional technology and problems As is well known, currently used ICs (semiconductor integrated circuits)
Semiconductor devices such as these are mainly made of silicon semiconductors using silicon substrates, but in the manufacturing method of such silicon semiconductor devices, the surface of the silicon substrate is thermally oxidized to generate a 5i02 film, and the 5i02 film is The oxidation process that uses silicon as an insulating film is the core of the manufacturing method, and this ingenious method of forming an insulating film is the biggest reason for the development of silicon semiconductors.

従って、5i02膜の膜質によってICの性能は大き(
左右され、高品質な5i02膜を形成するために、従来
より多くの努力が払われてきた。しかし、最近のように
半導体装置が高集積化されて微細化されてくると、Si
O2欣の膜厚も益々薄くなって、絶縁耐圧が次第に悪化
する恐れがでてきた。
Therefore, the performance of the IC is greatly affected by the quality of the 5i02 film (
In the past, much effort has been made to form highly sensitive and high quality 5i02 films. However, as semiconductor devices have become highly integrated and miniaturized in recent years, Si
As the thickness of the O2 film becomes thinner and thinner, there is a fear that the dielectric strength will gradually deteriorate.

この絶縁耐圧の劣化は、主として5i02膜の中に不純
物が混入するためである。
This deterioration of the dielectric strength voltage is mainly due to the incorporation of impurities into the 5i02 film.

第1図はシリコン半導体メモリのうち、DRAM(ダイ
ナミック・ランダムアクセス・メモリ)のセル断面図を
示しており、一般にDRAMは1トランジスタ1キヤパ
シタからなるセルで構成され、この形式のメモリが64
 K 、 125 K 、 256 Kなどと極めて高
集積化されている。図において、lはフィールド酸化膜
12はゲート酸化膜、3はキャパシタで、これらは何れ
も生成した5i02膜からなる絶縁膜あるいは誘電体膜
である。
Figure 1 shows a cross-sectional view of a DRAM (dynamic random access memory) cell among silicon semiconductor memories. Generally, a DRAM consists of a cell consisting of one transistor and one capacitor, and this type of memory has 64 cells.
They are extremely highly integrated, such as 125K, 125K, and 256K. In the figure, 1 is a field oxide film 12, a gate oxide film, and 3 is a capacitor, both of which are insulating films or dielectric films made of the produced 5i02 film.

このDRAMメモリにおいて、特に膜質の重要なSiO
2膜はキャパシタ3で、高集積化すればキャパシタが小
型になって、容量が小さくなるために、微細にして且つ
容量を大きくする目的で、キャパシタ用の5i02膜は
膜厚100〜250人程度と極めて薄く形成されるよう
になってきた。これに対し、ゲート酸化膜2は400〜
500人と厚く、フィールド酸化膜1は更に厚い膜厚(
1μm程度)が形成されている。
In this DRAM memory, SiO film quality is particularly important.
The 2 film is the capacitor 3. If the integration is high, the capacitor becomes smaller and the capacitance becomes smaller. Therefore, in order to make it finer and increase the capacitance, the 5i02 film for the capacitor is made to have a thickness of about 100 to 250. It has come to be formed extremely thin. On the other hand, the gate oxide film 2 has a thickness of 400~
500 thick, and the field oxide film 1 is even thicker (
(approximately 1 μm) is formed.

ところで、上記のように、従来からも高品質な5i02
膜の生成には留意しているが、このキャパシタのような
5i02膜の生成は従来より特に慎重に行なわれ、次の
ように処理されている。即ち、シリコン基板面を弗酸で
エツチングして、純水で洗浄する工程(前処理工程)を
経た後、シリコン基板面を800〜900℃の乾燥(ド
ライ)酸素中で僅かに酸化して50〜100人の5i0
2膜を生成する処理(表面保護工程)を行なう。次に、
ハロゲンガスを少し含んだ酸素ガス雰囲気中で約100
0℃に加熱する熱処理(酸化工程)を行なって、所要膜
厚のキャパシタを形成する。
By the way, as mentioned above, the high quality 5i02
Although careful attention is paid to the production of the film, the production of a 5i02 film such as this capacitor is performed with particular care than in the past, and is processed as follows. That is, after the silicon substrate surface is etched with hydrofluoric acid and washed with pure water (pretreatment step), the silicon substrate surface is slightly oxidized in dry oxygen at 800 to 900°C. ~100 people 5i0
A process (surface protection process) to generate two films is performed. next,
Approximately 100% in an oxygen gas atmosphere containing a small amount of halogen gas
A heat treatment (oxidation step) of heating to 0° C. is performed to form a capacitor with a desired thickness.

ここに、ハロゲンガスには塩酸やトリクロールエタンな
どの塩素系ガス等が使用され、そのガス混合率は10%
未満(対酸素流量比)と少しであるが、この塩素系ガス
のようなハロゲンガスを混合させると、シリコン表面に
付着した汚染物やシリコン内部に含まれる各種の不純物
をこのガスがゲッタリングして昇華除去し、純粋な膜質
のSiO2膜を形成することができる。
Here, chlorine-based gas such as hydrochloric acid or trichloroethane is used as the halogen gas, and the gas mixing ratio is 10%.
Although the flow rate ratio to oxygen is small, when halogen gas such as chlorine-based gas is mixed, this gas getster the contaminants attached to the silicon surface and various impurities contained inside the silicon. By sublimation removal, a pure SiO2 film can be formed.

しかしなから、更に高集積化が進み、上記のように5i
02膜の膜厚が100〜250人程度と著しく薄くなっ
てきた現在、従来の生成法では十分に耐圧を維持する事
ができなくなってきた。これは、酸化工程の処理時間が
短くなって、ハロゲンガスによるゲッタリング効果がな
くなってきたものと考えられる。
However, as the integration has progressed further, as mentioned above, 5i
Nowadays, the thickness of the 02 film has become significantly thinner to about 100 to 250, and it is no longer possible to maintain sufficient pressure resistance using conventional production methods. This is considered to be because the processing time of the oxidation step has become shorter and the gettering effect of the halogen gas has disappeared.

fcl 発明の目的 本発明は、このような薄い5i02膜の膜質を改善して
絶縁耐圧を向上するための、SiO2膜の生成方法を提
案するものである。
fcl Object of the Invention The present invention proposes a method for producing a SiO2 film in order to improve the film quality of such a thin 5i02 film and increase its dielectric strength.

+d) 発明の構成 その目的は、シリコン基板をハロゲンガスを混入した中
性ガス雰囲気中で熱処理し、次いで該シリコン基板面を
酸化して二酸化シリコン膜を生成する工程が含まれる半
導体装置の製造方法によって達成される。
+d) Structure of the Invention The object is to provide a method for manufacturing a semiconductor device, which includes a step of heat-treating a silicon substrate in a neutral gas atmosphere mixed with halogen gas, and then oxidizing the surface of the silicon substrate to generate a silicon dioxide film. achieved by.

tel 発明の実施例 以下2図面を参照して実施例によって詳細に説明する。tel Embodiments of the invention Examples will be described in detail below with reference to two drawings.

第2図は本発明にかかる一実施例の酸化生成工程の温度
と時間との関係図表を示している。まず、シリコン基板
面を弗酸でエツチングして、純水で洗浄する前処理(前
処理工程)を行なった後に、シリコン基板面を850℃
の酸素中で10分間熱処理(表面保護工程;図表のAラ
イン)して、膜厚数10人の5i02膜を生成する。次
いで、0.5%塩酸ガス(この%は対酸素流量比である
)を混入したアルゴンガス雰囲気中で昇温し、1100
℃で20分保持(ゲソタリング工程;図表のBライン)
する。
FIG. 2 shows a diagram of the relationship between temperature and time in the oxidation generation step in one embodiment of the present invention. First, the silicon substrate surface is etched with hydrofluoric acid and washed with pure water (pretreatment step), and then the silicon substrate surface is heated to 850°C.
A 5i02 film with a thickness of several tens of layers is produced by heat treatment for 10 minutes in oxygen (surface protection step; line A in the diagram). Next, the temperature was raised in an argon gas atmosphere mixed with 0.5% hydrochloric acid gas (this % is the flow rate ratio to oxygen), and the temperature was increased to 1100
Hold at ℃ for 20 minutes (gesotaring process; line B in the diagram)
do.

次いで、塩酸ガスを止め、アルゴンガスのみの雰囲気中
で降温し、800℃位まで降下させる。次いで、塩酸を
含んだドライ酸素ガス雰囲気中で800℃から1050
℃まで温度を上げる酸化処理(酸化工程;図表のCライ
ン)を行い、1050℃で直ちに降温する。
Next, the hydrochloric acid gas is stopped, and the temperature is lowered to about 800° C. in an atmosphere of argon gas only. Next, the temperature was heated from 800°C to 1050°C in a dry oxygen gas atmosphere containing hydrochloric acid.
An oxidation treatment (oxidation step; line C in the diagram) is performed to raise the temperature to 1050°C, and the temperature is immediately lowered to 1050°C.

そうすると、第3図に示すようにシリコン基板11の表
面に膜厚150人の純粋な5i02膜12が形成される
。即ち、この5i02膜12はシリコンと前記表面保護
工程で形成された5i02膜13との界面に生成され、
表面保護工程で形成されたSiO2膜13ば酸化工程で
エツチングされて除去され、純粋な5i02膜12のみ
が残存する。
Then, as shown in FIG. 3, a pure 5i02 film 12 with a thickness of 150 nm is formed on the surface of the silicon substrate 11. That is, this 5i02 film 12 is generated at the interface between silicon and the 5i02 film 13 formed in the surface protection step,
The SiO2 film 13 formed in the surface protection process is etched and removed in the oxidation process, leaving only the pure 5i02 film 12.

このようにして形成したキャパシタの絶縁耐圧のデータ
を従来法のキャパシタのデータと比較して第4図の図表
を示している。第4図(alは従来法によって生成した
5i02膜の絶縁耐圧の分布、第4図中)は本発明にか
かる生成法によった5i02膜の絶縁耐圧の分布で、本
発明によれば90%のキャパシタに良好な絶縁耐圧が得
られたが、従来法では所望耐圧のキャパシタは50%程
度しか得られていなかった。
The diagram of FIG. 4 compares the dielectric strength data of the capacitor thus formed with the data of the conventional capacitor. Figure 4 (al is the distribution of the dielectric strength voltage of the 5i02 film produced by the conventional method, in Figure 4) is the distribution of the dielectric strength voltage of the 5i02 film produced by the production method according to the present invention, and according to the present invention, 90% A good dielectric breakdown voltage was obtained for the capacitor, but only about 50% of the capacitors had the desired breakdown voltage using the conventional method.

上記は一実施例であるが、ゲソタリング工程における熱
処理温度は900〜1250℃が適当で、またハロゲン
ガスの対アルゴン流ft 比ハ0.1〜1.0%が適当
である。且つ、酸化工程における酸化処理は、酸素の代
わりに水蒸気と酸素との混合ガス、あるいはハロゲンガ
スの雰囲気中で行なっても良い。
Although the above is an example, the heat treatment temperature in the gesotaring step is suitably 900 to 1250°C, and the halogen gas to argon flow ft ratio is suitably 0.1 to 1.0%. In addition, the oxidation treatment in the oxidation step may be performed in an atmosphere of a mixed gas of water vapor and oxygen or a halogen gas instead of oxygen.

且つ、本実施例で説明したキャパシタ1 (第1図参照
)はフィールド酸化膜3を形成する工程(LOGO3工
程)の次の工程で形成されるものであるが、本発明はこ
のようなキャパシタのみならず、薄い5i02膜生成の
全般に適用できることは云うまでもない。
Furthermore, although the capacitor 1 (see FIG. 1) described in this embodiment is formed in the next step after the step of forming the field oxide film 3 (LOGO3 step), the present invention is applicable only to such a capacitor. Needless to say, the present invention can be applied to the production of thin 5i02 films in general.

(fl 発明の効果 以上の説明から明らかなように、本発明によれば所望の
絶縁耐圧を有する高品質な薄い5i02膜が生成され、
ICの歩留、信頼性の向上に顕著な効果があるものであ
る。
(fl Effects of the Invention As is clear from the above explanation, according to the present invention, a high quality thin 5i02 film having a desired dielectric strength voltage is produced,
This has a remarkable effect on improving the yield and reliability of ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はDRAMメモリのセル断面図、第2図は本発明
にかかる処理工程図表、第3図はシリコン基板の断面図
、第4図(a)、 (blは従来法と本発明にかかる生
成法の絶縁耐圧分布図表である。 図中、1は薄い5i02膜からなるキャパシタ。 11はシリコン基板、 12は薄い5i02膜を示して
いる。 第1圀 第2図 第3図 第4図 (縛m1氏 淀縁弧 手続補正書輸発) 1.事件の表示 3、補正をする者 事件との関係 特許出願人 住所 神奈川県用崎市中原区」二小ぽ1中1015番地
(522)名称富士通株式会社 4、代 理 人 住所 神奈川県用崎市中原区−に小r
Jl中1015番地8補正の内容 別紙の通り 1)明細書第3頁第6行乃至第9行を以下の様に補正す
る。 「ヤパシタ用の5102膜1は膜厚100〜25OA程
度と極めて薄く形成されるようになってきた。 これに対し、ゲート酸化膜2は400〜500Aと厚く
、フィールド酸化膜3は更に厚い膜厚(1μm程度)」 2)明細書第6頁第16行乃至第18行を以下の様に補
正する。 「て第4図の図表を示している。第4図(b)は従来法
によって生成した5102膜の絶縁耐圧の分布、第4図
(a)は本発明にかかる生成法によった5to2膜」 3)明細書第8頁第4行及び第5行を以下の様に補正す
る。 「ン基板の断面図、第4図(a)は本発明にかかる5i
02膜の絶縁耐圧分布図、第4図(b)は従来法によっ
て得られた8102膜の絶縁耐圧分布図である。 代理人 弁理士 松 岡 宏四部 2−
Fig. 1 is a cross-sectional view of a DRAM memory cell, Fig. 2 is a processing process chart according to the present invention, Fig. 3 is a cross-sectional view of a silicon substrate, and Fig. 4 (a) and (bl are for the conventional method and the present invention) This is a breakdown voltage distribution chart of the production method. In the figure, 1 is a capacitor made of a thin 5i02 film. 11 is a silicon substrate, and 12 is a thin 5i02 film. Mr. Baku m1 (Import of Yodoen-Aku procedural amendment) 1. Indication of the case 3, person making the amendment Relationship with the case Patent applicant address 1015 (522) Nikopo 1 Nakahara-ku, Yozaki City, Kanagawa Prefecture Name Fujitsu Limited 4, Agent Address Nakahara Ward, Yozaki City, Kanagawa Prefecture
Contents of the amendment at No. 8, 1015 Jl Naka As shown in the attached sheet 1) Lines 6 to 9 of page 3 of the specification are amended as follows. ``The 5102 film 1 for Yapacita has become extremely thin, with a thickness of about 100 to 25 OA.On the other hand, the gate oxide film 2 has a thick thickness of 400 to 500 Å, and the field oxide film 3 has an even thicker thickness. (approximately 1 μm)” 2) Lines 16 to 18 of page 6 of the specification are corrected as follows. Figure 4(b) shows the distribution of dielectric strength of the 5102 film produced by the conventional method, and Figure 4(a) shows the distribution of the dielectric strength of the 5to2 film produced by the production method according to the present invention. 3) Lines 4 and 5 of page 8 of the specification are amended as follows. 4(a) is a cross-sectional view of the 5i according to the present invention.
FIG. 4(b) is a dielectric strength distribution diagram of the 8102 film obtained by the conventional method. Agent Patent Attorney Hiroshi Matsuoka Department 2-

Claims (1)

【特許請求の範囲】[Claims] シリコン基板をハロゲンガスを混入した中性ガス雰囲気
中で熱処理し、次いで該シリコン基板面を酸化して二酸
化シリコン膜を生成する工程が含まれてなることを特徴
とする半導体装置の製造方法。
1. A method for manufacturing a semiconductor device, comprising the steps of heat-treating a silicon substrate in a neutral gas atmosphere mixed with halogen gas, and then oxidizing the surface of the silicon substrate to produce a silicon dioxide film.
JP59086993A 1984-04-27 1984-04-27 Manufacture of semiconductor device Pending JPS60231351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59086993A JPS60231351A (en) 1984-04-27 1984-04-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59086993A JPS60231351A (en) 1984-04-27 1984-04-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60231351A true JPS60231351A (en) 1985-11-16

Family

ID=13902392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59086993A Pending JPS60231351A (en) 1984-04-27 1984-04-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60231351A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635534A (en) * 1986-06-25 1988-01-11 Matsushita Electronics Corp Manufacture of semiconductor device
JPH01297827A (en) * 1988-05-25 1989-11-30 Nec Corp Oxidization of semiconductor substrate and device therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635534A (en) * 1986-06-25 1988-01-11 Matsushita Electronics Corp Manufacture of semiconductor device
JPH01297827A (en) * 1988-05-25 1989-11-30 Nec Corp Oxidization of semiconductor substrate and device therefor

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