JPS60189228A - Chip taping apparatus - Google Patents

Chip taping apparatus

Info

Publication number
JPS60189228A
JPS60189228A JP4285384A JP4285384A JPS60189228A JP S60189228 A JPS60189228 A JP S60189228A JP 4285384 A JP4285384 A JP 4285384A JP 4285384 A JP4285384 A JP 4285384A JP S60189228 A JPS60189228 A JP S60189228A
Authority
JP
Japan
Prior art keywords
chip
tape
reel
good
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4285384A
Other languages
Japanese (ja)
Inventor
Yasuo Shimoda
下田　靖雄
Motohiko Kato
元彦 加藤
Takeshi Kimoto
木本　武
Eiji Sato
英治 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinkawa Ltd
Original Assignee
Shinkawa Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Ltd filed Critical Shinkawa Ltd
Priority to JP4285384A priority Critical patent/JPS60189228A/en
Publication of JPS60189228A publication Critical patent/JPS60189228A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve operativity and controllability as well as operating percentage of a chip bonder, by housing good chips in concaves of a tape so that the tape can be kept with being wound on a filling reel. CONSTITUTION:A chip 20 is positioned by wafer ring driving means 10 and it is differentiated by the camera 61 of a chip differentiating apparatus 60 whether the chip 20 is good or bad. If the chip 20 is good, it is vacuum-attracted by a transfer collet 51 after the up-and-down rotating axis 54 is lowered. Next, the axis 54 is risen, rotated, and lowered to put the chip 20 in a hole 33a of a tape 31. Each time any one good chip 20 is housed in a hole 33a, the filling reel 37 is drived intermittently by a pitch distance between two holes 33a and the tape 31 is taken up on the filling reel 37 while a upper face cover 40 is overlaid on the tape 31. Since the filling reel 37 on which the tape 31 housing good chips 20 was wound can be utilized, an operating percentage of a chip bonder would be more improved.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はチップボンダにおけるチップテーピング装置に
関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a chip taping device for a chip bonder.

（発明の背景） チップボンダにおいては、稼動率向上のため、例えば特
開昭５８−２２０４４１号公報に示すように、ウェハか
ら良品チップを識別して一旦トレーに詰め換えることが
行われている。しかしながら、かかる方法は、１個のト
レーに詰めるチップの数が少なく、チップボンダにトレ
ーラ頻繁にセットしなければならなく、作業能率が悪い
。またトレー駆動装置の振動でチップがトレーより飛び
出すことがある。またトレーがかさばったり、トレーを
長時間外部環境にさらしておくとごみ等が付着したりし
、保管上に難点があった。(Background of the Invention) In a chip bonder, in order to improve the operating rate, as shown in, for example, Japanese Unexamined Patent Publication No. 58-220441, good chips are identified from wafers and temporarily repacked into a tray. However, in this method, the number of chips packed into one tray is small, and the trailer must be frequently set in the chip bonder, resulting in poor work efficiency. Also, the chips may fly out of the tray due to the vibration of the tray drive device. In addition, the trays are bulky, and if the trays are exposed to the outside environment for a long time, dirt and the like may adhere to them, making storage difficult.

（発明の目的） 本発明の目的は、作業性及び管理性に優れたチップテー
ピング装置を提供することにある。(Object of the Invention) An object of the present invention is to provide a tip taping device with excellent workability and manageability.

（発明の実施例） 以下、本発明を図示の実施例により説明する。(Example of the invention) Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第１図は本発明になるチップテーピング装置の一実施例
を示す概略構成斜視図、第２図は第１図のテープリール
手段の正面図、第３図は第２図の要部拡大断面図である
。本装置は大別して、縦横複数に分割されたチップをピ
ツクア゛ツブ位ｔ＋こｍ動するためのウェハリング駆動
手段１０と、良品チップを収納するテープリール手段３
０と、ウェハリング駆動手段１０よりテープリール手段
３０のテープに良品チップを詰めるチップピックアップ
手段５０と、ウェハリング駆動手段１０にセットされた
チップを識別するチップ識別装置６０とにより構成され
ている。FIG. 1 is a schematic perspective view showing an embodiment of the chip taping apparatus according to the present invention, FIG. 2 is a front view of the tape reel means shown in FIG. 1, and FIG. 3 is an enlarged sectional view of the main part of FIG. 2. It is. This device is roughly divided into a wafer ring driving means 10 for moving the chips divided vertically and horizontally by a pick-up position t+ feet, and a tape reel means 3 for storing good chips.
0, a chip pickup means 50 for filling the tape of the tape reel means 30 with good chips from the wafer ring drive means 10, and a chip identification device 60 for identifying the chips set in the wafer ring drive means 10.

この手段１０は、特開昭５８−２２０４４１号公＠ｆこ
開示さｎたウェハリング駆動手段と同じ構成よりなる。This means 10 has the same structure as the wafer ring driving means disclosed in Japanese Patent Application Laid-Open No. 58-220441.

ウェハリングホルダ１１はＸ方向駆動用モータ１２によ
ってＸ方向に駆動されるＸテーブル１３に固定されてお
り、Ｘテーブル１３はＹ方向駆動用モータ１４によって
Ｙ方向に駆動されるＹテーブル１５に摺動自在に搭載さ
れている。即ち、Ｘテーブル１３とＹテーブル１５によ
ってＸＹテーブルを構成している。前記ウェハリングホ
ルダ１１には、ウェハリング１６を位置決め固定するた
めに、２本のピン１７．１８と爪１９とが設けられ、爪
１９はウェハリング１６をピン１７．１８ζこ押付ける
ように図示しないばねで付勢されでいる。The wafer ring holder 11 is fixed to an X table 13 that is driven in the X direction by an X direction drive motor 12, and the X table 13 slides on a Y table 15 that is driven in the Y direction by a Y direction drive motor 14. It is freely installed. That is, the X table 13 and the Y table 15 constitute an XY table. The wafer ring holder 11 is provided with two pins 17.18 and a claw 19 in order to position and fix the wafer ring 16, and the claw 19 is shown in the figure so as to press the wafer ring 16 against the pin 17. It is biased by a spring that does not work.

前記ウェハリング１６ｔこは縦横複数に等間隔にウェハ
が分割されたチップ２０が粘着シート上に貼付けられそ
の粘着シートが取付けられている。In the wafer ring 16t, chips 20 each having a wafer divided into a plurality of vertically and horizontally spaced chips are pasted on an adhesive sheet, and the adhesive sheet is attached thereto.

良品チップ２０を収納するフープ状のテープ３１は、チ
ップ２０より十分率さな穴３２ａが等間隔に明けられた
主テープ３２と、この主テープ３２の上面Ｉこ貼り合せ
られチップ２０が十分大る大きさの穴３３ａが前記穴３
２ａに対応した部分に明けられた補助テープ３３とより
構成されでいる。A hoop-shaped tape 31 that accommodates the good chip 20 is pasted to a main tape 32 in which holes 32a, which are sufficiently larger than the chips 20, are formed at equal intervals, and the upper surface of this main tape 32, so that the chip 20 is sufficiently large. The hole 33a is the size of the hole 3.
It is composed of an auxiliary tape 33 opened in a portion corresponding to 2a.

かかる構成よりなるテープ３１は架台３４に回転自在ζ
こ支承された空リール３５ｉこ巻回されており、架台３
６に回転自在に支承され図示しない駆動手段で間欠的に
駆動させられる充填リール３７１こ巻取られる。前記両
リール３５．３７間にはテープ３１を水平にガイドする
ガイドローラ３８．３９が回転自在に配設されている。The tape 31 having such a configuration is rotatably mounted on the stand 34.
This supported empty reel 35i is wound around the frame 3.
The filling reel 371 is rotatably supported on the filling reel 371 and is driven intermittently by a drive means (not shown). Guide rollers 38 and 39 for horizontally guiding the tape 31 are rotatably disposed between the reels 35 and 37.

また充填リール３７の上方にはフープ状のテープ上面カ
バー４０を巻回したカバーリール４１が架台４２に回転
自在に配設されており、充填リール３７の近傍に回転自
在に配設されたガイドローラ４３を通って前記テープ３
１の上面に重ね合せられて前記充填リール３７に巻取ら
れるようになっている。Further, above the filling reel 37, a cover reel 41 on which a hoop-shaped tape top cover 40 is wound is rotatably disposed on a pedestal 42, and a guide roller rotatably disposed near the filling reel 37. 43 and the tape 3
1 and wound onto the filling reel 37.

チップピックアップ手段５０（第１図参照〕この手段５
０は、特開昭５８−２２０４４１号公報に開示されたチ
ップピックアップ手段と同じ構成よりなる。Chip pickup means 50 (see FIG. 1) This means 5
0 has the same structure as the chip pickup means disclosed in Japanese Unexamined Patent Publication No. 58-220441.

チップ２０を吸着移送する移送コレット５１はコＶット
アーム５２の一端に固定されており、コンットアーム５
２の他端はスタンド５３に上下動及び旋回可能ｌこ設け
られた上下回転軸５４に固定されている。上下回転軸５
４の上下動及び旋回は図示しない機構によって行われる
。また前記ウェハリング１６の下方ｌこは前記チップ２
０を突き上げる突上げ針５５が設けられ、この突上げ針
５５はガイド５６に沿って図示しない駆動手段で上下動
させられる。A transfer collet 51 that suctions and transfers the chip 20 is fixed to one end of a cot arm 52.
The other end of 2 is fixed to a vertical rotation shaft 54 provided on a stand 53 so as to be able to move up and down and rotate. Vertical rotation axis 5
The vertical movement and rotation of 4 are performed by a mechanism not shown. Also, below the wafer ring 16 is the chip 2.
A push-up needle 55 for pushing up the 0 is provided, and the push-up needle 55 is moved up and down along a guide 56 by a drive means (not shown).

チップ識別装置６０（第１図参照） 前記突上げ針５５の真上上方にはチップ２０の良、不良
を判定するための検出カメラ６１が配設されており、こ
の検出カメラ６１は架台６２に固定されている。Chip identification device 60 (see FIG. 1) A detection camera 61 for determining whether the chip 20 is good or bad is disposed directly above the push-up needle 55, and this detection camera 61 is mounted on a pedestal 62. Fixed.

次にかから構成される装置の作動について説明する。ウ
ェハリング駆動手段１０のＸＹテーブル１３．１５の移
動によってピックアップされるチップ２０がピックアッ
プ位置に位置決めされると、チップ識別装置６０のカメ
ラ６１によってチップ２０の良、不良が識別される。チ
ップ２０が不良であると、再びＸＹテーブル１３．１５
が駆動して次のチップ２０がチップピックアップ位置に
位置決めされ、チップ２０の良、不良が識別される。Next, the operation of the device constructed as above will be explained. When the chip 20 to be picked up is positioned at the pickup position by the movement of the XY table 13.15 of the wafer ring driving means 10, the chip 20 is identified as good or bad by the camera 61 of the chip identification device 60. If the chip 20 is defective, the XY table 13.15
is driven to position the next chip 20 at the chip pickup position, and whether the chip 20 is good or bad is identified.

識別されたチップ２０が良品であると、上下回転軸５４
が下降及び上昇し、ウェハリング１６上のチ゛ツブ２０
を移送コＶット５１により真空吸着してピックアップす
る。続いて上下回転軸５４が回転して移送コレット５１
ｊこ吸着されたチップ２０はテープ３１の穴３３ａの上
方の所定位置に位置する。そして、上下回転軸５４が下
降し、移送コンット５１の真空が切れると、チップ２０
はテープ３１の穴３３ａ内に載置される。その後上下回
転軸５４は上昇及び前記と逆方向に回転し、移送コレラ
１−５１はウェハリング１６上のチップピックアップ位
置の上方に位置する。If the identified chip 20 is a good product, the vertical rotation shaft 54
is lowered and raised, and the chips 20 on the wafer ring 16
is vacuum-adsorbed and picked up by the transfer cot 51. Subsequently, the vertical rotation shaft 54 rotates, and the transfer collet 51
The attracted chip 20 is located at a predetermined position above the hole 33a of the tape 31. Then, when the vertical rotation shaft 54 descends and the vacuum of the transfer cont 51 is cut off, the chip 20
is placed in the hole 33a of the tape 31. Thereafter, the vertical rotation shaft 54 rises and rotates in the opposite direction, and the transferred cholera 1-51 is located above the chip pickup position on the wafer ring 16.

前記のようにウェハリング１６上より移送コンット５１
によって良品チップ２０がピックアップされる毎に前記
したようにＸＹテーブル１３．１５が駆動してチップ２
０の良、不良がカメラ６１によって識別される。またテ
ープ３１に良品チップ２０が収納し終る毎に充填リール
３７は穴３３ａのピ゛ソチ間隔だけ間欠的に駆動され、
良品チップ２０が収納されたテープ３１は上面にテープ
上面カバー４０が重ね合せられ、充填リール３７に巻取
られる。As mentioned above, the transfer cont 51 is moved from above the wafer ring 16.
Every time a good chip 20 is picked up by
The camera 61 identifies 0 as good or bad. Furthermore, every time a good chip 20 is stored in the tape 31, the filling reel 37 is intermittently driven by the distance between the holes 33a.
A tape top cover 40 is superimposed on the top surface of the tape 31 containing the good chips 20, and the tape 31 is wound onto a filling reel 37.

このように、良品チップ２ｏをテープ３１に収納して充
填リール３７に巻取るので、非常に多くの良品チップ２
０を収容できる。従って、かさばらなく管理上優れてい
ると共に、次の工程１こおけるチップボンダにおいては
、前記のように多数の良品チップ２０が収容されたテー
プ３１を巻回した充填リール３７をセットして使用でき
るので、チップボンダの稼動率が一層向上する。In this way, since the good chips 2o are stored in the tape 31 and wound up on the filling reel 37, a large number of good chips 2o are stored.
Can accommodate 0. Therefore, it is not bulky and is easy to manage, and in the chip bonder used in the next step, the filling reel 37 wound with the tape 31 containing a large number of good chips 20 can be set and used as described above. , the operating rate of the chip bonder is further improved.

なお、上記実施例１こおいては、テープ３０こテープ上
面カバー４０を重ねたが、主テープ３２のダイ２０側の
面を弱い粘着剤を塗布しておくと。In the first embodiment, the tape 30 and the tape top cover 40 are overlapped, but a weak adhesive may be applied to the surface of the main tape 32 on the die 20 side.

チップ２０は主テープ３２の粘着剤に保持されるので、
特にテープ上面カバー４０を設けなくてもよい。Since the chip 20 is held by the adhesive of the main tape 32,
In particular, it is not necessary to provide the tape top cover 40.

（発明の効果） 以上の説明から明らかな如く、本発明によれば、テープ
の凹部に良品チップを収納し、この良品チップを収納し
たテープを充填リールに巻回して保管できるので、かさ
ばらなく、またごみなどの付着もなく、管理上優れると
共に、次工程９）チップボンダの稼動率が一層向上する
。(Effects of the Invention) As is clear from the above description, according to the present invention, good chips can be stored in the recesses of the tape, and the tape containing the good chips can be wound around a filling reel and stored, without adding bulk. Further, there is no adhesion of dust, etc., which is excellent in terms of management, and the operation rate of the chip bonder in the next step 9) is further improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明になるチップテーピング装置の一実施例
を示す概略構成斜視図、第２図は第１図のテープリール
手段の正面図、第３図は第２図の要部拡大断面図である
。 １０・・・ウェハリング駆動手段、　１６・・・ウェハ
リング、　２０・・・チップ、　３０・・・テープリー
ル手段、　３１・・・テープ、　３３ａ・・・穴、３５
・・・空リール、３７・・・充填リール、５０・・・チ
ップピックアップ手段、　６０・・・チップ識別装置。 第１図FIG. 1 is a schematic perspective view showing an embodiment of the chip taping apparatus according to the present invention, FIG. 2 is a front view of the tape reel means shown in FIG. 1, and FIG. 3 is an enlarged sectional view of the main part of FIG. 2. It is. DESCRIPTION OF SYMBOLS 10... Wafer ring drive means, 16... Wafer ring, 20... Chip, 30... Tape reel means, 31... Tape, 33a... Hole, 35
... Empty reel, 37... Filling reel, 50... Chip pickup means, 60... Chip identification device. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 縦横に配列された多数のチップが設けられたつするチッ
プ識別装置と、この識別されたウェハリング上の良品チ
ップを１個づつピックアップして所定のチップ収納位置
ｆこ移動するチップピックアップ手段とを備えたチップ
テーピング装置において、チップを収納する凹部が等間
隔に形成されたテープと、このテープを巻回した空リー
ルと、この空リールより一定距離離れて配設され空リー
ルに巻回されたテープをこのテープの凹部ピッチ間隔づ
つ巻取る充填リールとよりなるテープリール手段を備え
、前記テープの凹部が前記チップ収納位置に位置するよ
うに前記テープリール手段を配設したことを特徴とする
チップテーピング装置。The chip identification device includes a chip identification device having a large number of chips arranged vertically and horizontally, and chip pickup means for picking up the identified good chips on the wafer ring one by one and moving them to a predetermined chip storage position f. In a chip taping device, a tape having concave portions for storing chips formed at equal intervals, an empty reel around which this tape is wound, and a tape placed a certain distance away from the empty reel and wound around the empty reel. A chip taping device comprising: a filling reel for winding the tape at intervals of a concave pitch interval; and a tape reel means disposed such that the concave portions of the tape are located at the chip storage position. Device.
JP4285384A 1984-03-08 1984-03-08 Chip taping apparatus Pending JPS60189228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4285384A JPS60189228A (en) 1984-03-08 1984-03-08 Chip taping apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4285384A JPS60189228A (en) 1984-03-08 1984-03-08 Chip taping apparatus

Publications (1)

Publication Number Publication Date
JPS60189228A true JPS60189228A (en) 1985-09-26

Family

ID=12647571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4285384A Pending JPS60189228A (en) 1984-03-08 1984-03-08 Chip taping apparatus

Country Status (1)

Country Link
JP (1) JPS60189228A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04219955A (en) * 1990-12-20 1992-08-11 Matsushita Electric Ind Co Ltd Taping and packaging method of electronic chip component
JP2006049877A (en) * 2004-07-09 2006-02-16 Semiconductor Energy Lab Co Ltd Ic chip and method of manufacturing the same
SG152128A1 (en) * 2007-10-23 2009-05-29 Emutech Co Ltd Chip transporting method and the device thereof
US8426293B2 (en) 2004-07-09 2013-04-23 Semiconductor Energy Laboratory Co., Ltd. IC chip and its manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588944B2 (en) * 1981-04-01 1983-02-18 アイワ株式会社 How to solder electrical parts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS588944B2 (en) * 1981-04-01 1983-02-18 アイワ株式会社 How to solder electrical parts

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04219955A (en) * 1990-12-20 1992-08-11 Matsushita Electric Ind Co Ltd Taping and packaging method of electronic chip component
JP2006049877A (en) * 2004-07-09 2006-02-16 Semiconductor Energy Lab Co Ltd Ic chip and method of manufacturing the same
US8426293B2 (en) 2004-07-09 2013-04-23 Semiconductor Energy Laboratory Co., Ltd. IC chip and its manufacturing method
SG152128A1 (en) * 2007-10-23 2009-05-29 Emutech Co Ltd Chip transporting method and the device thereof

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