JPS60189124U - Bias circuit for static induction field effect transistor - Google Patents
Bias circuit for static induction field effect transistorInfo
- Publication number
- JPS60189124U JPS60189124U JP7701784U JP7701784U JPS60189124U JP S60189124 U JPS60189124 U JP S60189124U JP 7701784 U JP7701784 U JP 7701784U JP 7701784 U JP7701784 U JP 7701784U JP S60189124 U JPS60189124 U JP S60189124U
- Authority
- JP
- Japan
- Prior art keywords
- pair
- field effect
- effect transistor
- circuit
- input terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例によるゲートバイアス回路を
示す回路図、第２図は第１図の回路の動作を説明するた
めの図、第３図はＳＩＴのＶ−１特性を示す図、第４図
は従来のゲートバイアス回路を有するＢ級増幅回路を示
す回路図、第５図は第４図の回路の動作を説明するため
の図、第６図は第４図の５ＩＴＩＱ□及び１０□の動作
ラインとアイドリング電流１１を示す図である。
１０１及び１０２・・−３ＩＴ、 ２０． ２０を及び
２０゜・・・ゲートバイアス回路、ＩＮｌ及びＩＮ２・
・・一対の入力端子、０ＵＴ１及び０ＵＴ２・・・一対
の出力端子、−Ｑ□・・・トランジスタ、Ｒ１・・・放
電用抵抗１、Ｃ１及びＣ２・・・コンデンサ。
゛−一一令時間FIG. 1 is a circuit diagram showing a gate bias circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the circuit in FIG. 1, and FIG. 3 is a diagram showing the V-1 characteristic of SIT. , FIG. 4 is a circuit diagram showing a class B amplifier circuit having a conventional gate bias circuit, FIG. 5 is a diagram for explaining the operation of the circuit in FIG. 4, and FIG. 10 is a diagram showing an operating line of 10□ and an idling current 11. FIG. 101 and 102...-3IT, 20. 20 and 20°...gate bias circuit, INl and IN2.
... A pair of input terminals, 0UT1 and 0UT2 ... A pair of output terminals, -Q□ ... Transistor, R1 ... Discharge resistor 1, C1 and C2 ... Capacitor.゛-11th age
Claims (1)
端子に接続される一対の出力端子と、電′ 源電圧
が入力される一対の入力端子と、該一対の入力端子及び
前記一対の出力端子間に接続されたシリーズ・レギュレ
ータ型定電圧回路を有し、該定電圧回路は、前記一対の
入力端子の一方及び前記一対の出力端子の一方間にコレ
クタ及びエミッタを接続されたトランジスタを有すると
共に、前記一対の入力端子の一方と、前記一対の入力端
子の他方及び−前記一対の出力端子の他方間を接続する
接続線と、前記トランジスタのベースとの間に、接続さ
れた規定バイアス電圧を設定するための規定バイア゛ス
設定回路を有している前記静電誘導型電界効果トランジ
スタのゲートバイアス回路において、前記一対の入力端
子の一方と前記トランジスタのベースとの間にコンデン
サを接続したことを特徴とする静電誘導型電界効果ｌ・
ランジスタのバイアス回路。A pair of output terminals connected to the gate terminal and another terminal of the electrostatic induction field effect transistor, a pair of input terminals to which a power supply voltage is input, and a terminal between the pair of input terminals and the pair of output terminals. a series regulator type constant voltage circuit connected to the constant voltage circuit, the constant voltage circuit having a transistor having a collector and an emitter connected between one of the pair of input terminals and one of the pair of output terminals; Setting a specified bias voltage connected between one of the pair of input terminals, the other of the pair of input terminals, and the other of the pair of output terminals, and the base of the transistor. In the gate bias circuit of the electrostatic induction field effect transistor, which has a prescribed bias setting circuit for Characteristic electrostatic induction type electric field effect
transistor bias circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7701784U JPS60189124U (en) | 1984-05-28 | 1984-05-28 | Bias circuit for static induction field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7701784U JPS60189124U (en) | 1984-05-28 | 1984-05-28 | Bias circuit for static induction field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60189124U true JPS60189124U (en) | 1985-12-14 |
| JPH0246090Y2 JPH0246090Y2 (en) | 1990-12-05 |
Family
ID=30619693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7701784U Granted JPS60189124U (en) | 1984-05-28 | 1984-05-28 | Bias circuit for static induction field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189124U (en) |
-
1984
- 1984-05-28 JP JP7701784U patent/JPS60189124U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0246090Y2 (en) | 1990-12-05 |
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