JPS60184156U

JPS60184156U - multiplication circuit

Info

Publication number: JPS60184156U
Application number: JP6999784U
Authority: JP
Inventors: 紀之山下
Original assignee: ソニー株式会社
Priority date: 1984-05-14
Filing date: 1984-05-14
Publication date: 1985-12-06

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの考案の一実施例の回路図、第２図は従来の
掛算回路の一例の回路図、第３図は従来の掛算回路の他
の例の回路図である。１１．１２及び２１，２２はそれぞれ１対のトランジス
タ、４４及び４５は電流源、６１及び６２は第１及び第
２のトランジスタである。FIG. 1 is a circuit diagram of an embodiment of this invention, FIG. 2 is a circuit diagram of an example of a conventional multiplication circuit, and FIG. 3 is a circuit diagram of another example of a conventional multiplication circuit. 11. 12, 21 and 22 are each a pair of transistors, 44 and 45 are current sources, and 61 and 62 are first and second transistors.

Claims

【実用新案登録請求の範囲】[Scope of utility model registration request]

エミッタが共通に接続され、その接点が電流源に接続さ
れた第１及び第２の１対のトランジスタが設けられ、上
記第１及び第２の１対のトランジスタのそれぞれ一方の
トランジスタのコレクタが互いに接続されて第１の出力
端とされ、上記第１及び第２の１対のトランジスタのそ
れぞれ他方のトランジスタのコレクタが互いに接続され
て第２の出力端とされ、上記共通エミッタと電源端子と
の間に第３及び第４のトランジスタのコレクターエミッ
タ間がそれぞイエミッタが上記共通エミッタと接続され
る状態で挿入され、上記第１及び第２の１対のトランジ
スタの一方及び他方のトランジスタのベースに第１の入
力信号が差動でそれぞれ供給されるとともに上記第３及
び第４のトランジスタのベースに第２の入力信号が差動
で供給されるようになされた掛算回路。A first and second pair of transistors are provided whose emitters are commonly connected and whose contacts are connected to a current source, and the collectors of each of the first and second transistors are connected to each other. The collectors of the other of the first and second transistors are connected to each other to form a second output terminal, and the common emitter and the power supply terminal are connected to each other to form a first output terminal. A third and a fourth transistor are inserted between their collector emitters with their emitters connected to the common emitter, and are connected to the bases of one and the other of the first and second pair of transistors. A multiplication circuit, wherein the first input signals are differentially supplied, and the second input signals are differentially supplied to the bases of the third and fourth transistors.