JPS6017992A - Method of producing ceramic substrate for integrated circuit - Google Patents
Method of producing ceramic substrate for integrated circuitInfo
- Publication number
- JPS6017992A JPS6017992A JP12482583A JP12482583A JPS6017992A JP S6017992 A JPS6017992 A JP S6017992A JP 12482583 A JP12482583 A JP 12482583A JP 12482583 A JP12482583 A JP 12482583A JP S6017992 A JPS6017992 A JP S6017992A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- metallized layer
- integrated circuit
- firing
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、セラミック基板上に形成されたパターンへの
接続部を基板裏面に有する集積回路用セラミック基板の
製造法に関するものであり、さらに詳しくは例えば、プ
ラグインパッケージの如き集積回路パッケージのセラミ
ック基板を安定して）ｑる集積回路用セラミック）；１
板の製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a ceramic substrate for an integrated circuit having a connection portion to a pattern formed on the ceramic substrate on the back surface of the substrate, and more specifically, for example, for manufacturing a ceramic substrate for an integrated circuit. Ceramics for integrated circuits that stably support ceramic substrates of integrated circuit packages such as
This relates to a method for manufacturing plates.
従来、プラグインパッケージのような集積回路用セラミ
ック基板の製造法としては、例えば第１図に示すように
、セラミックグリーンシート１の表面にモリブデンある
いはタングステン等よりなるメタライズペーストでパタ
ーン２及び該パターンを裏面に接続するスルボール３及
び裏面にリード接続部となるメタライズ層４を印刷し、
ざらにその表面にパターン２の１部に開口するスルボー
ル５及び表面に印刷パターン６を右するセラミックグリ
ーンシート７を積層し、さらにその表面に印刷パターン
８を有するセラミックグリーンシート９を積層した積層
板をモリブデン等よりなる焼成用平板セッター１０の上
に載置して還元雰囲気中で焼成する方法が広く知られて
いる。Conventionally, as shown in FIG. 1, a conventional method for manufacturing a ceramic substrate for an integrated circuit such as a plug-in package involves forming a pattern 2 on the surface of a ceramic green sheet 1 with a metallized paste made of molybdenum, tungsten, or the like. A through ball 3 to be connected to the back side and a metallized layer 4 which will be a lead connection part to the back side are printed,
A laminated plate in which a through ball 5 having an opening in a part of the pattern 2 on its surface and a ceramic green sheet 7 having a printed pattern 6 on its surface are laminated, and a ceramic green sheet 9 having a printed pattern 8 on its surface is further laminated. A widely known method is to place the material on a firing flat plate setter 10 made of molybdenum or the like and fire it in a reducing atmosphere.
しかしながら、このＪ：うな従来の集積回路用ヒラミッ
ク基板のＶ造法はセラミックグリーンシー１〜１の裏面
に露出した、例えば多数のリード取付り用メタライズ層
４が焼成中に焼成用平板セッター１０に溶融接着し製品
不良が発生する問題点があった。又、この問題点をなく
すため、メタライズ層１がしツタ−１０に接触しないよ
うに両者間にスペーク−（図示ぜず）を介在させて焼成
するかあるいは積層板を前記と上下逆にして焼成する方
法も知られているが、いずれも積層板に反りが生ずる欠
点があった。However, in the conventional V manufacturing method of the ceramic substrate for integrated circuits, for example, a large number of metallized layers 4 for attaching leads exposed on the back surface of the ceramic green sheets 1 to 1 are placed on the firing flat plate setter 10 during firing. There was a problem in that the product was defective due to melt adhesion. In order to eliminate this problem, the metallized layer 1 may be fired with a space (not shown) interposed between them so that it does not come into contact with the vine 10, or the laminate may be fired upside down. There are also known methods to do this, but all of them have the drawback of causing warpage in the laminate.
本発明は、セラミック基板の裏面に例えば多数のロウ（
ＪＩ：Ｊ用メタライズ層が露出した例えばプラグインパ
ッケージの如ぎ集積回路用セラミックの基板をその焼成
中における反り、メタライズ層の相ｎ溶着等を全くなく
して安定して得るセラミック基板の製造法を提供するこ
とにある。According to the present invention, for example, a large number of waxes (
JI: A method for producing a ceramic substrate for an integrated circuit, such as a plug-in package, in which the metallized layer for J is exposed, by completely eliminating warping during firing, phase-n welding of the metallized layer, etc. It is about providing.
本発明はセラミック基板内に形成されたパターンと導通
Ｊ−るメタライズ層が基板裏面に露出して成る集積回路
用セラミックの基板の製造法において、基板裏面に露出
したメタライズ層の少なくとも１部を露出させてセラミ
ック基板裏面にメタライズ層の〜みＪ、す１９い絶縁層
を塗イ１１シ、メタライズ層を焼成用ヒツターと」１接
触状ｒ１りとしＣ−焼成する集積回路用ｌ！フミック＋
７４仮の１１１造法である。The present invention relates to a method for manufacturing a ceramic substrate for an integrated circuit in which a metallized layer that is conductive to a pattern formed in a ceramic substrate is exposed on the back surface of the substrate, in which at least a part of the metallized layer exposed on the back surface of the substrate is exposed. Then apply a metallized layer to the back surface of the ceramic substrate, apply a thin insulating layer, place the metallized layer in contact with a firing heater, and then bake the integrated circuit. Humic+
74 temporary 111 construction method.
本発明の史に詳しい４部成をぞの一↓−４体例を承り第
２図に３１づいて説明りるど、アルミナ、ベリリア等の
レラミックグリーンシ−１〜１１の表面にモリブデンあ
るいはタンゲスｊ″７４丁どのメタライスペース１へて
パターン１２及び該パターンを裏面に接続４るスルホー
ル１３及び裏面にリード接続部どなるメタライズＩＦｉ
１４を印刷し、更にこの−にに印刷パターン１６及び必
要に応じ下部パターン１２と接続するスルホール１５を
右するグリーンシー１〜１７を複数枚積層する。そして
更にレラミックグリーンシー１−１１の裏面に好Ｊ、し
くけ裏面のメタライズＭ１４の中央部を残しメタライズ
層１４の外周部を含み好ましくは、グリーンシートと同
祠質よりなる絶縁層２１を印刷塗布り−る。そ１）でこ
れらの積層板を乾燥後、金属モリブデン等よりなる焼成
用平板ｌ？フッタ２０の上に絶縁層２１を接触させて載
若し、ｔ？ラミック基板１１の裏面のメタライズ層１４
をレッター２０と非３−
接触４人態として還元雰囲気中で焼成して集積回路用セ
ラミック基板を製造するものである。The history of this invention is explained in detail with reference to Figure 2, based on the 4-part structure 1↓-4 example.Molybdenum or tanges is added to the surface of Relamic Green Sea-1 to 11 made of alumina, beryllia, etc. j''74 metallization space 1 to pattern 12, through hole 13 connecting the pattern to the back side, and metallization IFi to the back side for lead connection.
14 is printed, and then a plurality of sheets of green sheets 1 to 17 are laminated on top of the printed pattern 16 and, if necessary, a plurality of green sheets 1 to 17 that have through holes 15 connected to the lower pattern 12. Then, on the back side of the Relamic Green Sheet 1-11, an insulating layer 21 is preferably printed, which is preferably made of the same abrasive quality as the green sheet, and includes the outer periphery of the metallized layer 14, leaving the central part of the metallized layer M14 on the back side of the mechanism. Apply. After drying these laminated plates in step 1), a flat plate for firing made of metal molybdenum or the like is prepared. If the insulating layer 21 is placed on the footer 20 in contact with it, then t? Metallized layer 14 on the back side of the ramic substrate 11
A ceramic substrate for an integrated circuit is manufactured by firing the ceramic substrate in a reducing atmosphere in a non-contact state with the letter 20.
なお、セラミック基板１１の裏面に塗布Ｊ−る絶縁層２
１は、メタライズ層１４をレッター２０と非接触状態と
するためにメタライズ層１４の厚みより厚い膜厚が必要
である。そして好ましくは絶縁層２１はメタライズ層１
４の中央部を除きメタライズ層１４の外周部に重ねて印
刷することが良く、その絶縁層２１の厚みは１０〜５０
μｍ程度が良い。Note that an insulating layer 2 coated on the back surface of the ceramic substrate 11
1 requires a film thickness greater than that of the metallized layer 14 in order to keep the metallized layer 14 out of contact with the letter 20. And preferably, the insulating layer 21 is the metallized layer 1
It is preferable to print overlappingly on the outer peripheral part of the metallized layer 14 except for the central part of the insulating layer 21, and the thickness of the insulating layer 21 is 10 to 50 mm.
About μm is good.
そして、焼成後のセラミック基板に対しては、セラミッ
ク基板１１の裏面の絶縁層２１間に開口するメタライズ
層１４にリード線又は導体ビン（いずれも図示せず）を
ロウイ］【プ等により固着すると、例えばプラグインパ
ッケージ等のセラミックパッケージが出来上るものであ
る。Then, for the ceramic substrate after firing, lead wires or conductor bottles (none of which are shown) are fixed to the metallized layer 14 opened between the insulating layers 21 on the back side of the ceramic substrate 11 using a low wire or the like. For example, a ceramic package such as a plug-in package is completed.
本発明によれば次のＪ：うな効果が得られる。According to the present invention, the following J: Una effect can be obtained.
（１）メタライズ層１４ど焼成用セッター２１との溶着
が完全に防止できる。(1) Welding of the metallized layer 14 to the firing setter 21 can be completely prevented.
（２）焼成用レッター２０への基板の詰め作業効率を茗
しく高めることが出来る。(2) The efficiency of packing substrates into the firing letter 20 can be greatly improved.
４− （３）品質の安定したセラミック基板が製造できる。4- (3) Ceramic substrates with stable quality can be manufactured.
又、本発明は次のよう４ｆ製晶の製造法として利用出来
る。Further, the present invention can be used as a method for producing 4f crystals as follows.
■プラグインパッケージ基板 ■ＤＩＰ形パッケージ基板 ■多層配線基板 ■トランジスターパッケージ基板■Plug-in package board ■DIP type package board ■Multilayer wiring board ■Transistor package board
第１図は従来の集積回路用セラミック基板の焼成状態を
模式的に示を説明図であり、
第２図は本発明の集積回路用セラミック基板の焼成状態
を模式的に示す説明図である。
１．７，９，１１，１７．１９・・・セラｆミックグリ
ーンシー１〜２．６，８，１２，１６．１８川パターン
３．５，１３．１５・・・スルホール
４．１４・・・メタライズ層
１０．２０・・・焼成用平板セッター
２１・・・絶縁層FIG. 1 is an explanatory diagram schematically showing the firing state of a conventional ceramic substrate for integrated circuits, and FIG. 2 is an explanatory diagram schematically showing the firing state of the ceramic substrate for integrated circuits of the present invention. 1.7, 9, 11, 17.19... Ceramic Green Sea 1-2.6, 8, 12, 16.18 River pattern 3.5, 13.15... Through hole 4.14...・Metallized layer 10.20...Flat plate setter for firing 21...Insulating layer
Claims (1)
メタライズ層が基板裏面に露出して成る集積回路用セラ
ミック基板の製造法において、基板裏面に露出したメタ
ライズ層の少なくとも１部を除き、セラミック基板裏面
にメタライズ層の厚みより厚い絶縁層を塗布し、メタラ
イズ層を焼成用レッターと非接触状態として焼成するこ
とを特徴どする集積回路用セラミック基板の製造法。 ２、絶縁層をメタライズ層の外周部を含む基板裏面に塗
布する特許請求の範囲第１項記載の集積回路用セラミッ
ク基板の製造法。[Claims] 1. A method for manufacturing a ceramic substrate for an integrated circuit in which a metallized layer conductive to a pattern formed on a ceramic substrate is exposed on the back surface of the substrate, in which at least a portion of the metallized layer exposed on the back surface of the substrate is provided. A method of manufacturing a ceramic substrate for integrated circuits, which is characterized by applying an insulating layer thicker than the thickness of the metallized layer to the back surface of the ceramic substrate, and firing the metallized layer without contacting the firing letter. 2. The method of manufacturing a ceramic substrate for an integrated circuit according to claim 1, wherein the insulating layer is applied to the back surface of the substrate including the outer peripheral portion of the metallized layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12482583A JPS6017992A (en) | 1983-07-11 | 1983-07-11 | Method of producing ceramic substrate for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12482583A JPS6017992A (en) | 1983-07-11 | 1983-07-11 | Method of producing ceramic substrate for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6017992A true JPS6017992A (en) | 1985-01-29 |
| JPS6350861B2 JPS6350861B2 (en) | 1988-10-12 |
Family
ID=14895034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12482583A Granted JPS6017992A (en) | 1983-07-11 | 1983-07-11 | Method of producing ceramic substrate for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6017992A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439599A (en) * | 1990-06-01 | 1992-02-10 | Hidaka Seiki Kk | Manufacture of fin for heat exchanger |
| JPH05144967A (en) * | 1991-11-19 | 1993-06-11 | Kyocera Corp | Manufacture of package for containing semiconductor element |
-
1983
- 1983-07-11 JP JP12482583A patent/JPS6017992A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0439599A (en) * | 1990-06-01 | 1992-02-10 | Hidaka Seiki Kk | Manufacture of fin for heat exchanger |
| JPH05144967A (en) * | 1991-11-19 | 1993-06-11 | Kyocera Corp | Manufacture of package for containing semiconductor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6350861B2 (en) | 1988-10-12 |
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