JPS60176251A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60176251A JPS60176251A JP3285684A JP3285684A JPS60176251A JP S60176251 A JPS60176251 A JP S60176251A JP 3285684 A JP3285684 A JP 3285684A JP 3285684 A JP3285684 A JP 3285684A JP S60176251 A JPS60176251 A JP S60176251A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- wiring layers
- layer wiring
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(技術分野)
本発明は半導体装置にかがシ、とくに多層配線構造を有
する半導体装置とくに半導体集積回路装置に於いてその
配線パターンに工夫をこらし上層配線の短絡を防止する
配線形状に関する。Detailed Description of the Invention (Technical Field) The present invention provides protection for semiconductor devices, particularly semiconductor devices having a multilayer wiring structure, particularly semiconductor integrated circuit devices, by devising the wiring pattern to prevent short circuits in upper layer wiring. Regarding the wiring shape.
(従来技術)
半導体集積回路に於いては、集積度の増大に伴ない多層
配線構造の採用が不可避となっている。(Prior Art) In semiconductor integrated circuits, as the degree of integration increases, it is inevitable to adopt a multilayer wiring structure.
多層配線構造は配線のトポロジカルな自由度の増大によ
る設計の容易化と配線面積の減少によるチップ面積の縮
小化という大きな利点があるものの上層配線が下層配線
の大きな段をまたいで配設される為、特に上層配線が下
配配嬶の段iを狭い配線間隔で平行して歩る場合、該段
部における上層配線間の短絡という問題が存在する。即
ち最近の配線形成プ・ロセスに於いては、配線用金属の
エツチングには微細配線を精度よく形成する必要から異
方性のドライエッチが主流となっている。この異方性ド
ライエツチングはエツチングが異方的に進行するため、
レジストパターン通シにエツチングされる反面、急峻な
段部が存在すると、該段部での実効的な金属膜厚が厚く
なるため、該段部でのエツチング残シが発生し易くなる
。上層配線の配線間隔が狭くなると、この現象による上
層配線間の短絡の可能性は一層高くなる。Although the multilayer wiring structure has the major advantages of facilitating design by increasing the topological freedom of wiring and reducing the chip area by reducing the wiring area, it is because the upper layer wiring is arranged across large steps of the lower layer wiring. In particular, when upper layer wirings walk parallel to each other with narrow wiring intervals in step i of the lower wiring, there is a problem of short-circuiting between the upper layer wirings at the step portion. That is, in recent wiring forming processes, anisotropic dry etching has become mainstream for etching metal for wiring because it is necessary to form fine wiring with high precision. In this anisotropic dry etching, etching progresses anisotropically, so
Although etching is performed through the resist pattern, if there is a steep step, the effective metal film thickness at the step increases, and etching residue is likely to occur at the step. As the spacing between the upper layer wirings becomes narrower, the possibility of a short circuit between the upper layer wirings due to this phenomenon becomes higher.
(発明の目的)
本発明の目的はかかる従来技術の欠点を除去した有効な
半導体装置を提供することである。(Object of the Invention) An object of the present invention is to provide an effective semiconductor device that eliminates the drawbacks of the prior art.
(発明の構成)
本発明はかかる下層配線の段部での上層配線間の短絡の
可能性を低減すべく下層配線の段差部を平行して通過す
る上層配線の対向する2辺を段差部において相対的に後
退させて間隔を拡げ上層配線間の短絡を防止することに
ある。(Structure of the Invention) In order to reduce the possibility of a short circuit between the upper layer wirings at the stepped portion of the lower layer wiring, the present invention provides two opposing sides of the upper layer wiring passing in parallel to the stepped portion of the lower layer wiring at the stepped portion. The purpose is to prevent short circuits between upper layer wirings by moving them relatively backward to widen the interval.
(実施例の説明)
第1図においてはシリコン基板1の表面に形成されたシ
リコン酸化膜2上を第1層目の配線層3が配設され、そ
の上を絶縁物4で覆った状態の断面構造である。第1層
目の配線層3の段差はそのまま絶縁物4にも反映され絶
縁物にも段差5が形成されている。かかる状態の絶縁物
上に配線用金属を被着した後、通常のレジスト塗布、目
金露光を行ない第2層目の配線のリンストノくターンを
配積用金属上に形成する。かかる状態で異方性ドライエ
ツチングを行なうと、エツチングがシリコンウェハース
に対し垂直方向の異方性をもって退行するため、段差部
でエツチング残りが発生し易く、第2層目の配線の短絡
が起き易くなる。(Explanation of Embodiment) In FIG. 1, a first wiring layer 3 is disposed on a silicon oxide film 2 formed on the surface of a silicon substrate 1, and an insulating material 4 is covered thereon. It has a cross-sectional structure. The step difference in the first wiring layer 3 is directly reflected on the insulator 4, and a step 5 is also formed in the insulator. After the wiring metal is deposited on the insulator in such a state, ordinary resist coating and eyelid exposure are performed to form the rinse strips of the second layer of wiring on the wiring metal. If anisotropic dry etching is performed in such a state, the etching regresses with anisotropy in the direction perpendicular to the silicon wafer, which tends to leave etching residue on the stepped portions and short circuits in the second layer wiring. Become.
第2図は従来技術を示す平面図であシ、第2層目の配線
層のエツチングが完了した時点での平面図である。第1
層目の配線層3をまたいで第2層目の配線層7が平行に
2本走っている。8〜11は第1層目の配線段差部での
すなわちその上の絶縁物4における段差部での第2層目
の配線金属の残シである。8,10.11は第2層目の
配線層間短絡をひき起こす可能性があり、9の金属桟シ
は完全に第2層目の配線層間の短絡をひき起こしている
。この様な段部での金属桟シによる配線間短絡は配線間
隔が狭くなると急激に増大し、良品チップ歩留の低下を
ひき起こす。FIG. 2 is a plan view showing the prior art, and is a plan view at the time when etching of the second wiring layer is completed. 1st
Two second wiring layers 7 run in parallel across the second wiring layer 3. Reference numerals 8 to 11 indicate the residue of the second layer wiring metal at the step portion of the first layer wiring, that is, at the step portion of the insulator 4 thereon. Nos. 8, 10, and 11 may cause a short circuit between the second wiring layers, and the metal crosspiece 9 completely causes a short circuit between the second wiring layers. Such short circuits between wires due to the metal crosspiece at the stepped portion increase rapidly as the wire spacing becomes narrower, causing a decrease in the yield of non-defective chips.
本発明は下層配線段部での上層配線間の短絡の可能性を
低減すべく、下層配線に直交し、下層配線の段差部を平
行して走る複数の上層配素の対向する2辺を該段差部に
おいて相直的に後退させて間隔を拡げ、上層配線間の短
絡の可能性を低減することにある。In order to reduce the possibility of short-circuiting between upper layer wirings at a stepped portion of lower layer wiring, the present invention aims to connect two opposing sides of a plurality of upper layer interconnects that are perpendicular to the lower layer wiring and run parallel to the stepped portion of the lower layer wiring. The purpose is to rectify the gap at the stepped portion to widen the interval, thereby reducing the possibility of short circuit between the upper layer wirings.
第3図は本発明の実施例を示すもので、第2層目のパタ
ーンで第2層目配線層のエツチングが完了した時点での
平面図である。第1層目の配線層3をまたいで層内絶縁
物(第1図)を介して第2層目の配線層13が複数本平
行に走っている。FIG. 3 shows an embodiment of the present invention, and is a plan view at the time when etching of the second wiring layer with the second layer pattern is completed. A plurality of second wiring layers 13 run in parallel across the first wiring layer 3 via an interlayer insulator (FIG. 1).
14〜17は第1層目の配線層の段差部で第2層目の配
線層の対向する2辺を後退させたパターン部を示す。こ
れによ)、該段差部での第2N目の配線層間隔が拡がり
、該段差部での金属桟りによる第2層目の配線層間短絡
の可能性が低減される。Reference numerals 14 to 17 indicate pattern portions in which two opposing sides of the second wiring layer are set back at step portions of the first wiring layer. As a result, the interval between the 2Nth wiring layers at the stepped portion is increased, and the possibility of a short circuit between the second wiring layers due to the metal crosspiece at the stepped portion is reduced.
該段差部での第2層配線パターンの四部は対向する2辺
に設けてもよく、又−辺にの、み設けてもよい。The four portions of the second layer wiring pattern at the stepped portion may be provided on two opposing sides, or may be provided only on the - side.
本発明になる配線パターン構造を採用すれ4、増々集積
度の増大する半導体集積回路において、1配線形成の安
定性が増し、良品歩留の向上が実現できる。By employing the wiring pattern structure of the present invention,4 the stability of forming one wiring can be increased and the yield of good products can be improved in semiconductor integrated circuits whose degree of integration is increasing.
第1図は第1層目の配線を形成した状態を示す断面図で
!り、a、第2図は従来技術を示す平面図であシ、第3
図は本発明の実施例を示す平面図である。
尚、図において、1・・・・・・シリコン半導体基板、
2・・・・・・二酸化シリコン膜等の絶縁膜、3・・・
・・・下層配線である211層目の配線層、4・・・・
・・C0■ハ二酸化シリコン等の層間絶縁層、5・・・
・・・段差、7゜13・・・・・・上層の配線である第
2層目の配線層、14.15,16.17・・・・・・
本発明による凹部の平面パターンである。Figure 1 is a cross-sectional view showing the state in which the first layer of wiring has been formed! Figure 2 is a plan view showing the prior art.
The figure is a plan view showing an embodiment of the present invention. In addition, in the figure, 1... silicon semiconductor substrate,
2... Insulating film such as silicon dioxide film, 3...
...The 211th wiring layer, which is the lower layer wiring, 4...
・・C0■ Interlayer insulating layer such as silicon dioxide, 5...
...Level difference, 7°13...Second wiring layer, which is upper layer wiring, 14.15, 16.17...
It is a plane pattern of a recessed part according to the present invention.
Claims (1)
いし複数本の下層配線上を該下層配線に直交した複数本
の上層配線において、該下層配線の段差部を通過する上
層配線の対向する2′lLを該段差部において相対的に
後退させ、該段差部における該上層配線間隔を他の部分
における間隔に比して拡大させたことを特徴とする半導
体装置。In a plurality of upper layer wirings which are perpendicular to one or more lower layer wirings disposed in a semiconductor device having a multilayer wiring structure and are perpendicular to the lower layer wirings, the upper layer wirings passing through the stepped portions of the lower layer wirings face each other. 2'lL is relatively set back at the stepped portion, and the upper layer wiring spacing at the stepped portion is expanded compared to the spacing at other portions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3285684A JPS60176251A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3285684A JPS60176251A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60176251A true JPS60176251A (en) | 1985-09-10 |
JPH0230180B2 JPH0230180B2 (en) | 1990-07-04 |
Family
ID=12370479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3285684A Granted JPS60176251A (en) | 1984-02-23 | 1984-02-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60176251A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5317185A (en) * | 1990-11-06 | 1994-05-31 | Motorola, Inc. | Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same |
US5462767A (en) * | 1985-09-21 | 1995-10-31 | Semiconductor Energy Laboratory Co., Ltd. | CVD of conformal coatings over a depression using alkylmetal precursors |
US5567989A (en) * | 1993-07-27 | 1996-10-22 | Samsung Electronics Co., Ltd. | Highly integrated semiconductor wiring structure |
US5894170A (en) * | 1996-08-29 | 1999-04-13 | Nec Corporation | Wiring layer in semiconductor device |
JP2010034236A (en) * | 2008-07-28 | 2010-02-12 | Panasonic Corp | Solid-state image pickup device and method for fabricating the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5791523A (en) * | 1980-11-28 | 1982-06-07 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-02-23 JP JP3285684A patent/JPS60176251A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5791523A (en) * | 1980-11-28 | 1982-06-07 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5462767A (en) * | 1985-09-21 | 1995-10-31 | Semiconductor Energy Laboratory Co., Ltd. | CVD of conformal coatings over a depression using alkylmetal precursors |
US5317185A (en) * | 1990-11-06 | 1994-05-31 | Motorola, Inc. | Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same |
US5567989A (en) * | 1993-07-27 | 1996-10-22 | Samsung Electronics Co., Ltd. | Highly integrated semiconductor wiring structure |
US5894170A (en) * | 1996-08-29 | 1999-04-13 | Nec Corporation | Wiring layer in semiconductor device |
JP2010034236A (en) * | 2008-07-28 | 2010-02-12 | Panasonic Corp | Solid-state image pickup device and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0230180B2 (en) | 1990-07-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |