JPS59148347A - Method for forming wiring metal for semiconductor device - Google Patents
Method for forming wiring metal for semiconductor deviceInfo
- Publication number
- JPS59148347A JPS59148347A JP2230683A JP2230683A JPS59148347A JP S59148347 A JPS59148347 A JP S59148347A JP 2230683 A JP2230683 A JP 2230683A JP 2230683 A JP2230683 A JP 2230683A JP S59148347 A JPS59148347 A JP S59148347A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- wiring metal
- layer wiring
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は、多層金属配線金有する集積回路製造工程にお
いて、配線金属のパターン形成後の熱処理により、配線
形状を傾斜化し、第一層、第二層配線の交差する断差部
における第二層配線の断線全防止した、半導体装置の配
線金属の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION In the manufacturing process of integrated circuits having multilayer metal wiring, the wiring shape is sloped by heat treatment after patterning of the wiring metal, and the cross-cuts of the first and second layer wirings are created. The present invention relates to a method for forming wiring metal of a semiconductor device, which completely prevents disconnection of the second layer wiring at the difference portion.
近年、集積回路の素子寸法の微細化にともないレジスト
パターンに対する忠実性の良いドライエツチングを用い
ることによる併置を現れてきた。In recent years, with the miniaturization of the element dimensions of integrated circuits, the use of dry etching with good fidelity to the resist pattern has emerged.
すなわち、レジストパターン忠実性が向上した反面、交
差する第二層配線が急峻な断差によって断線しやすいと
いう欠点がある。以下、図面を用いてこれを説明する。That is, although resist pattern fidelity has been improved, there is a drawback that intersecting second-layer wiring is likely to be disconnected due to a steep difference. This will be explained below using the drawings.
＄１図の、１．９に、素子を構成する拡散層を含むシリ
コン基板１の上に、ｃｖＤ法等を用論で形成した絶縁層
２を介しで、第一層配線バクーン３を形成する。必要に
応じで、酸化膜２ｖＣは拡散層と電気的接ｆｆ１ｆｆｉ
取るためのコンタクトホール４ｆｒ、つくり、この部分
では第一層配線パターン５は拡散層に接触している。配
線パターン３お工び、コンタクトホール４の形成には既
知のフォトリングラフィ技術、ドライエツチング技術を
用いる。At 1.9 in Figure 1, a first layer wiring board 3 is formed on a silicon substrate 1 including a diffusion layer constituting an element, via an insulating layer 2 formed using a CVD method or the like. . If necessary, the oxide film 2vC is electrically connected to the diffusion layerff1ffi.
A contact hole 4fr is made to take the first layer wiring pattern 5 in contact with the diffusion layer at this portion. Known photolithography techniques and dry etching techniques are used to form the wiring pattern 3 and to form the contact holes 4.
次に、第２図のように、第一層、第二層配線の中間絶縁
層５１ｃＣ３ＶＤ法等を用いで形成した後。Next, as shown in FIG. 2, an intermediate insulating layer 51c of the first layer and second layer wiring is formed using a C3VD method or the like.
第一層配線バクーンと同様にして、第二層配線パターン
６を形成する。第２図には示していないが必要に応じて
、第二層配線と第一層配線’ｚ′ｆｃは拡散層を電気的
に接続するコンタクトホールを形成する。A second layer wiring pattern 6 is formed in the same manner as the first layer wiring pattern. Although not shown in FIG. 2, if necessary, the second layer wiring and the first layer wiring 'z'fc form a contact hole for electrically connecting the diffusion layer.
以上の従来法においては、第２図を見でわかるように、
ドライエツチングによって形成し７を第一層配線パター
ン６の急峻な断差ＶＣおいて、中間絶縁・層５．第二層
配線パターン６にくびれが生じ、この部分で第二層配線
の＃線が起こりやすい。In the above conventional method, as can be seen from Figure 2,
The intermediate insulating layer 5. is formed by dry etching, and the intermediate insulating layer 5. A constriction occurs in the second layer wiring pattern 6, and the # line of the second layer wiring is likely to occur in this portion.
本発明は、上記の問題全改善するためになされたもので
ある。以下、図面を用いて本発明を詳細Ｋｆｉ５１ＢＡ
する。The present invention has been made to alleviate all of the above problems. Hereinafter, the present invention will be explained in detail using the drawings.
do.
フォトリソグラフィ技術、ドライエツチング技術を用い
て、第一層配線パターンを形成する。A first layer wiring pattern is formed using photolithography technology and dry etching technology.
次に、赤外線またにレーザーによる急速熱処理全行な９
ことにより、第６図に示すように、第一層配線金属７の
断面形状を傾斜化する。この後、第４図のように中間絶
縁層８．第二層配線９を形成する。第一層配線７が傾斜
化しているため、断差部にかいても中間絶縁層８．第二
層配線９にはくびれは発生せず、断線がおこりにくい。Next, rapid heat treatment using infrared rays or laser is carried out.
As a result, as shown in FIG. 6, the cross-sectional shape of the first layer wiring metal 7 is made sloped. After this, as shown in FIG. 4, an intermediate insulating layer 8. A second layer wiring 9 is formed. Since the first layer wiring 7 is sloped, the intermediate insulating layer 8. No constriction occurs in the second layer wiring 9, and disconnection is less likely to occur.
熱処理の時間及び温度は配線金属の材質によって異なる
が、５重量パーセントのシリコンを含むアルミニウムの
場合、６００℃、３秒の赤外線熱処理によって、傾斜断
面形状が得られる。他の材料についでも、温度９時間を
変えて傾斜化できる。The time and temperature of the heat treatment vary depending on the material of the wiring metal, but in the case of aluminum containing 5 weight percent silicon, an inclined cross-sectional shape can be obtained by infrared heat treatment at 600° C. for 3 seconds. Other materials can also be graded by changing the temperature 9 hours.
なお、今１での説明では、説明の都合により。In addition, the explanation in Part 1 is for convenience of explanation.
二層配線の場合について説明したが、二層以上の配線金
属層を形成する半導体装置の製造工程についても、同様
に適用できることは言９″！！でもない。Although the case of two-layer wiring has been described, it goes without saying that the invention can be similarly applied to the manufacturing process of a semiconductor device in which two or more wiring metal layers are formed.
第１図と第２図は従来の配線金属形成方法の工程順を示
す断面図。
第３図と第４図は本発明の配線金属形成方法の工程順を
示す断面図である。
１・・・・・・素子となる拡散層を含むシリコン基板２
・・・・・・絶縁層
４・・・・・・コンタクトホール
５．８・・・・・・中間絶縁層
６．９・・・・・・第二層配線 よ 上山
願人 株式会社 第二稍工舎
代理人弁理士最上 務FIGS. 1 and 2 are cross-sectional views showing the process order of a conventional wiring metal forming method. FIGS. 3 and 4 are cross-sectional views showing the order of steps in the method for forming wiring metal according to the present invention. 1...Silicon substrate 2 including a diffusion layer that becomes an element
...Insulating layer 4...Contact hole 5.8...Intermediate insulating layer 6.9...Second layer wiring Yato Kamiyama Dai-ni Co., Ltd. Tsutomu Mogami, Patent Attorney, Hankosha
Claims (1)
形成しｆｃ後、急速熱処理全行な９ことによジ前記配線
金属の断面形状を傾斜化させることを特徴とす弓る半導
体装置の配線金属の形成方法。Dry etching the wiring metal pattern [, J: Tute -
9. A method for forming a wiring metal of a curved semiconductor device, characterized in that after forming and fc, a rapid heat treatment is performed to make the cross-sectional shape of the wiring metal slope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2230683A JPS59148347A (en) | 1983-02-14 | 1983-02-14 | Method for forming wiring metal for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2230683A JPS59148347A (en) | 1983-02-14 | 1983-02-14 | Method for forming wiring metal for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59148347A true JPS59148347A (en) | 1984-08-25 |
Family
ID=12079053
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2230683A Pending JPS59148347A (en) | 1983-02-14 | 1983-02-14 | Method for forming wiring metal for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59148347A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6233483A (en) * | 1985-08-07 | 1987-02-13 | Agency Of Ind Science & Technol | Superconductive integrated circuit |
| JPS6236846A (en) * | 1985-06-24 | 1987-02-17 | アメリカ合衆国 | Flattening of metal layer |
| JPH02104647A (en) * | 1988-10-12 | 1990-04-17 | Univ Waseda | Heat treatment for ni-p alloy film |
-
1983
- 1983-02-14 JP JP2230683A patent/JPS59148347A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6236846A (en) * | 1985-06-24 | 1987-02-17 | アメリカ合衆国 | Flattening of metal layer |
| JPS6233483A (en) * | 1985-08-07 | 1987-02-13 | Agency Of Ind Science & Technol | Superconductive integrated circuit |
| JPH02104647A (en) * | 1988-10-12 | 1990-04-17 | Univ Waseda | Heat treatment for ni-p alloy film |
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