JPS60160667A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60160667A JPS60160667A JP1510584A JP1510584A JPS60160667A JP S60160667 A JPS60160667 A JP S60160667A JP 1510584 A JP1510584 A JP 1510584A JP 1510584 A JP1510584 A JP 1510584A JP S60160667 A JPS60160667 A JP S60160667A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- silicon substrate
- thin
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000001301 oxygen Substances 0.000 claims abstract description 15
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 15
- 239000003870 refractory metal Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000002597 Solanum melongena Nutrition 0.000 description 1
- 244000061458 Solanum melongena Species 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高集積化、高速化さちたＭＯ８Ｏ８形量積回路
いて好適な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device suitable for highly integrated and high-speed MO8O8 type mass integrated circuits.
近年、ＭＯＳ形の集積回路で高集積化や高速化が進めら
れているが、これにともなってゲート酸化膜（Ｓｔｏｗ
膜）の厚さが薄くなる傾向にある。例えばメガビット級
のＭＯＳメモリ素子では、１Ｍビットで上２００Ａ程度
、これよりさらに高ビットでは１００Ａ程度にまで薄く
なる。In recent years, MOS-type integrated circuits have become more highly integrated and faster.
There is a tendency for the thickness of the film to become thinner. For example, in a megabit class MOS memory element, the thickness is about 200A for 1Mbit, and about 100A for higher bits.
また、高速にするためにはゲート電極材料の低抵抗化が
進められ、これに適した高温度耐性をもつりフラクトリ
ーメタルの薄膜の高純度化形成技術もますます進められ
ている。Furthermore, in order to achieve higher speeds, the resistance of gate electrode materials has been reduced, and technology for forming high-purity thin films of factory metals with high temperature resistance suitable for this purpose is also progressing.
しかしながら、膜厚１００Ａ程度の８１０．膜の厚さを
制御する際、酸素分圧が十分にコントロールされた雰囲
気中では比較的低温でシリコン基板上に膜を形成するの
が可能であるが、これを室温中に取り出して放置すると
、例えば２４時間で膜厚が１０〜２０チ増加し、膜厚制
御がで睡なくなってしまう。However, the film thickness of 810. When controlling the thickness of a film, it is possible to form a film on a silicon substrate at a relatively low temperature in an atmosphere where the oxygen partial pressure is sufficiently controlled, but if the film is taken out and left at room temperature, For example, the film thickness increases by 10 to 20 inches in 24 hours, making it difficult to control the film thickness.
また、ゲート電極を構成するりフラクトリーメタル薄膜
は、高真空中で蒸着によって、または低真空中でスパッ
タリングによって基板上に形成されるが、このために雰
囲気中の酸素や窒素等のガスが膜に含まれてしまう。In addition, the factory metal thin film that constitutes the gate electrode is formed on the substrate by vapor deposition in a high vacuum or by sputtering in a low vacuum. It will be included in
これは高真空中でスパッタリングした場合も同′様であ
る。このようにゲート電極中にガス、特に酸素が存在す
ると、その抵抗値に大きな影響を与えるという問題があ
る。The same is true when sputtering is performed in a high vacuum. As described above, there is a problem in that the presence of gas, especially oxygen, in the gate electrode greatly affects its resistance value.
本発明は従来のこのような点を解決するためになされた
もので、その目的とするところは、薄いゲート酸化膜と
低抵抗のゲート電極が得られるような半導体装置の製造
方法を提供することにある。The present invention has been made to solve these conventional problems, and its purpose is to provide a method for manufacturing a semiconductor device that allows a thin gate oxide film and a low-resistance gate electrode to be obtained. It is in.
本発明はこのような目的を達成するために、シリコン基
板上にり７ラクトリーメタルの薄膜を形成し、非酸化性
雰囲気中で加熱して薄膜をアニールし、薄膜中の酸素を
シリコン基板と反応させて薄膜直下に５ｉｎｌｌ膜を形
成するようにしたものである。In order to achieve such an object, the present invention forms a thin film of 7 Lactoly metal on a silicon substrate, heats it in a non-oxidizing atmosphere to anneal the thin film, and removes the oxygen in the thin film from the silicon substrate. The reaction was carried out to form a 5 inch film directly under the thin film.
また、シリコン基板上に薄いポリシリコンを形成してお
き、ポリシリコンと上記薄膜中の酸素との反応によりｓ
ｈｏ、膜を形成するようにしたものである。In addition, thin polysilicon is formed on a silicon substrate, and s
ho, it is designed to form a film.
一般に、モリブデン、タングステン等のり７ラクトリー
メタル中に酸素が導入されると、これらのメタルの酸化
物が形成されるが、そこに高温中でシリコンが存在する
と、リフラクトリ−メタルは還元されてもとのメタルに
戻る。この反応は例えばモリブデンの場合、次のような
反応式になる。Generally, when oxygen is introduced into refractory metals such as molybdenum and tungsten, oxides of these metals are formed, but if silicon is present at high temperatures, the refractory metals are reduced even though they are reduced. Back to metal with. For example, in the case of molybdenum, this reaction has the following reaction formula.
２Ｍ、ＯＢ＋３Ｊ ＝ ２Ｍ０＋３８ＩＯ。2M, OB+3J = 2M0+38IO.
従って、シリコン基板上にモリブデンをスパッタリング
して薄膜を形成し、これを高温中で処理すると、モリブ
デン薄膜中に吸蔵されていた酸素が基板上まで拡散し、
上記のような反応が起こってきわめて薄いＳｉｎ、膜が
薄膜直下に形成され、同時にモリブデン薄膜中の酸素吸
蔵率が減少して次に、第１図（ａ）〜（Ｃ）を用いて、
本発明の一実施例であるＭＯＳ ＦＥＴの製造方法につ
いて説明する。Therefore, when molybdenum is sputtered to form a thin film on a silicon substrate and this is treated at high temperature, the oxygen occluded in the molybdenum thin film diffuses onto the substrate.
As the above reaction occurs, an extremely thin film of Sin is formed directly below the thin film, and at the same time the oxygen storage rate in the thin molybdenum film decreases.
A method for manufacturing a MOS FET, which is an embodiment of the present invention, will be described.
先づ、Ｐ形シリコン基板１上にリフラクトリ−メタルを
全面に形成した後、ホトリソグラフィ技術を用いてパタ
ーニングを行なってゲート電極２を形成する（第１図（
ａ））。First, a refractory metal is formed on the entire surface of a P-type silicon substrate 1, and then patterned using photolithography to form a gate electrode 2 (see FIG. 1).
a)).
次に、非酸化性雰囲気中（例えば窒素、アルゴンガス中
、温度１０００程度）で加熱アニールすると、ゲート電
極２中の酸素がシリコン基板１の表面まで拡散してゲー
ト電極２の直下に８１０．膜３を形成する（第１図（ｂ
））。このＳｉｎ、膜３はリフラクトリ−メタル形成時
の雰囲気およびアニール温度２時間により制御すること
ができるが、非常に薄い膜厚が得られる。Next, when heat annealing is performed in a non-oxidizing atmosphere (for example, in nitrogen or argon gas at a temperature of about 1,000 ℃), oxygen in the gate electrode 2 diffuses to the surface of the silicon substrate 1 and forms an 810.degree. Form a film 3 (see Figure 1(b)
)). Although this Sin film 3 can be controlled by the atmosphere during refractory metal formation and the annealing temperature for 2 hours, a very thin film can be obtained.
次にゲート電極２をマスクにしてＮ形不純物を注入して
ソース、ドレインとなる虻領域４，５を形成する。Next, using the gate electrode 2 as a mask, N-type impurities are implanted to form dovetail regions 4 and 5 that will become the source and drain.
次に、他の実施例を第２図（、）〜（ｄ）を用いて説明
する。Next, another embodiment will be described using FIGS. 2(,) to (d).
先づ、Ｐ形シリコン基板１上に５０Ａ 程度の厚さにポ
リシリコンロを形成する（第２図（ａ））。First, a polysilicon film having a thickness of about 50 Å is formed on a P-type silicon substrate 1 (FIG. 2(a)).
次に、ポリシリコンロ上にリフラクトリ−メタルを形成
した後、パターニングしてゲート電極２を形成する（第
２図（ｂ））。Next, a refractory metal is formed on the polysilicon layer and then patterned to form a gate electrode 2 (FIG. 2(b)).
次に、非酸化性雰囲気中で加熱してゲート電極２中に吸
蔵している酸素によってポリシリコンロをＳｉｎ、膜３
となす（第２図（Ｃ））。Next, by heating in a non-oxidizing atmosphere, oxygen occluded in the gate electrode 2 converts the polysilicon layer into Sin, and the film 3
and eggplant (Figure 2 (C)).
次に、Ｎ形不純物を注入して虻領域４，５を形成する（
第２図（ｄ））。Next, N-type impurities are implanted to form fly regions 4 and 5 (
Figure 2(d)).
また、第３図（、）〜（Ｃ）に示すように、第２図（ｂ
）のポリシリコンロ上にゲート電極２を形成した後、ゲ
ート電極２をマスクにしてポリシリコンロをエツチング
除去しく第３図（ａ））、Ｌかる後、非酸化性雰囲気中
で加熱してゲート′ｌ！極２の直下に残ったポリシリコ
ンロを酸化して５ＩＯ１ｌ膜３を形成しく第３図（ｂ）
） 、次いでＮ形不純物を注入して虻領域４，５を形
成することもできる。In addition, as shown in Figures 3(,) to (C), Figure 2(b)
After forming the gate electrode 2 on the polysilicon layer shown in FIG. 3(a), the polysilicon layer is etched away using the gate electrode 2 as a mask. Gate'l! The polysilicon layer remaining directly under the electrode 2 is oxidized to form a 5IO1L film 3. FIG. 3(b)
), then N-type impurities may be implanted to form the dovetail regions 4 and 5.
このように本発明に係る半導体装置の製造方法によると
、薄いゲー） Ｓｉｎ、膜が容易に得られ、しかもリフ
ラクトリ−メタル中に吸蔵してい曳酸素を利用してＪｏ
ｇ膜を作るためにゲート電極中の酸素を減少でき低抵抗
化がはかれるという優れた効果がある。As described above, according to the method of manufacturing a semiconductor device according to the present invention, a thin film of silicon (Si) can be easily obtained, and moreover, it is possible to obtain a thin silicon film using the drawn oxygen occluded in the refractory metal.
This has the excellent effect of reducing the amount of oxygen in the gate electrode to form a g film, resulting in lower resistance.
第１図（、）〜（ｃ）は本発明に係る半導体装置の製造
方法の一実施例における各工程の断面図、第２図（−）
〜（ｄ）は他の実施例における各工程の断面図、第３図
（、）〜（ｅ）は他の実施例における各工程の断面図で
ある。
１・・・・シリコン基板、２・・・・ゲート電極、３
・−−−ＳＩＯ，膜、４，５日・・Ｎ＋領領域６・・・
・ポリシリコン。
第１図 第２図Figures 1 (,) to (c) are cross-sectional views of each step in an embodiment of the method for manufacturing a semiconductor device according to the present invention, and Figure 2 (-)
-(d) are sectional views of each process in another embodiment, and FIGS. 3(a) to 3(e) are sectional views of each process in another embodiment. 1...Silicon substrate, 2...Gate electrode, 3
・---SIO, membrane, 4th and 5th days...N+ area 6...
・Polysilicon. Figure 1 Figure 2
Claims (1)
薄い膜を形成し、非酸化性雰囲気中で加熱して膜中の酸
素をシリコン基板のシリコンと反応させ、膜の直下ＫＳ
ｌＯ，膜を形成することを特徴とする半導体装置の製造
方法。 ２、 シリコン基板上にポリシリコン薄膜を形成し、こ
のポリシリコン薄膜の上にリフラクトリ−メタルからな
る薄い膜を形成し、非酸化性雰囲気中で加熱して膜中の
酸素をポリシリコン薄膜のシリコンと反応きせ、膜の直
下にＳｉｎ、膜を形成することを特徴とする半導体装置
の製造方法。[Claims] 1. A thin film made of refractory metal is formed on a silicon substrate, heated in a non-oxidizing atmosphere to cause oxygen in the film to react with silicon on the silicon substrate, and the KS directly below the film is heated.
1. A method for manufacturing a semiconductor device, the method comprising forming a 1O2 film. 2. Form a polysilicon thin film on a silicon substrate, form a thin film made of refractory metal on top of this polysilicon thin film, and heat it in a non-oxidizing atmosphere to remove oxygen in the film from the silicon of the polysilicon thin film. A method for manufacturing a semiconductor device, characterized in that a film of Sin is formed directly under the film by reacting with the film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1510584A JPS60160667A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1510584A JPS60160667A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60160667A true JPS60160667A (en) | 1985-08-22 |
Family
ID=11879554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1510584A Pending JPS60160667A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160667A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593229B1 (en) | 1999-06-04 | 2003-07-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for manufacturing the same |
-
1984
- 1984-02-01 JP JP1510584A patent/JPS60160667A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593229B1 (en) | 1999-06-04 | 2003-07-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method for manufacturing the same |
| US6737341B1 (en) | 1999-06-04 | 2004-05-18 | Renesas Technology Corporation | Semiconductor integrated circuit device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4505028A (en) | Method of producing semiconductor device | |
| JP2615390B2 (en) | Method of manufacturing silicon carbide field effect transistor | |
| JPH03227516A (en) | Manufacture of semiconductor device | |
| JPS60160667A (en) | Manufacture of semiconductor device | |
| JPH11289087A (en) | Semiconductor device and its manufacture | |
| JPS59200418A (en) | Manufacture of semiconductor device | |
| JPS63119268A (en) | Manufacture of semiconductor device | |
| JP3261444B2 (en) | Manufacturing method of semiconductor thin film | |
| JPH04266031A (en) | Manufacture of semiconductor device | |
| JPS61135156A (en) | Semiconductor device and manufacture thereof | |
| JPH01276616A (en) | Manufacture of semiconductor device | |
| JPS62104078A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2857170B2 (en) | Method for manufacturing semiconductor device | |
| JPH04155967A (en) | Manufacture of semiconductor device | |
| JPH02181918A (en) | Manufacture of semiconductor device | |
| JPH02114641A (en) | Manufacture of semiconductor device | |
| JPS6138264B2 (en) | ||
| JP2650972B2 (en) | Method for manufacturing semiconductor device | |
| JPH09293722A (en) | Manufacture of semiconductor device | |
| JPH01289165A (en) | Manufacture of semiconductor device | |
| JPS63283064A (en) | Formation of polycide pattern | |
| JPH0349230A (en) | Semiconductor device and manufacture thereof | |
| JPS5846651A (en) | Structure of electrode wiring and its manufacture | |
| JPS58162062A (en) | Manufacture of semiconductor device | |
| JPH0738103A (en) | Semiconductor device and manufacture thereof |