JPS6014522A - Generator for clock signal synchronized with digital signal - Google Patents
Generator for clock signal synchronized with digital signalInfo
- Publication number
- JPS6014522A JPS6014522A JP58122603A JP12260383A JPS6014522A JP S6014522 A JPS6014522 A JP S6014522A JP 58122603 A JP58122603 A JP 58122603A JP 12260383 A JP12260383 A JP 12260383A JP S6014522 A JPS6014522 A JP S6014522A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency
- clock signal
- circuit
- synchronized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 19
- 230000010355 oscillation Effects 0.000 claims description 12
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- ZYXYTGQFPZEUFX-UHFFFAOYSA-N benzpyrimoxan Chemical compound O1C(OCCC1)C=1C(=NC=NC=1)OCC1=CC=C(C=C1)C(F)(F)F ZYXYTGQFPZEUFX-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、再生デジタルオーディオ信号などの、デジ
タル信号からこれと同期したクロック信号を得るクロッ
ク信号発生装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock signal generation device that obtains a clock signal synchronized with a digital signal, such as a reproduced digital audio signal.
この種のクロック信号発生装置として、第１図に示す位
相同期回路が一般に使用されてきた。即ち図において（
１）は位相比較回路、（２）は電圧制御発振器のような
可変周波数発振回路で１位相比較回路＋１１において、
この回路へのビット周波数ｆｂのデジタル入力信号Ａと
、可変周波数発振回路（２）の出力クロック信号Ｃとの
位相差を検出し、その位相差に応じた信号Ｂで可変周波
数発振回路（２１の出力周波数１位相を制御し、入力デ
ジタル信号Ａと同期したクロック信号を得ていた。この
第１図に示された装置は第２図に示すような動作特性な
有秒を変化させた場合の位相差信号Ｂの変化を示したも
ので、ｆｌ）が充分低いところから徐々に高くしていく
と当初はクロック信号Ｃはデジタル信号Ａと同期せずに
発振中心周波数ｆｏ なるクロック信号となっている。As this type of clock signal generator, a phase synchronized circuit shown in FIG. 1 has generally been used. That is, in the figure (
1) is a phase comparison circuit, (2) is a variable frequency oscillation circuit such as a voltage controlled oscillator, and in 1 phase comparison circuit +11,
The phase difference between the digital input signal A of bit frequency fb to this circuit and the output clock signal C of the variable frequency oscillation circuit (2) is detected, and the signal B corresponding to the phase difference is used to input the variable frequency oscillation circuit (21). By controlling one phase of the output frequency, a clock signal synchronized with the input digital signal A was obtained. This shows the change in the phase difference signal B. When fl) is gradually raised from a sufficiently low level, the clock signal C initially becomes a clock signal with an oscillation center frequency fo without synchronizing with the digital signal A. There is.
ｈ２ においてクロック信号はデジタル信号Ａと同期す
る。即ちクロック信号Ｃの周波数ｆｃ はｆｂと同一と
なる。ｂ４ においてクロック信号０とデジタル信号Ａ
との同期は外れ。At h2, the clock signal is synchronized with digital signal A. That is, the frequency fc of the clock signal C is the same as fb. At b4, clock signal 0 and digital signal A
Out of sync with.
ｆｃ−ｆｏとなる。逆にｆｌ）が充分高いところから下
降していくと、ｂ３ において両信号は同期し。It becomes fc-fo. Conversely, when fl) starts to fall from a sufficiently high point, both signals become synchronized at b3.
ｂｌ にて同期が外れる。Synchronization is lost at bl.
以上の位相同期回路をデジタル信号のクロック信号発生
装置として使用した場合１次のようないくつかの問題点
があった。第１に入力信号がデジタル信号であるため、
デジタル信号の反転数がビット周波数ｆｂ、クロック周
波数ｆｃ より相当少ない（デジタル信号が１０１０１
０・・・とビット毎に反転する場合が最高でｆｂ）ため
、入力デジタル信号中に含まれるクロック信号と位相比
較される情報が少ない。そのために可変周波数発振回路
として充分安定度の高いものを使用しないと誤制御を生
じたり同期外れを起重頻度が大となる一第２に可変周波
数発振回路が温度変化等によって特性変化を生ずると、
第２図に示した特性も左右にずれ。When the above-mentioned phase synchronization circuit is used as a clock signal generator for digital signals, there are several problems of the first order. First, since the input signal is a digital signal,
The number of inversions of the digital signal is considerably smaller than the bit frequency fb and clock frequency fc (the digital signal is 10101
0 . . . is inverted bit by bit at most (fb), so there is little information to be phase-compared with the clock signal contained in the input digital signal. Therefore, unless a variable frequency oscillator circuit with sufficiently high stability is used, erroneous control will occur and synchronization will occur more frequently.Secondly, if the variable frequency oscillator circuit changes in characteristics due to temperature changes, etc. ,
The characteristics shown in Figure 2 also shift left and right.
ある温度では同期が得られたデジタル信号Ａに対しても
、温度が変化すると同期が得られない場合もある。第３
に、上記のように入力デジタル信号の反転数が少なくて
も同期外れが生せず温度変（１ｊに対しても特性の変化
のない安定度の高い可変周波数発振回路では、第２図に
示した同期化可能な周波数範囲、即ちキャプチャー・レ
ンジ（ＣａｐｔｕｒｅＲａｎｇｅ ）が広くとれず、こ
れを広くとるよう設計すれば、安定度の高い回路は得ら
れない、といった欠点を有していた。Even if the digital signal A is synchronized at a certain temperature, synchronization may not be achieved when the temperature changes. Third
As mentioned above, even if the number of inversions of the input digital signal is small, synchronization does not occur and the characteristics do not change even with temperature changes (1j). However, the synchronizable frequency range, that is, the capture range, cannot be widened, and if designed to be wide, a highly stable circuit cannot be obtained.
この発明は１以上のような従来方式の欠点を除き、比較
的広いキャプチャー・レンジで、常に安定したクロック
信号を確実に得られるクロック信号発生装置を提供する
ものである。The present invention eliminates one or more of the drawbacks of the conventional system and provides a clock signal generation device that can always reliably obtain a stable clock signal over a relatively wide capture range.
以下第３図によってこの発明の詳細な説明する。図は、
この発明の１実施例を示すブロックダイヤグラムで、（
１）は第１図と同様に入力信号Ａとクロック信号Ｃとの
位相差信号りを得る第１の位相比較回路、（２）も第１
図と同様入力信号Ｂで出力クロック信号Ｃを得る可変周
波数発振回路、（３１は可変周波数発振回路（２）の出
力クロック信号Ｃを整数（Ｎ）分の１（１／Ｎ）に分周
する分周回路、（４）は安定した周波数ｆＦの基準クロ
ック信号Ｆを発生する基準信号発生回路で、入力信号ビ
ット周波数ｆｂごＮ−ｆＦなるようＮ及びｆ、が選ばれ
ている。The present invention will be explained in detail below with reference to FIG. The diagram is
A block diagram showing one embodiment of this invention (
1) is a first phase comparator circuit that obtains a phase difference signal between an input signal A and a clock signal C, as in FIG.
As shown in the figure, a variable frequency oscillation circuit obtains an output clock signal C using an input signal B. (31 is a frequency division of the output clock signal C of the variable frequency oscillation circuit (2) by an integer (N) (1/N). The frequency dividing circuit (4) is a reference signal generating circuit that generates a reference clock signal F with a stable frequency fF, and N and f are selected so that the input signal bit frequency fb is equal to N-fF.
（５）はこの基準信号発生回路（４）の出力基準クロッ
ク信号Ｆと分周回路（３）の出力信号Ｅとの位相差を検
出し、出力Ｇを得る第２の位相比較回路、（６）はクロ
ック信号Ｃがデジタル信号Ａに同期していない時に閉路
する開閉器、（７）は位相比較回路＋１１ ＋７１から
の位相差信号り、Ｇを可変周波数発振回路（２）の入力
に伝達する低域フィルタ回路で１種の積分回路を構成し
直流信号で最大のゲインを有している。(5) is a second phase comparator circuit that detects the phase difference between the output reference clock signal F of the reference signal generation circuit (4) and the output signal E of the frequency divider circuit (3) and obtains the output G; ) is a switch that closes when clock signal C is not synchronized with digital signal A, (7) is a phase difference signal from phase comparison circuit +11 +71, and transmits G to the input of variable frequency oscillation circuit (2). The low-pass filter circuit constitutes a type of integration circuit and has the maximum gain for DC signals.
次にその動作を説明する。クロック信号がデジタル信号
Ａと同期していない時は、第２図に示したように第１の
位相比較回路ｆｌｌはＯｖを出力し。Next, its operation will be explained. When the clock signal is not synchronized with the digital signal A, the first phase comparator circuit fll outputs Ov as shown in FIG.
開閉器（６）が開いていれば回路（２）の入力電圧Ｂは
成る一定の値となっている。この時同期が外れているこ
とを何等かの手段で検出して開閉器（６）を閉成丁れば
１分周回路（３：の出力分周クロック信号Ｅと基準クロ
ック信号Ｆとの位相比較が行なわねる。When the switch (6) is open, the input voltage B of the circuit (2) is a constant value. At this time, if the synchronization is detected by some means and the switch (6) is closed, the phase of the output frequency divided clock signal E of the frequency divider circuit (3:) and the reference clock signal F will be changed. Comparison cannot be made.
この時の信号Ｊ Ｐの周波数ｆｙ２．ｆＦはｆｘ＝ｆｃ
／Ｎ＊ ｆｐ： ｆｌｙ’ｎとなり、ｆｃとｆｂの周波
数差９位相差も１／Ｎとなることと、信号Ｆｉ、Ｆ共に
デジタル（Ｓ号と異なり毎半周期毎に反転するクロック
信号であるためｆｃとｆｂとが多少ずれていても同期化
は容易で。The frequency fy2 of the signal JP at this time. fF is fx=fc
/N* fp: fly'n, and the frequency difference 9 phase difference between fc and fb is also 1/N, and both the signals Fi and F are digital (unlike signal S, they are clock signals that are inverted every half cycle). Therefore, even if fc and fb are slightly different, synchronization is easy.
分周クロック信号Ｅは基準信号Ｐ・と同期する。従って
ｆＥ＝ ｆＦ＝ ｆｏ／Ｈ＝ ｆ １）／Ｎ 故に ｆ
ｃＺｆｂとなるので、開閉器（６１を開路丁れはクロッ
ク信号Ｃはデジタル信号Ａに容易に同期する。The divided clock signal E is synchronized with the reference signal P. Therefore, fE= fF= fo/H= f 1)/N Therefore, f
cZfb, the clock signal C is easily synchronized with the digital signal A when the switch 61 is opened.
以上のように、この発明ではｆｌ）が前もってわかって
いる場合に
Ｎ ＠ｆＢ、ユｆｂ
となるよう整数Ｎ及び基準クロツノ１キ号周波数ｆ１ｒ
を選定し、基準クロック信号Ｆと分周クロック信号Ｅと
の位相差信号Ｇを可変周波数発振回路に印加して同期を
とり、その後クロック信号Ｃをデジタル入力信号Ａに同
期させようとするものである５上記フィルタ回路（７）
は２位相同期ループのループゲインを上げてキャプチャ
ー・レンジを広くするために設けられたもので、入力信
号に重量しているノイズ迄増幅されると不安定となるの
で直流信号で最大ゲインの低域フィルタ特性を持たせて
いる。しかし、この発明では必しもこのような回路に限
られることはない。As described above, in this invention, when fl) is known in advance, the integer N and the reference black horn 1 key frequency f1r are
is selected, a phase difference signal G between a reference clock signal F and a frequency-divided clock signal E is applied to the variable frequency oscillation circuit to achieve synchronization, and then the clock signal C is synchronized with the digital input signal A. There are 5 above filter circuits (7)
is provided to increase the loop gain of the two-phase locked loop and widen the capture range.If the input signal is amplified to the level of noise, it will become unstable, so it is necessary to use a DC signal with a low maximum gain. It has band filter characteristics. However, the present invention is not necessarily limited to such a circuit.
なお、上記開閉器（６）として第２の位相比較回路（５
１とフィルタ回路（７）との間にのみ設けたが、第１の
位相比較回路（５）とフィルタ回路（７）との間にも接
点を設け、開閉器（６）の接点と相補的に開閉させるよ
うにしてもよい。又１位相比較回路として１個のみ使用
し、入力デジタル信号Ａと基準クロック信号Ｆ、クロッ
ク信号Ｃと分周クロック信号Ｅとを同時に切替え制御し
て、第１及び第２の位相比較回路を兼用してもよい。In addition, the second phase comparator circuit (5) is used as the switch (6).
Although a contact point is provided only between the first phase comparison circuit (5) and the filter circuit (7), a contact point is also provided between the first phase comparison circuit (5) and the filter circuit (7), and a contact point is provided complementary to the contact point of the switch (6). It may also be configured to open and close. In addition, only one phase comparison circuit is used, and the input digital signal A, the reference clock signal F, the clock signal C, and the frequency-divided clock signal E are switched and controlled at the same time, and the circuit is also used as the first and second phase comparison circuits. You may.
上記開閉器（６）は、入力デジタル信号Ａとクロック信
号Ｃとの同期状態を適宜検出して制御てれはよいが、入
力デジタル信号中に、複数ビットの固定パターンによる
同期信号が含まれている場合。The switch (6) can be controlled by appropriately detecting the synchronization state of the input digital signal A and the clock signal C, but the input digital signal contains a synchronization signal with a fixed pattern of multiple bits. If there is.
この信号を検出する別の信号処理回路ｌこよってこの信
号が検出されているかどうかによって、信号ＡとＣが同
期しているかどうかを判断して開閉器（６）を制御する
ようにしてもよい。Another signal processing circuit that detects this signal may be used to control the switch (6) by determining whether the signals A and C are synchronized depending on whether or not this signal is detected. .
以上の装置は、テープ又はディスク等の記録媒体に記録
されたデジタル信号を再生１石場合のクロック信号発生
に使用し得るが、この時のテープの走行制御、又はディ
スクの回転制御に上記第２の位相比較回路出力信号Ｇが
利用できる。The above device can be used to generate a clock signal when reproducing a digital signal recorded on a recording medium such as a tape or a disk. The phase comparison circuit output signal G can be used.
以上のようにこの発明によれは１分周回路の分周比Ｎを
適宜選定することにより可成り広Ｇ叱ット周波数範囲に
わたる入力デジタル信号に対し確実に安定したクロック
信号を発生し得る装置を提供できるという１−ぐれた効
果を有している。As described above, the present invention provides a device that can reliably generate a stable clock signal for input digital signals over a fairly wide frequency range by appropriately selecting the frequency division ratio N of the frequency divider circuit. It has the outstanding effect of being able to provide the following.
第１図は従来のクロック信号発生装俯を示すブロックダ
イヤグラム、第２図は、その動作説明図。
第３図はこの発明の１笑施例を示すブロックダイヤクラ
ムである、
図中、（１）は第１の位相比較回路、（２）は司変周波
数発振回路、（３１は分周回路、（４１は基準信号発生
回路、（５）は第２の位相比較回路、（６）は開閉器、
（７）は低域フィルタ回路である。
代理人 大 岩 増 雄（ほか２名）
−１四
第響図
第３図FIG. 1 is a block diagram showing a conventional clock signal generation device, and FIG. 2 is an explanatory diagram of its operation. FIG. 3 is a block diagram showing one embodiment of the present invention. In the figure, (1) is a first phase comparator circuit, (2) is a variable frequency oscillation circuit, (31 is a frequency dividing circuit, (41 is a reference signal generation circuit, (5) is a second phase comparison circuit, (6) is a switch,
(7) is a low-pass filter circuit. Agent Masuo Oiwa (and 2 others) -14th Symphony Orchestra Figure 3
Claims (1)
振回路の出力クロック信号との位相差を検出し、この位
相差に応じた信号を上記可変周波数発振回路に入力し、
その出力クロック信号周波数を制御するようにしたデジ
タル信号に同期したクロック信号発生装置において、上
記可変周波数発振回路の出力クロック信号周波数を整数
（Ｎ）分の１（１／Ｎ）に分周する分周回路、上記入力
デジタル信号のビット周波数ｆｂの上記整数分の１（１
／Ｎ）に近い周波数ｆＦの基準周波数信号発生回路、及
びこれら両回踏出力信号の位相差を検出する第２の位相
比較回路を設け、この回路の出力信号を。 上記可変周波数信号発生回路に周波数制御用信号として
選択的に印加するようにしたことを特徴とするデジタル
信号に同期したクロック信号発生装置。[Claims] Detecting a phase difference between an input digital signal of bit frequency fb and an output clock signal of a variable frequency oscillation circuit, and inputting a signal corresponding to this phase difference to the variable frequency oscillation circuit,
In a clock signal generation device synchronized with a digital signal that controls the output clock signal frequency, the output clock signal frequency of the variable frequency oscillation circuit is divided into an integer (N) (1/N). circuit, 1/(1) of the above integer of the bit frequency fb of the above input digital signal
A reference frequency signal generation circuit with a frequency fF close to /N) and a second phase comparison circuit for detecting the phase difference between these two rotational output signals are provided, and the output signal of this circuit is. A clock signal generating device synchronized with a digital signal, characterized in that a frequency control signal is selectively applied to the variable frequency signal generating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58122603A JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58122603A JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6014522A true JPS6014522A (en) | 1985-01-25 |
Family
ID=14840023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58122603A Pending JPS6014522A (en) | 1983-07-06 | 1983-07-06 | Generator for clock signal synchronized with digital signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6014522A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239623A (en) * | 1988-07-28 | 1990-02-08 | Nec Corp | Pll circuit |
| JPH02127817A (en) * | 1988-11-07 | 1990-05-16 | Nec Corp | Phase locked loop oscillator |
| JPH0440117A (en) * | 1990-06-06 | 1992-02-10 | Fujitsu Ltd | Pll circuit |
| US5097219A (en) * | 1988-12-15 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Pll for controlling frequency deviation of a variable frequency oscillator |
| JPH05129942A (en) * | 1991-11-08 | 1993-05-25 | Matsushita Electric Ind Co Ltd | Pll circuit |
| US5384291A (en) * | 1993-06-25 | 1995-01-24 | The Dow Chemical Company | Carbothermal synthesis precursors |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57106241A (en) * | 1980-10-31 | 1982-07-02 | Westinghouse Electric Corp | Phase lock loop |
-
1983
- 1983-07-06 JP JP58122603A patent/JPS6014522A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57106241A (en) * | 1980-10-31 | 1982-07-02 | Westinghouse Electric Corp | Phase lock loop |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239623A (en) * | 1988-07-28 | 1990-02-08 | Nec Corp | Pll circuit |
| JPH02127817A (en) * | 1988-11-07 | 1990-05-16 | Nec Corp | Phase locked loop oscillator |
| US5097219A (en) * | 1988-12-15 | 1992-03-17 | Mitsubishi Denki Kabushiki Kaisha | Pll for controlling frequency deviation of a variable frequency oscillator |
| JPH0440117A (en) * | 1990-06-06 | 1992-02-10 | Fujitsu Ltd | Pll circuit |
| JPH05129942A (en) * | 1991-11-08 | 1993-05-25 | Matsushita Electric Ind Co Ltd | Pll circuit |
| US5384291A (en) * | 1993-06-25 | 1995-01-24 | The Dow Chemical Company | Carbothermal synthesis precursors |
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