JPH01198828A - Phase locked loop circuit - Google Patents
Phase locked loop circuitInfo
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- JPH01198828A JPH01198828A JP63023224A JP2322488A JPH01198828A JP H01198828 A JPH01198828 A JP H01198828A JP 63023224 A JP63023224 A JP 63023224A JP 2322488 A JP2322488 A JP 2322488A JP H01198828 A JPH01198828 A JP H01198828A
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- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000001360 synchronised effect Effects 0.000 claims description 11
- 230000010355 oscillation Effects 0.000 claims description 5
- 230000001052 transient effect Effects 0.000 abstract description 9
- 230000035945 sensitivity Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 241000283986 Lepus Species 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
〔概要〕
例えば、°データに同期したクロックを抽出する際など
に使用するフェーズロックドループ回路に関し、
ループの帯域幅を切り替える際に過渡現象が生じない様
にすることを目的とし、
同期検出手段よりの切替信号の状態に対応して入力信号
をｎ分周して出力し、又は直接出力する第１の分周手段
と、該同期検出手段よりの切替信号の状態に対応して電
圧制御発振器の出力をｎ分周して出力し、又は直接出力
する第２の分周手段と、該第１及び第２の分周手段の出
力が同期状態に入ったことを検出した時に異なる状態の
切替信号を送出する同期検出手段と、該第２の分周手段
の出力を用いて該第１０分周手段の出力を位相検波する
位相検波器と、該位相検波器の出力から位相差信号を抽
出するループフィルタと、該ループフィルタの出力によ
って該第１及び第２の分周手段の出力が同期する様に発
振周波数が制御される該電圧制御発振器とを有する様に
構成する。[Detailed Description of the Invention] [Summary] For example, regarding a phase-locked loop circuit used when extracting a clock synchronized with data, the present invention aims to prevent transient phenomena from occurring when switching the loop bandwidth. A first frequency dividing means that divides the input signal by n and outputs the frequency divided by n in response to the state of the switching signal from the synchronization detection means, or outputs the frequency directly, and Detecting that a second frequency dividing means correspondingly divides the output of the voltage controlled oscillator by n and outputs it or outputs it directly, and the outputs of the first and second frequency dividing means enter a synchronized state. synchronization detection means for sending out switching signals in different states when the second frequency division means is applied; a phase detector for phase detecting the output of the tenth frequency division means using the output of the second frequency division means; and an output of the phase detector. and a voltage controlled oscillator whose oscillation frequency is controlled so that the outputs of the first and second frequency dividing means are synchronized by the output of the loop filter. do.
本発明は９例えばデータに同期したクロックを抽出する
際などに使用するフェーズロックドループ回路に関する
ものである。The present invention relates to a phase-locked loop circuit used, for example, when extracting a clock synchronized with data.
フェーズロックドループ回路は電圧制御発振器の出力の
位相を基準入力信号の位相に同期させるためのもので、
位相が一致するのみならず９周波数も完全に一致するた
めにクロック抽出、搬送波再生９周波数シンセサイザな
どに広（使用されているが、この回路としては同期が取
れるまでの時間が短く、同期後は純度の高い同期出力を
送出しなければならない。A phase-locked loop circuit is used to synchronize the phase of the output of a voltage controlled oscillator with the phase of the reference input signal.
Not only do the phases match, but the 9 frequencies also completely match, so it is widely used in clock extraction, carrier wave regeneration, 9-frequency synthesizers, etc. (although this circuit takes a short time to synchronize, and after synchronization Highly pure synchronous output must be sent out.
この為、同期が取れた時にフェーズロックドループのパ
ラメータの切り替えを行っているが、この切り替えの際
に過渡現象が生じない様にすることが必要である。For this reason, the parameters of the phase-locked loop are switched when synchronization is achieved, but it is necessary to prevent transient phenomena from occurring during this switching.
第４図は従来例のブロック図を示す。以下、抵抗Ｒ４の
抵抗値の方が抵抗Ｒ２の抵抗値よりも高いとして図の動
作を説明する。FIG. 4 shows a block diagram of a conventional example. The operation of the diagram will be described below assuming that the resistance value of the resistor R4 is higher than the resistance value of the resistor R2.
例えば、雑音に埋もれたクロックが位相検波器（以下、
ＰＤと省略する）１１に入力するが、ここには上記の
クロックと非同期状態にある電圧制御発振器（以下、
ＶＣＯと省略する）１３の出力が印加されているので、
上記のクロックはｖＣＯの出力で位相検波されて検波出
力が得られる。For example, if a clock buried in noise is detected by a phase detector (hereinafter referred to as
(abbreviated as PD) 11, where a voltage controlled oscillator (hereinafter referred to as
Since the output of 13 (abbreviated as VCO) is applied,
The phase of the above clock is detected by the output of the vCO to obtain a detected output.
この検波出力は抵抗Ｒ，，Ｒ，、Ｒ３，Ｃ及び演算増幅
器１４．抵抗Ｒ１で構成されたループフィルタを通って
位相差信号が抽出され、制御信号としてＶＣＯ１３に加
えられる。そこで、ＶＣＯ１３の出力が入力クロックに
対して１例えば１８０°ずれる様に発振周波数が制御さ
れる。This detection output is generated by the resistors R, , R, , R3, C and the operational amplifier 14. A phase difference signal is extracted through a loop filter made up of a resistor R1 and is applied to the VCO 13 as a control signal. Therefore, the oscillation frequency is controlled so that the output of the VCO 13 is shifted by 1, for example, 180 degrees with respect to the input clock.
ここで、同期検出器１２は入力クロックとＶＣＯの出力
の位相差が１８０°あることを検出した時に同期状態と
判定して、切替信号をスイッチ１５に送出してＲ４から
Ｒ３に切り替えて演算増幅器１４の利得を下げ、フェー
ズロックドループ回路（以下、 ＰＬＬと省略する）の
ループ帯域幅を上記よりも狭くする。Here, when the synchronization detector 12 detects that there is a phase difference of 180 degrees between the input clock and the output of the VCO, it determines that the synchronization state is established, and sends a switching signal to the switch 15 to switch from R4 to R3 and switch the operational amplifier. 14, and the loop bandwidth of the phase-locked loop circuit (hereinafter abbreviated as PLL) is made narrower than above.
そこで、ＶＣＯ１３からジッタの少ない出力、即ち再生
クロックが送出される。Therefore, the VCO 13 sends out an output with less jitter, that is, a reproduced clock.
さて、ＰＬＬの引き込み時間Ｔ、とＰＬＬの帯域幅ＢＬ
との関係は、 １９７９年にＪｏｈｎ Ｗｉｌｅｙ ＆
Ｓｏｎ社より発行されたＦｌｏｙｄ Ｍ、 Ｇａｒｄ
ｎｅｒ 、Ｐｈ、 Ｄ著書のｒｌ’ｈａｓｅ Ｌｏｃｋ
Ｔｅｃｈｎｉｑｕｅｓ Ｊ ７６頁の５・１１式（下
記の（１）式）に示されている。即ち、但し、ＢＬはＰ
ＬＬの帯域幅を示すが、これは同書の１５頁及び３１頁
のＥｘａｍｐｌｅｓ及びＴａｂｌｅ ３．１に示す様に
９例えばｖＣＯの変調感度に０が高くなれば広がり、低
くなれば狭くなる。又、Δｆは中心周波数からのオフセ
ット周波数を示す。Now, the PLL pull-in time T and the PLL bandwidth BL
The relationship with John Wiley &
Floyd M, Gard, published by Son.
rl'hase Lock written by ner, Ph, D
Techniques J, page 76, formula 5.11 (formula (1) below). That is, however, BL is P
The bandwidth of LL is shown, and as shown in Examples and Table 3.1 on pages 15 and 31 of the same book, for example, the higher the modulation sensitivity of vCO, the wider it becomes, and the lower it becomes, the narrower it becomes. Further, Δf indicates an offset frequency from the center frequency.
即ち、上記の様にＰＬＬが引き込む迄、即ち同期が取れ
る迄はＢＬを広くしてＴＰを短くする為。That is, as described above, until the PLL is pulled in, that is, until synchronization is achieved, BL is widened and TP is shortened.
スイッチ１５で抵抗値の大きいＲ４を選択して演算増幅
器の利得（倍数）を大きくして、 ＶＣＯの変調感度に
０を利得倍だけ高くする。Select R4 with a large resistance value using switch 15 to increase the gain (multiple) of the operational amplifier, and increase the modulation sensitivity of the VCO by the gain times 0.
一方、同期が取れた後はＢＬを狭くして再生クロックの
ジッタをできるだけ少なくする為、スイッチ１５は抵抗
値の小さいＲｓを選択して演算増幅器の利得を下げてＶ
ＣＯの変調感度に。を前記よりも小さくする。On the other hand, after synchronization is achieved, in order to narrow the BL and minimize the jitter of the recovered clock, the switch 15 selects Rs, which has a small resistance value, and lowers the gain of the operational amplifier.
For CO modulation sensitivity. be smaller than the above.
即ち、同期が取れるまでは演算増幅器１４の抵抗はＲ４
に、同期が取れた時はスイッチ１５を用いてＲ３に切り
替えて利得を切り替えているが、切り替えの際にＰＬＬ
に第５図に示す様な過渡現象が生じて安定する迄に時間
がかかると云う問題点がある。That is, until synchronization is achieved, the resistance of the operational amplifier 14 is R4.
When synchronization is achieved, switch 15 is used to switch to R3 to change the gain, but when switching, the PLL
However, there is a problem in that a transient phenomenon as shown in FIG. 5 occurs and it takes time for it to stabilize.
この過渡現象の間再生クロックにジッタが乗るので１例
えば誤り率が劣化する可能性がある。During this transient phenomenon, jitter is added to the recovered clock, so that, for example, the error rate may deteriorate.
第１図は本発明の原理ブロック図を示す。 FIG. 1 shows a block diagram of the principle of the present invention.
図中、２は同期検出手段よりの切替信号の状態に対応し
て入力信号をｎ分周して出力し、又は直接出力する第１
の分周手段で、５は該同期検出手段よりの切替信号の状
態に対応して電圧制御発振器の出力をｎ分周して出力し
、又は直接出力する第２の分周手段であり、４は該第１
及び第２の分周手段の出力が同期状態に入ったことを検
出した時に異なる状態の切替信号を送出する同期検出手
段である。In the figure, 2 is a first circuit which divides the input signal by n and outputs it or directly outputs it, depending on the state of the switching signal from the synchronization detection means.
5 is a second frequency dividing means which divides the output of the voltage controlled oscillator by n and outputs the divided frequency or directly outputs the frequency divided by n in accordance with the state of the switching signal from the synchronization detection means; is the first
and a synchronization detection means that sends out a switching signal of a different state when it is detected that the output of the second frequency dividing means enters a synchronization state.
又、３は該第２の分周手段の出力を用いて該第１の分周
手段の出力を位相検波する位相検波器で、６は該位相検
波器の出力から位相差信号を抽出するループフィルタで
あり、１３は該ループフィルタの出力によって該第１及
び第２の分周手段の出力が同期する様に発振周波数が制
御される該電圧制御発振器である。Further, 3 is a phase detector that detects the phase of the output of the first frequency dividing means using the output of the second frequency dividing means, and 6 is a loop that extracts a phase difference signal from the output of the phase detector. 13 is the voltage controlled oscillator whose oscillation frequency is controlled so that the outputs of the first and second frequency dividing means are synchronized by the output of the loop filter.
一般に、位相検波器３．ループフィルタ６、電圧制御発
振器１３で構成されるＰＬＬの帯域幅は、該電圧制御発
振器の変調感度が高くなれば広がり。Generally, a phase detector 3. The bandwidth of the PLL composed of the loop filter 6 and the voltage controlled oscillator 13 increases as the modulation sensitivity of the voltage controlled oscillator increases.
低くなれば狭くなると云うことは広く知られている。It is widely known that the lower the area, the narrower it becomes.
本発明は、電圧制御発振器１３の出力が入力信号に同期
したことを同期検出手段４が検出した時、ループフィル
タ６の構成要素である演算増幅器の利得は切り替えずに
一定のままにして、第１の分周手段２及び第２の分周手
段５に切替信号を送出して、入力信号と電圧制御発振器
１３の出力とをそれぞれｎ分周したものを位相検波器３
に加える様にした。これにより、上記の変調感度は公知
の様に同期前の時よりも（１／ｎ）となってＰＬＬの帯
域幅は狭くなる。In the present invention, when the synchronization detection means 4 detects that the output of the voltage controlled oscillator 13 is synchronized with the input signal, the gain of the operational amplifier, which is a component of the loop filter 6, is not switched but remains constant. A switching signal is sent to the first frequency dividing means 2 and the second frequency dividing means 5, and the frequency of the input signal and the output of the voltage controlled oscillator 13 is divided by n, respectively, and the resulting signal is divided by n to the phase detector 3.
I added it to As a result, as is well known, the modulation sensitivity becomes (1/n) more than before synchronization, and the bandwidth of the PLL becomes narrower.
尚、切り替え時１位相検波器３の入出力特性はそのまま
の状態に保たれているので過渡現象は生じない。Incidentally, at the time of switching, the input/output characteristics of the 1-phase detector 3 are maintained as they are, so no transient phenomenon occurs.
第２図は本発明の実施例のブロック図、第３図は第２図
の動作説明図を示す。FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2.
尚、第３図の左側の符号は第２図中の同じ符号の部分の
波形を示す。ここで、２分周器２１．スイッチ２２は第
１の分周手段の構成部分、同期検出器４１は同期検出手
段４の構成部分、２分周器５１．スイッチ５２．インバ
ータ５３は第２の分周手段５の構成手段、抵抗ＲＩ”’
Ｒ３＋ Ｒ６＋ コンデンサＣ１演算増幅器６１はルー
プフィルタ６の構成部分を示す。Note that the symbols on the left side of FIG. 3 indicate the waveforms of the portions with the same symbols in FIG. Here, the frequency divider 21. The switch 22 is a component of the first frequency dividing means, the synchronization detector 41 is a component of the synchronization detection means 4, the frequency divider 51 . Switch 52. The inverter 53 is a component of the second frequency dividing means 5, and a resistor RI"'
R3+ R6+ Capacitor C1 Operational amplifier 61 represents a component of loop filter 6.
又、全図を通じて同一符号は同一対象物を示す。Also, the same reference numerals indicate the same objects throughout the figures.
以下、ｎ＝２として第３図を参照しながら第２図の動作
を説明する。The operation of FIG. 2 will be described below with reference to FIG. 3 assuming n=2.
（１１入力クロックとＶＣＯ出力とが非同期の場合先ず
、例えば第３図−■、■、■、■の左側に示す入力クロ
ックとＶＣＯ１３の出力とが非同期の場合にはスイッチ
２２．５２はａ側にあるので、入力クロックはそのまま
位相検波器１１に入力する。(If the input clock 11 and the VCO output are asynchronous, for example, if the input clock and the output of the VCO 13 shown on the left side of Figure 3 - ■, ■, ■, ■ are asynchronous, Therefore, the input clock is input to the phase detector 11 as is.
一方、ここにはＶＣＯ１３の出力がインバータ５３゜ス
イッチ５２を介して印加されているので、上記の入力ク
ロックは反転されたＶＣＯの出力で位相検波され、第３
図−〇の左側に示す検波出力が得られる。On the other hand, since the output of the VCO 13 is applied here via the inverter 53° switch 52, the above input clock is phase detected by the inverted output of the VCO, and the third
The detection output shown on the left side of Figure 2 is obtained.
この検波出力は抵抗Ｒ１＋ Ｒ１＋ Ｒ３＋ コンデン
サＣ１抵抗れ、演算増幅器６１で構成されたループフィ
ルタを通って位相差信号が抽出され、制御信号としてＶ
ＣＯ１３に加えられ、入力クロックと反転されたｖＣＯ
の出力との位相差が１例えば１８０°となる様に発振周
波数が制御される。This detection output is passed through a loop filter consisting of a resistor R1 + R1 + R3 + a capacitor C1, and an operational amplifier 61 to extract a phase difference signal, which is then output as a control signal to V.
vCO added to CO13 and inverted with the input clock
The oscillation frequency is controlled so that the phase difference with the output of is 1, for example, 180°.
尚、この時のループ帯域幅をＢＬとする。Note that the loop bandwidth at this time is BL.
（２） 入力クロックとＶＣＯ出力とが同期の場合衣
に、第３図−〇、■の左側に示す様に入力クロックとｖ
ＣＯ出力との位相差が１例えば１８０°になった時にｖ
ＣＯの出力は入力クロックに同期したと定められている
ので、同期検出器４１はこの状態を検出してスイッチ２
２．５２をａ側からｂ側に同時に切り替える。(2) When the input clock and VCO output are synchronized, the input clock and
When the phase difference with the CO output is 1, for example 180°, v
Since the output of CO is determined to be synchronized with the input clock, the synchronization detector 41 detects this state and switches switch 2.
2.Switch 52 from side a to side b at the same time.
これにより、位相検波器３には入力クロック及びＶＣＯ
の出力が２分周されたものが入力するが、この切り替え
の際には第３図に示す様に位相の不連続性はない。As a result, the phase detector 3 receives the input clock and the VCO.
The output obtained by dividing the frequency by two is input, but there is no phase discontinuity during this switching as shown in FIG.
ここで、ＰＬＬの帯域幅Ｂ、はＶＣＯの変調感度Ｋ。Here, the bandwidth B of the PLL is the modulation sensitivity K of the VCO.
が高（なれば広がり、低くなれば狭くなると従来例の項
で述べたが、入力クロフクの周波数を〃にすることによ
り公知の様に変調感度に０が〃になり。As mentioned in the conventional example section, if the frequency is high, it is wide, and if it is low, it is narrow. However, by setting the frequency of the input clock to , the modulation sensitivity becomes 0, as is known.
帯域幅ＢＬは狭くなる。Bandwidth BL becomes narrower.
しかも、演算増幅器６１の利得は（１）項、（２）項共
に切り替えずに同じ値になっているので、非同期状態か
ら同期状態に入った時にＰＬＬの帯域幅ＢＬを狭くして
も過渡現象は生じない。Moreover, since the gain of the operational amplifier 61 is the same value without switching both terms (1) and (2), even if the PLL bandwidth BL is narrowed when entering the synchronized state from the asynchronous state, transient phenomena will not occur. does not occur.
以上詳細に説明した様に本発明によればＰＬＬの帯域幅
を切り替えても過渡現象は生じないと云う効果がある。As described above in detail, the present invention has the effect that no transient phenomenon occurs even when the PLL bandwidth is switched.
第１図は本発明の原理ブロック図、 第２図は本発明の実施例のブロック図、図 第３図は第ソδ動作説明図、 第４図は従来例のブロック図、 第５図は第４図の動作説明図を示す。 図において、 ２は第１の分周手段、 ３は位相検波器、 ４は同期検出手段、 ５は第２の分周手段、 ６はループフィルタ、 １３は電圧制御発振器を示す。 ■ Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram of an embodiment of the present invention. Fig. 3 is an explanatory diagram of the operation of No. δ, Figure 4 is a block diagram of the conventional example. FIG. 5 shows an explanatory diagram of the operation of FIG. 4. In the figure, 2 is a first frequency dividing means; 3 is a phase detector, 4 is a synchronization detection means; 5 is a second frequency dividing means; 6 is a loop filter, 13 indicates a voltage controlled oscillator. ■
Claims (1)
力信号をｎ分周（ｎは正の整数）して出力し、又は直接
出力する第１の分周手段（２）と、該同期検出手段（４
）よりの切替信号の状態に対応して電圧制御発振器（１
３）の出力をｎ分周して出力し、又は直接出力する第２
の分周手段（５）と、該第１及び第２の分周手段（２、
５）の出力が同期状態に入ったことを検出した時に異な
る状態の切替信号を送出する同期検出手段（４）と、該
第２の分周手段（５）の出力を用いて該第１の分周手段
（２）の出力を位相検波する位相検波器（３）と、該位
相検波器の出力から位相差信号を抽出するループフィル
タ（６）と、該ループフィルタの出力によって該第１及
び第２の分周手段（２、５）の出力が同期する様に発振
周波数が制御される該電圧制御発振器（１３）とから構
成されることを特徴とするフェーズロックドループ回路
。a first frequency dividing means (2) that divides the input signal by n (n is a positive integer) and outputs the divided signal or directly outputs the divided signal according to the state of the switching signal from the synchronization detecting means (4); Synchronization detection means (4
) in response to the state of the switching signal from the voltage controlled oscillator (1
3), which divides the output by n and outputs it, or outputs it directly.
a frequency dividing means (5), and the first and second frequency dividing means (2,
synchronization detection means (4) that sends a switching signal of a different state when it detects that the output of 5) enters a synchronization state, and the output of the second frequency division means (5) to a phase detector (3) for phase detecting the output of the frequency dividing means (2); a loop filter (6) for extracting a phase difference signal from the output of the phase detector; A phase-locked loop circuit comprising the voltage controlled oscillator (13) whose oscillation frequency is controlled so that the outputs of the second frequency dividing means (2, 5) are synchronized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023224A JPH01198828A (en) | 1988-02-03 | 1988-02-03 | Phase locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023224A JPH01198828A (en) | 1988-02-03 | 1988-02-03 | Phase locked loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01198828A true JPH01198828A (en) | 1989-08-10 |
Family
ID=12104668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63023224A Pending JPH01198828A (en) | 1988-02-03 | 1988-02-03 | Phase locked loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01198828A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007036936A (en) * | 2005-07-29 | 2007-02-08 | Icom Inc | Clock reproduction circuit and clock reproduction method |
| JPWO2009001414A1 (en) * | 2007-06-22 | 2010-08-26 | 富士通マイクロエレクトロニクス株式会社 | PLL control circuit, PLL device, and PLL control method |
| JP2011519252A (en) * | 2008-04-29 | 2011-06-30 | クゥアルコム・インコーポレイテッド | System and method for controlling power consumption in a digital phase locked loop (DPLL) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5929812B2 (en) * | 1976-05-06 | 1984-07-23 | 新日本製鐵株式会社 | Method for detecting surface flaws on steel materials |
| JPS60189326A (en) * | 1984-03-08 | 1985-09-26 | Mitsubishi Electric Corp | Phase locked loop circuit |
| JPS6135601A (en) * | 1984-07-27 | 1986-02-20 | Matsushita Electric Ind Co Ltd | Modulator |
| JPS61184001A (en) * | 1985-02-08 | 1986-08-16 | Nippon Telegr & Teleph Corp <Ntt> | Pll modulator |
-
1988
- 1988-02-03 JP JP63023224A patent/JPH01198828A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5929812B2 (en) * | 1976-05-06 | 1984-07-23 | 新日本製鐵株式会社 | Method for detecting surface flaws on steel materials |
| JPS60189326A (en) * | 1984-03-08 | 1985-09-26 | Mitsubishi Electric Corp | Phase locked loop circuit |
| JPS6135601A (en) * | 1984-07-27 | 1986-02-20 | Matsushita Electric Ind Co Ltd | Modulator |
| JPS61184001A (en) * | 1985-02-08 | 1986-08-16 | Nippon Telegr & Teleph Corp <Ntt> | Pll modulator |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007036936A (en) * | 2005-07-29 | 2007-02-08 | Icom Inc | Clock reproduction circuit and clock reproduction method |
| JPWO2009001414A1 (en) * | 2007-06-22 | 2010-08-26 | 富士通マイクロエレクトロニクス株式会社 | PLL control circuit, PLL device, and PLL control method |
| JP4667525B2 (en) * | 2007-06-22 | 2011-04-13 | 富士通セミコンダクター株式会社 | PLL control circuit, PLL device, and PLL control method |
| JP2011519252A (en) * | 2008-04-29 | 2011-06-30 | クゥアルコム・インコーポレイテッド | System and method for controlling power consumption in a digital phase locked loop (DPLL) |
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